From: ixgbe <redacted>
Date: Tue, 11 Nov 2025 11:41:51 +0000 (+0800)
Subject: ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion (llama... 
X-Git-Tag: upstream/0.9.4.395~196
X-Git-Url: https://git.djapps.eu/?a=commitdiff_plain;h=6d94c37a9be7deadf6c3c5a1d40a0884aa8a7419;p=pkg%2Fggml%2Fsources%2Fggml

ggml-cpu : add RISC-V RVV (Zvfh) optimization for FP16 to FP32 conversion (llama/17161)

Signed-off-by: Wang Yang <redacted>
---

diff --git a/src/ggml-cpu/ggml-cpu.c b/src/ggml-cpu/ggml-cpu.c
index 086708ba..d8e3c48c 100644
--- a/src/ggml-cpu/ggml-cpu.c
+++ b/src/ggml-cpu/ggml-cpu.c
@@ -3274,6 +3274,13 @@ void ggml_cpu_fp16_to_fp32(const ggml_fp16_t * x, float * y, int64_t n) {
         __m128 y_vec = _mm_cvtph_ps(x_vec);
         _mm_storeu_ps(y + i, y_vec);
     }
+#elif defined(__riscv_zvfh)
+    for (int vl; i < n; i += vl) {
+        vl = __riscv_vsetvl_e16m1(n - i);
+        vfloat16m1_t vx = __riscv_vle16_v_f16m1((_Float16 *)&x[i], vl);
+        vfloat32m2_t vy = __riscv_vfwcvt_f_f_v_f32m2(vx, vl);
+        __riscv_vse32_v_f32m2(&y[i], vy, vl);
+    }
 #endif
 
     for (; i < n; ++i) {