--- /dev/null
+#include "common.cuh"
+#include "fwht.cuh"
+
+template <int N>
+__launch_bounds__(4*ggml_cuda_get_physical_warp_size(), 1)
+__global__ void fwht_cuda(const float * src, float * dst, const int64_t n_rows, const float scale) {
+ constexpr int warp_size = ggml_cuda_get_physical_warp_size();
+
+ const int64_t r = (int64_t) blockIdx.x * blockDim.y + threadIdx.y;
+
+ if (r >= n_rows) {
+ return;
+ }
+
+ src += r * N;
+ dst += r * N;
+
+ static constexpr int el_w = N / warp_size;
+ float reg[el_w];
+ const int lane = threadIdx.x;
+
+#pragma unroll
+ for (int i = 0; i < el_w; ++i) {
+ reg[i] = src[i * warp_size + lane] * scale;
+ }
+
+#pragma unroll
+ for (int h = 1; h < warp_size; h *= 2) {
+#pragma unroll
+ for (int j = 0; j < el_w; j++) {
+ const float val = reg[j];
+ const float val2 = __shfl_xor_sync(0xFFFFFFFF, val, h, warp_size);
+
+ reg[j] = (lane & h) == 0 ? val + val2 : val2 - val;
+ }
+ }
+
+#pragma unroll
+ for (int h = warp_size; h < N; h *= 2) {
+ const int step = h / warp_size;
+#pragma unroll
+ for (int j = 0; j < el_w; j += 2 * step) {
+#pragma unroll
+ for (int k = 0; k < step; k++) {
+ const float x = reg[j + k];
+ const float y = reg[j + k + step];
+
+ reg[j + k] = x + y;
+ reg[j + k + step] = x - y;
+ }
+ }
+ }
+
+#pragma unroll
+ for (int i = 0; i < el_w; ++i) {
+ dst[i * warp_size + lane] = reg[i];
+ }
+}
+
+void ggml_cuda_op_fwht(ggml_backend_cuda_context & ctx, const ggml_tensor * src, ggml_tensor * dst) {
+ GGML_ASSERT(ggml_are_same_shape(src, dst));
+ GGML_ASSERT(ggml_is_contiguous(src));
+ GGML_ASSERT(ggml_is_contiguous(dst));
+ const int n = src->ne[0];
+ const int64_t rows = ggml_nrows(src);
+
+ const float * src_d = (const float *) src->data;
+ float * dst_d = (float *) dst->data;
+
+ const int warp_size = ggml_cuda_info().devices[ggml_cuda_get_device()].warp_size;
+ GGML_ASSERT(n % warp_size == 0);
+ const int rows_per_block = 4;
+
+ const int64_t num_blocks = (rows + rows_per_block - 1) / rows_per_block;
+
+ cudaStream_t stream = ctx.stream();
+ dim3 grid_dims(num_blocks, 1, 1);
+ dim3 block_dims(warp_size, rows_per_block, 1);
+ const ggml_cuda_kernel_launch_params launch_params =
+ ggml_cuda_kernel_launch_params(grid_dims, block_dims, 0, stream);
+
+ const float scale = 1 / sqrtf(n);
+
+ switch (n) {
+ case 64:
+ {
+ ggml_cuda_kernel_launch(fwht_cuda<64>, launch_params, src_d, dst_d, rows, scale);
+ break;
+ }
+ case 128:
+ {
+ ggml_cuda_kernel_launch(fwht_cuda<128>, launch_params, src_d, dst_d, rows, scale);
+ break;
+ }
+ case 256:
+ {
+ ggml_cuda_kernel_launch(fwht_cuda<256>, launch_params, src_d, dst_d, rows, scale);
+ break;
+ }
+ case 512:
+ {
+ ggml_cuda_kernel_launch(fwht_cuda<512>, launch_params, src_d, dst_d, rows, scale);
+ break;
+ }
+ default:
+ GGML_ABORT("fatal error");
+ }
+}
#include "ggml-cuda/diagmask.cuh"
#include "ggml-cuda/diag.cuh"
#include "ggml-cuda/fattn.cuh"
+#include "ggml-cuda/fwht.cuh"
#include "ggml-cuda/getrows.cuh"
#include "ggml-cuda/im2col.cuh"
#include "ggml-cuda/mmf.cuh"
bool use_batched_cublas_bf16 = src0->type == GGML_TYPE_BF16 && bf16_mma_hardware_available(cc);
bool use_batched_cublas_f32 = src0->type == GGML_TYPE_F32;
+ const int32_t hint = ggml_get_op_params_i32(dst, 1);
+ if (hint == GGML_HINT_SRC0_IS_HADAMARD) {
+ GGML_ASSERT(!split);
+ ggml_cuda_op_fwht(ctx, src1, dst);
+ return;
+ }
+
if (!split && use_mul_mat_vec_f) {
// the custom F16 vector kernel can be used over batched cuBLAS GEMM
// but this is only faster for GPUs without tensor cores or with a thin src0 matrix (particularly KQV in attention)
test_cases.emplace_back(new test_mul_mat_hadamard(GGML_TYPE_F32, GGML_TYPE_F32, 64, 1, 64));
test_cases.emplace_back(new test_mul_mat_hadamard(GGML_TYPE_F32, GGML_TYPE_F32, 256, 1, 256));
test_cases.emplace_back(new test_mul_mat_hadamard(GGML_TYPE_F32, GGML_TYPE_F32, 128, 32, 128));
+ test_cases.emplace_back(new test_mul_mat_hadamard(GGML_TYPE_F32, GGML_TYPE_F32, 128, 4, 128, {2, 3}));
#if 0
// > 4GB A matrix. Too slow to be enabled by default.