ggml-et: Initial ET backend (#24179)

* ggml-et: Add performance logging

* ggml-et: Quants helpers

* ggml-et: Add MUL_MAT kernel

* ggml-et: Add ROPE kernel

* ggml-et: Add RMS_NORM kernel

* ggml-et: Add GLU kernel

* ggml-et: Add SOFT_MAX kernel

* ggml-et: Add GET_ROWS kernel

* ggml-et: Add CONT kernel

* ggml-et: Add SET_ROWS kernel

* ggml-et: Add MUL_MAT_ID kernel

* ggml-et: Build et kernels as part of ggml

* ggml-et: Embed kernels with fs fallback

* ggml-et: Build fixes

* ggml-et: Add MUL_MAT F32xF32 op

* ggml_et: Add MUL_MAT_ID op

* ggml-et: Disable offloading for debug

* ggml-et: Refactor out block ops

* ggml-et: ggml backend API changes

* ggml-et: Add RESHAPE/TRANSPOSE to supported

* ggml-et: Add CONT_F16

* ggml-et: Add supported ops doc

* gglm-et: Initial doc

* ggml-et: Remove  runtime import hacks

We can now import the runtime by a simple find_package(), so we
can cleanup the CMakeLists.txt.

* ggml-et: Fix GET_ROWS kernel

Fix lost batch dimension.

Also clean vibe-comments.

* ggml-et: Fix SET_ROWS kernel

Remove incorrect broadcasting guard.

* ggml-et: Use custom instruction for fp32->fp16

* ggml-et: Vectorize set_rows fp32->fp16

* ggml-et: Fix ROPE kernel (yarn)

ggml-et: fix et_logf

WIP: Fix ramp

WIP: fix ROPE!

* ggml-et: Better sinf

* ggml-et: Fix SOFT_MAX

Add `max_bias` and `sink` support.

* ggml-et: Fix CONT

Reorder from contiguous write to read with atomic stores.

* ggml-et: Fix elmap kernel

Remainder handlin

* ggml-et: Fix MUL_MAT MUL_MAT_ID remainders

* ggml-et: Fix ET-SOC reference

* ggml-et: Fix embed kernels scripts for old python

This allows GGML-ET to build on pre-3.8 python.

* Add sysemu support with compile time flag `-DGGML_ET_SYSEMU=ON` (#6)

* Example using ET-Soc-1 emulator configuration

Example usage:
```bash
cmake -B build -DGGML_CUDA=OFF -DGGML_ET=ON -DLLAMA_CURL=OFF -DGGML_CCACHE=ON
cmake --build build --config Release -j $(nproc)

time ./build/bin/test-backend-ops

./build/bin/llama-server \
    --model Qwen3-0.6B-Q8_0.gguf \
    --alias Qwen3-0.6B-Q8_0 \
    -fa 0 \
    --ctx-size 1024 \
    --no-warmup \
    --host 127.0.0.1 \
    --port 8080
```

* build: proper dep tracking for kernels

* support host using MOLD linker

* initial multi core GET_ROW F32 implementation

* vectorized q8 dequant

* wip: cland warning clenaups and initial logging refactor

* wip: message default message cleanup

* chore: message cleanups

* cmake cleanup

* migrate to use platform provided functions

* cmake back into subdir

* support et_print() in kernels

* fix: repair kernel building

* perf: operations run async by default

* debug: proper kernel dep tracking and error detection on kenrel launch

* fix: kernel binary dep tracking and fixing get_rows_f32 erroring

* perf: back to doing async kernel runs by default

* perf: vectorize and parallel device memset

* merge matmul work

* misc: align allocation and enable all offload

* misc: delete deadcode and respect memory limits

* fix: repair tensor debug print

* fix: loosen RMS_NORM op percision

* feat: Q4_0 GET_ROWS

* perf: FP32 MUL_MAT using TensorFMA

* update limitations

* perf: redue L1 load in compute_block_dot_product_q8_0

* feat: save kernel mapping (name to id) when profiling is enabled

* chore: memops cleanup

* perf: parallelize softmax by rows

* perf: vectorize 2nd phase of softmax

* perf: ban GET_ROWS from offloaded

* perf: vectorize and non-atomic for eltwise ops and sub support

* perf: vectorize normal rope

* perf: glu runs in parallel

* merge: manually merge saqib's work on kernel fixes

* perf: more vectorized RoPE

* perf: parallelize mul_mat_id

* perf: parallelize set_rows_f32

* perf: vectorize softmax

* feat: support kernel fusion and fuse RMS_NORM + MUL

* fix: mostly resolve test-backend-ops failure in SOFT_MAX and ROPE

* fix: bump max rope dims for gemma

* feat: GeGLU and SCALE support to fully offload Gemma

* perf: faster device memset

* feat: get_rows supporting Q4_K and avoid cont cache coherent issues

* better F32 MM

* feat: NORM for ET backend

* feat: SQR for ET backend

* feat: UNARY on ET

* feat: el_map support broadcasting for ET

* feat: SUM_ROWS in ET backend

* feat: more ops in ET backend

* feat: WKV* operators in ET backend

* perf: parallelize operators across cacheline instead of row

* perf: parallelize get_rows on cacheline

* wip: baseline FlashAttention for ET backend

* wip: enough FA and CPY f32->f16 to run llama 3.1 fully offloaded with FA on

* feat: f16 x f16 -> f32 MM using matrix engine

* wip: f16 FlashAttention using matrix engine

* wip: clean up

* feat: barriers

* perf: optimize FA_F16 in ET

* perf: vectorize pack_k_for_transpose16

* perf: prefetch next loop matrix tile

* perf: FlashAttention 2nd MM uses TensorFMA and optimizations

* cleanup: flashattention reorg

* perf: optimizations and fixes

* feat: L2SCP API and make FlashAttention support DV = 256 for gemma

* perf: parallelize norms beyond single row

* feat: GATED_DELTA_NET support and relaxed L2_NORM requirment

* feat: loosen RMS_NORM, NORM, ROPE contingous req too

* feat: repeat supports brocasting on dim 0 and loosen cont check

* feat: FILL and DIAG operator

* feat: loosen UNARY support chcek

* feat: TRI support

* feat: SOLVE_TRI support

* feat: basic SET support

* feat: loosen CONT req

* perf: fp16_to_fp32 use ASM

* feat: IMROPE support

* feat: PAD support

* feat: global barrier

* fix: view must live on the same backend as backing tensor

* feat: relax CONCAT in ET backend

* feat: dead simple CUMSUM implementation

* feat: basic SSM_CONV support

* feat: loosen CONCAT req

* feat: relax GATED_DELTA_NET and add SET support proper

* cleanup: cleanup LCM math

* feat: SWIGLU single input

* feat: SSM_SCAN support

* feat: el_map supports non aligned tensors in best effort

* feat: basic GROUP_NORM support

* feat: loosen MUL_MAT capablities slightly

* feat: loosen MUL_MAT and GET_ROWS and add IM2COL

* feat: special case for softmax 1x1x1x1

* feat: loosen SOFT_MAX req in ET backend

* fix: el_map unaligned acse fixes

* perf: optimize zero_acc_vec in flash_attn_ext_f16_me

* perf: use hart 1 for packing in MM and FA for FP16

* feat: kernel semaphore

* perf: better instruction sequence in FlashAttention

* fix: gated_delta_net with proper masking

* perf: better parallelization for GATED_DELTA_NET

* perf: parallelize SSM_CONV over nr

* perf: vectorize SSM_CONV

* perf: optimize MUL_MAT for q8

* feat: support Gemma 4

* fix: support multi-device

* feat: broader GLU support

* feat: unary ops supports view

* fix: repair fp16 MM using matrix engine

* perf: handle large N GEMV better

* perf: better q8_0 MM

* perf: better set_rows

* add back deleted files

* fix: repair after merge

* feat: POC version of uberkernel

* feat: RMS_NORM in uberkernel

* feat: add more kernels into usage

* chore: clean up uberkernel compilation

* perf: faster flash attention

* perf: opt flash attention for large seq length

* feat: loosen op bounds. clamp and mean support

* perf: vectorize ssm_scan

* perf: slightly faster FA

* perf: FlashAttention parallel MM and load

* perf: fuse Q8 MM and ADD

* feat: basic conv kernel for ET

* softMAx_test

* set_rows_f32

* get_rows and cont

* testing

* set_rows_exp

* Junk addition

* Narrowing the issue

* Update flash_attn_ext_f16_me.c

Focusing FA_ext_f16_me

* test

* Eviction updated

* Detailed cache eviction debug

* mulmat

* removeal of `BUILD_FOR_UBERKERNEL` flag

* cleaning...

* fix: balance FCC0 count

* feat: implement mul_mat and mul_mat_id for Q4_0 type

* optimize uberkernel plan upload

* add mul_mat q4 into uberkernel

* enable gating flush to just uberkernel

* update docs for ET

* update op support for ET

* et-backend: optimize Q4_0 and Q8_0 mul_mat_id row accumulations

* et-backend: specialize mul_mat_id kernels for Q4_0 and Q8_0

* et-backend: fix RoPE YaRN corr_dim formula and handle degenerate inputs

* test-backend-ops: add DeepSeek-V2-Lite RoPE test coverage

* et-backend: add Q4_0 mul_mat matrix-engine kernel using TensorFMA32

* et-backend: vectorize Q4_0 matrix-engine dequantization

* et-backend: support hybrid matrix/vector engine execution for Q4_0 mul_mat tail

* et-backend: run partial-N tiles on matrix engine for Q4_0 mul_mat

* et-backend: route Q4_0 mul_mat N < 53 to vecdot for better prefill latency

* Update uberkernel.c

* Update unary_f32.c

* gemma 4

* bisect gemma4: enable scale_f32 only

* bisect gemma4: +rms_norm_f32

* bisect gemma4: +rms_norm_mul_f32

* bisect gemma4: disable rms_norm_mul_f32 -- BREAKS OUTPUT

* bisect gemma4: +rope_f32 (skip rms_norm_mul)

* bisect gemma4: +el_map_f32

* bisect gemma4: +softmax_f32

* bisect gemma4: +get_rows_f32

* bisect gemma4: +glu_f32

* bisect gemma4: +mul_mat_f32 +mul_mat_f32_matrix_engine

* bisect gemma4: +mul_mat_f16 +mul_mat_f16_matrix_engine

* bisect gemma4: +mul_mat_Q8_0 +mul_mat_Q4_0

* bisect gemma4: +flash_attn_ext_f32 +flash_attn_ext_f16_me

* bisect gemma4: +mul_mat_id_f32

* bisect gemma4: +sum_rows_f32

* bisect gemma4: +cont_f16

* bisect gemma4: +fill_f32

* bisect gemma4: +unary_f32 (all ops re-enabled except rms_norm_mul)

* Update rms_norm_mul_f32.c

* bisect2 gemma4 n64: +scale_f32 only

* bisect2 gemma4 n64: +rms_norm_f32 +rope_f32

* bisect2 gemma4 n64: +rms_norm_mul_f32 (with ET_UBERKERNEL eviction fix)

* bisect2 gemma4 n64: +el_map +get_rows +glu +softmax (skip rms_norm_mul)

* bisect2 gemma4 n64: all ops enabled except rms_norm_mul

* bisect2 n64: test unary+cont+fill+sum_rows (no mul_mat/flash_attn)

* bisect2 n64: +mul_mat_f32 +mul_mat_f32_matrix_engine

* bisect2 n64: +mul_mat_f16 +mul_mat_f16_matrix_engine

* bisect2 n64: +mul_mat_Q8_0 +mul_mat_Q4_0

* bisect2 n64: +mul_mat_Q8_0 only (disable Q4_0)

* bisect2 n64: +mul_mat_Q4_0 only (Q8_0 breaks)

* bisect2 n64: +mul_mat_id +flash_attn_ext (skip Q8_0)

* run-3: matmul + rms_norm_mul

* run-4

* Revert "run-4"

* run5

* changes after cleanup

* cleanup before upstream

* restrict changes into ET backend

* move kernel embedding from Python to CMake

* move uberkernel gen into CMake

* apply clang format

* update CMake style

* update to match C and C++ style

* use source ggml and quant headers instead of ET's

* MROPE support

* absorb view ops into same branch as none

* fix bad rebase

* add marty1885 to codeowners

* oops

* remove redundant newline

* fix CI editor warnings

---------

Co-authored-by: Vidas <redacted>
Co-authored-by: Gianluca Guida <redacted>
Co-authored-by: Gianluca Guida <redacted>
Co-authored-by: ubergarm <redacted>
Co-authored-by: SaqibAkram-10xE <redacted>
Co-authored-by: Rehan Qasim <redacted>

diff --git a/CODEOWNERS b/CODEOWNERS
index 46fd518b7e51011a155360ec73a4bd65f76c0611..2e30839ba0a8b76a4c5dee709a75a07a59c86d4b 100644 (file)
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -63,6 +63,7 @@
 /ggml/src/ggml-cuda/fattn-wmma*         @IMbackK
 /ggml/src/ggml-hexagon/                 @ggml-org/ggml-hexagon
 /ggml/src/ggml-hip/                     @IMbackK
+/ggml/src/ggml-et/                      @marty1885
 /ggml/src/ggml-impl.h                   @ggerganov
 /ggml/src/ggml-metal/                   @ggml-org/ggml-metal
 /ggml/src/ggml-opencl/                  @ggml-org/ggml-opencl

diff --git a/docs/backend/ET.md b/docs/backend/ET.md
new file mode 100644 (file)
index 0000000..8d9ba12
--- /dev/null
+++ b/docs/backend/ET.md
@@ -0,0 +1,177 @@
+# llama.cpp for ET
+
+- [Background](#background)
+- [Limitations](#limitations)
+- [Build](#build)
+- [Develop](#develop)
+- [Roadmap](#roadmap)
+
+
+## Background
+
+**ET** is a llama.cpp backend targeting the fully open source manycore
+RISC-V accelerator platform [ET-SOC](https://github.com/aifoundry-org/et-man).
+
+
+## Limitations
+
+The ET backend runs several of the major OSS models with some limitations:
+
+- Only limited set of operations is supported (check [../ops.md](../ops.md)
+  and [../ops/ET.csv](../ops/ET.csv)).
+- Only `q8_0`, `q4_0` (and partially `fp16`, `q4_K`) quantization is supported.
+- Only one llama.cpp instance can use device at the same time (current firmware
+  limitation).
+- Limited (but working) MoE model support
+
+As a result of the above, only select models can run fully on ET-SOC
+(you can actually run any model llama.cpp supports, but some/most operations
+will likely fallback to CPU backend).
+
+Fully supported models:
+- Qwen3 models (without MoE), e.g.
+  [ggml-org/Qwen3-0.6B-GGUF:q8_0](https://huggingface.co/ggml-org/Qwen3-0.6B-GGUF/blob/main/Qwen3-0.6B-Q8_0.gguf) or
+  [ggml-org/Qwen3-14B-GGUF:q8_0](https://huggingface.co/ggml-org/Qwen3-14B-GGUF/blob/main/Qwen3-14B-Q8_0.gguf).
+- Llama3.2 (1B/3B), e.g.
+  [lmstudio-community/Llama-3.2-1B-Instruct-GGUF:q8_0](https://huggingface.co/lmstudio-community/Llama-3.2-1B-Instruct-GGUF/blob/main/Llama-3.2-1B-Instruct-Q8_0.gguf).
+- SmolLM2, e.g.
+  [unsloth/SmolLM2-135M-Instruct-GGUF:q8_0](https://huggingface.co/unsloth/SmolLM2-135M-Instruct-GGUF/blob/main/SmolLM2-135M-Instruct-Q8_0.gguf)
+- Llama 3.1 model family.
+- RWKV v7 model family.
+- TinyLLaMA
+
+
+## Build
+
+### I. Prerequisites
+
+1. **Install custom RISC-V toolchain** - Follow instructions at:
+   [https://github.com/aifoundry-org/riscv-gnu-toolchain/tree/et/aifoundry](https://github.com/aifoundry-org/riscv-gnu-toolchain/tree/et/aifoundry)
+
+2. **Install ET platform** - Follow instructions at:
+   [https://github.com/aifoundry-org/et-platform](https://github.com/aifoundry-org/et-platform)
+
+Both should be installed to `/opt/et` (or set `ET_TOOLCHAIN` and `ET_PLATFORM`
+environment variables accordingly).
+
+```sh
+# Set toolchain and ET platform path (/opt/et is default)
+export ET_TOOLCHAIN=/opt/et
+export ET_PLATFORM=/opt/et
+```
+
+### II. Build llama.cpp
+
+Check out llama.cpp with ET backend (this should checkout `et` branch):
+
+```sh
+git clone https://github.com/aifoundry-org/llama.cpp
+cd llama.cpp
+```
+
+Build:
+
+```sh
+cmake -B build -DGGML_ET=ON
+cmake --build build --config Release
+# Optionally:
+# cmake --install build
+```
+
+Build targeting sysemu backend instead of physical hardware:
+```sh
+cmake -B build -DGGML_ET=ON -DGGML_ET_SYSEMU=ON
+cmake --build build --config Release
+```
+
+### III. Run
+
+Run llama.cpp binaries as usual. (Of course, please make sure you have the
+ET-SOC device installed and kernel driver loaded).
+
+```sh
+llama-cli -m mymodel.gguf
+# or
+llama-server -hf ggml-org/Qwen3-8B-GGUF:q8_0
+```
+
+If you want to run llama.cpp binaries (e.g. `llama-cli`) inside docker
+container, you should let it access device files:
+
+```sh
+docker run \
+    --device=/dev/et0_mgmt:/dev/et0_mgmt \
+    --device=/dev/et0_ops:/dev/et0_ops \
+    ...
+```
+
+## Develop
+
+Compute kernels are developed within `ggml/src/ggml-et/et-kernels` folder.
+Build is performed using custom RISC-V GNU toolchain and is managed by cmake.
+At the moment kernels are build as baremetal elf files, without
+standard lib or any other dependencies. All the yummy parts are written
+in inline assembler.
+
+Most kernels are very naive with lots of low hanging fruits left:
+
+> [!IMPORTANT]
+> Several assembly instructions emmited by the compiler are not implemented
+> in hardware and software emulation in firmware is not ready yet.
+> Eventually firmware will transparently trap unimplemented instructions
+> and will emulate them inside exception handler. Until then, kernel
+> build process includes step that checks compiled kernels and fails if any unimplemented
+> instructions are found. Problematic ones follow:
+> `FDIV.PI`, `FDIVU.PI`, `FREMU.PI`, `FREM.PI`, `FDIV.S`, `FDIV.PS`, `FSQRT.S`, `FSQRT.PS`, `FRSQ.PS`, `FSIN.PS`
+>  and (long cast) `FCVT.S.L`, `FCVT.S.LU`, `FCVT.L.S`, `FCVT.LU.S`
+> What this means, is that for now you should avoid doing any division involving floats,
+> any trigonometry or casting longs into floats.
+> Some workarounds are implemented in `math_fp.h` (`et_fdiv`, `et_powf` etc) and
+> long casting (presuming longs are small enough to fit into 32bits) can be
+> done via `int` like `a = (float)(int)(b)`.
+
+> [!TIP]
+> There are some slightly higher level helpers (abstracting more
+> complex instructions like tensor extension or synchronization primitives)
+> inside `et_platform`, directory `et-common-libs/include/etsoc/isa/`. It was
+> originally developed for firmware needs and is not included into compute
+> kernel build process. Feel free to take ideas/code from there or try linking
+> it in.
+
+Before commiting any changes to operations and/or kernels, don't forget
+to update supported ops reports (instructions at `docs/ops.md`).
+
+When logging is enabled (e.g. by setting `--log-file` cli param),
+each compute kernel run outputs a line with
+pipe-delimited key-value pairs containing kernel level performance infomation.
+Line is prefixed with `ET_PERF`:
+
+```
+ET_PERF|op=MUL_MAT|kernel=mul_mat_f32_Q8_0xf32|duration_us=3112|tensor=Qcur-0|shape=[4096,2,1,1]|start_us=48437862009|end_us=48437865121|flops=67100672
+ET_PERF|op=ROPE|kernel=rope_f32|duration_us=9266|tensor=Qcur-0|shape=[128,32,2,1]|start_us=48437865128|end_us=48437874394|mode=0x0|n_dims=128|freq_base=500000.00|freq_scale=1.00
+```
+Keys depend on the operation, but some are always present.
+`flops` in this case counts effective floating point operations and not floating
+point operations per second.
+
+You can enable ET-SOC runtime level ET-SOC profiling by setting environment
+variable `GGML_ET_PROFILE` to a path. Profiling/tracing results will be written
+to `GGML_ET_PROFILE/et_runtime_trace.json` and `GGML_ET_PROFILE/kernel_map` on exit.
+
+### Uberkernel
+
+The in-knernel implementaiton of device dispatch/kernel fusion. The ET SDK has a non-trivial op-to-op gap. `Uberkernel` (name taken from the original Esperanto AI's compiler)
+dispatches multiple already existing kernel implementations with device side synchronization. Due to the processor's design, there is no natural memory visibility
+horizon between sub-kernel invocations. This makes uberkernel much more difficult to develop and debug. Currently Uberkerel is hidden begind the
+`GGML_ET_UBERKERNEL` environment variable and is disabled by default. Setting it to 1 enables it and provides significant performance improvements but is only
+validated for the LLaMA 3.2 model family and Qwen 3.5.
+
+## Roadmap
+
+As of writing the documentation the ET backend is capable of running most models and smaller ones at usable speed given the low power profile of the processor. We'd
+address the following capabilities in the future:
+
+* Enable Uberkernel for all models
+* More oprtator support
+* Better TTS model support
+* Enable more quantization format support

diff --git a/docs/ops.md b/docs/ops.md
index bab6d8ff221ca50f215214c2573437a11a288274..f138753854afc356ee63902b6a4a3209b860e198 100644 (file)
--- a/docs/ops.md
+++ b/docs/ops.md
@@ -12,112 +12,112 @@ Legend:
 - 🟡 Partially supported by this backend
 - ❌ Not supported by this backend
 
-| Operation | BLAS | CANN | CPU | CUDA | MTL | OpenCL | SYCL | Vulkan | WebGPU | ZenDNN | zDNN |
-|-----------|------|------|------|------|------|------|------|------|------|------|------|
-|                              ABS | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                              ACC | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ |
-|                              ADD | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             ADD1 | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
-|                           ADD_ID | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                           ARANGE | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                           ARGMAX | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                          ARGSORT | ❌ | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             CEIL | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                            CLAMP | ❌ | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                        COL2IM_1D | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|                           CONCAT | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             CONT | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ |
-|                          CONV_2D | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                       CONV_2D_DW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                          CONV_3D | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|                CONV_TRANSPOSE_1D | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                CONV_TRANSPOSE_2D | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                              COS | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                      COUNT_EQUAL | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                              CPY | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
-|               CROSS_ENTROPY_LOSS | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|          CROSS_ENTROPY_LOSS_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|                           CUMSUM | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             DIAG | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                    DIAG_MASK_INF | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                              DIV | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                              DUP | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                              ELU | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                              EXP | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                            EXPM1 | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             FILL | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                   FLASH_ATTN_EXT | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
-|                            FLOOR | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                  GATED_DELTA_NET | ❌ | ❌ | ✅ | ❌ | 🟡 | ❌ | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                GATED_LINEAR_ATTN | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|                            GEGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                        GEGLU_ERF | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                      GEGLU_QUICK | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             GELU | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                         GELU_ERF | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                       GELU_QUICK | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                         GET_ROWS | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ |
-|                    GET_ROWS_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
-|                       GROUP_NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                      HARDSIGMOID | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                        HARDSWISH | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                           IM2COL | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                        IM2COL_3D | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                          L2_NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                       LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | ❌ | ❌ | ❌ |
-|                              LOG | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             MEAN | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                              MUL | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                          MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 |
-|                 MUL_MAT_HADAMARD | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                       MUL_MAT_ID | ❌ | 🟡 | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | 🟡 | 🟡 | ❌ |
-|                              NEG | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                   OPT_STEP_ADAMW | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ |
-|                     OPT_STEP_SGD | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ |
-|                         OUT_PROD | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ | 🟡 | ❌ | ❌ | ❌ | 🟡 |
-|                              PAD | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ |
-|                   PAD_REFLECT_1D | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|                          POOL_1D | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ |
-|                          POOL_2D | ❌ | 🟡 | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                            REGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             RELU | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                           REPEAT | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                      REPEAT_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                         RMS_NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                    RMS_NORM_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                             ROLL | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                             ROPE | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                        ROPE_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                            ROUND | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                        RWKV_WKV6 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                        RWKV_WKV7 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                            SCALE | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                              SET | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ |
-|                         SET_ROWS | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
-|                              SGN | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                          SIGMOID | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             SILU | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                        SILU_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ |
-|                              SIN | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                         SOFTPLUS | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                         SOFT_MAX | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                    SOFT_MAX_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ |
-|                        SOLVE_TRI | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ |
-|                              SQR | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                             SQRT | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ |
-|                         SSM_CONV | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                         SSM_SCAN | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | 🟡 | ✅ | ❌ | ❌ |
-|                             STEP | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                              SUB | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                              SUM | ❌ | 🟡 | ✅ | 🟡 | 🟡 | ❌ | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
-|                         SUM_ROWS | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ |
-|                           SWIGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                       SWIGLU_OAI | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                             TANH | ❌ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|               TIMESTEP_EMBEDDING | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ |
-|                            TOP_K | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | 🟡 | 🟡 | ✅ | ❌ | ❌ |
-|                              TRI | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                            TRUNC | ❌ | ❌ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                          UPSCALE | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
-|                            XIELU | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ |
+| Operation | BLAS | CANN | CPU | CUDA | ET | MTL | OpenCL | SYCL | Vulkan | WebGPU | ZenDNN | zDNN |
+|-----------|------|------|------|------|------|------|------|------|------|------|------|------|
+|                              ABS | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                              ACC | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | ð\9f\9f¡ | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                              ADD | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             ADD1 | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
+|                           ADD_ID | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                           ARANGE | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                           ARGMAX | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                          ARGSORT | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                             CEIL | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                            CLAMP | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | 🟡 | ✅ | ❌ | ❌ |
+|                        COL2IM_1D | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|                           CONCAT | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             CONT | ❌ | 🟡 | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ |
+|                          CONV_2D | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                       CONV_2D_DW | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                          CONV_3D | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|                CONV_TRANSPOSE_1D | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                CONV_TRANSPOSE_2D | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                              COS | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | ð\9f\9f¡ | â\9c\85 | â\9d\8c | â\9d\8c |
+|                      COUNT_EQUAL | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                              CPY | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
+|               CROSS_ENTROPY_LOSS | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|          CROSS_ENTROPY_LOSS_BACK | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|                           CUMSUM | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                             DIAG | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                    DIAG_MASK_INF | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ |
+|                              DIV | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                              DUP | ❌ | ✅ | ✅ | 🟡 | ❌ | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ | ❌ |
+|                              ELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                              EXP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                            EXPM1 | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             FILL | ❌ | ❌ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                   FLASH_ATTN_EXT | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
+|                            FLOOR | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                  GATED_DELTA_NET | ❌ | ❌ | ✅ | ❌ | ✅ | 🟡 | ❌ | ✅ | 🟡 | ✅ | ❌ | ❌ |
+|                GATED_LINEAR_ATTN | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|                            GEGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                        GEGLU_ERF | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                      GEGLU_QUICK | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             GELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                         GELU_ERF | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                       GELU_QUICK | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                         GET_ROWS | ❌ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | ✅ | ✅ | 🟡 | ❌ | ❌ |
+|                    GET_ROWS_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ |
+|                       GROUP_NORM | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                      HARDSIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                        HARDSWISH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                           IM2COL | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                        IM2COL_3D | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                          L2_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                       LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | ❌ | 🟡 | ❌ | ✅ | 🟡 | ❌ | ❌ | ❌ |
+|                              LOG | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                             MEAN | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                              MUL | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                          MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 |
+|                 MUL_MAT_HADAMARD | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                       MUL_MAT_ID | ❌ | 🟡 | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | 🟡 | 🟡 | ❌ |
+|                              NEG | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ |
+|                   OPT_STEP_ADAMW | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                     OPT_STEP_SGD | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                         OUT_PROD | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ | ❌ | 🟡 | ❌ | ❌ | ❌ | 🟡 |
+|                              PAD | ❌ | 🟡 | ✅ | 🟡 | ❌ | 🟡 | 🟡 | 🟡 | ✅ | ✅ | ❌ | ❌ |
+|                   PAD_REFLECT_1D | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|                          POOL_1D | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c |
+|                          POOL_2D | â\9d\8c | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                            REGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             RELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                           REPEAT | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                      REPEAT_BACK | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                         RMS_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                    RMS_NORM_BACK | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                             ROLL | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                             ROPE | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                        ROPE_BACK | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                            ROUND | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                        RWKV_WKV6 | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                        RWKV_WKV7 | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                            SCALE | â\9d\8c | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                              SET | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                         SET_ROWS | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
+|                              SGN | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                          SIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                             SILU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                        SILU_BACK | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                              SIN | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9d\8c | â\9c\85 | ð\9f\9f¡ | â\9c\85 | â\9d\8c | â\9d\8c |
+|                         SOFTPLUS | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                         SOFT_MAX | ❌ | 🟡 | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                    SOFT_MAX_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | 🟡 | ✅ | ❌ | ❌ | ❌ |
+|                        SOLVE_TRI | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | 🟡 | ✅ | ✅ | ❌ | ❌ |
+|                              SQR | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | ❌ |
+|                             SQRT | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | ð\9f\9f¡ | â\9c\85 | â\9d\8c | â\9d\8c |
+|                         SSM_CONV | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                         SSM_SCAN | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | ð\9f\9f¡ | ð\9f\9f¡ | â\9c\85 | â\9d\8c | â\9d\8c |
+|                             STEP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                              SUB | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                              SUM | ❌ | 🟡 | ✅ | 🟡 | ❌ | 🟡 | ❌ | 🟡 | 🟡 | 🟡 | ❌ | ❌ |
+|                         SUM_ROWS | â\9d\8c | â\9c\85 | â\9c\85 | ð\9f\9f¡ | â\9d\8c | â\9c\85 | ð\9f\9f¡ | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                           SWIGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                       SWIGLU_OAI | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                             TANH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|               TIMESTEP_EMBEDDING | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c | â\9d\8c |
+|                            TOP_K | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | ð\9f\9f¡ | ð\9f\9f¡ | â\9c\85 | â\9d\8c | â\9d\8c |
+|                              TRI | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                            TRUNC | ❌ | ❌ | ✅ | 🟡 | 🟡 | ✅ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ |
+|                          UPSCALE | â\9d\8c | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9d\8c | â\9c\85 | ð\9f\9f¡ | â\9c\85 | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |
+|                            XIELU | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9d\8c | â\9d\8c | â\9c\85 | â\9c\85 | â\9d\8c | â\9d\8c |

diff --git a/docs/ops/ET.csv b/docs/ops/ET.csv
new file mode 100644 (file)
index 0000000..91774c5
--- /dev/null
+++ b/docs/ops/ET.csv
@@ -0,0 +1,16114 @@
+"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name"
+"ET","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","EXPM1","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","EXPM1","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","SOFTPLUS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","SOFTPLUS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","FLOOR","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","FLOOR","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","CEIL","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","CEIL","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","ROUND","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","ROUND","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","TRUNC","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","ET"
+"ET","TRUNC","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","ET"
+"ET","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","SIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","GELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","GELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","EXPM1","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","EXPM1","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","SOFTPLUS","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
+"ET","SOFTPLUS","type=f16,ne_a=[5,7,11,13],v=1","support","0","no","ET"
+"ET","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","no","ET"
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+"ET","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=3,d0=1,d1=1,d2=1,v=1","support","0","no","ET"
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+"ET","IM2COL_3D","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,10,3],ne_kernel=[3,3,3,3],IC=1,s0=1,s1=1,s2=1,p0=0,p1=0,p2=3,d0=3,d1=3,d2=1,v=1","support","0","no","ET"
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+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=4,ID=8,IH=8,IW=8,OC=8,KD=1,KH=1,KW=1,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f32","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=1,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=1,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=1,s1=1,s2=1,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=0,p1=0,p2=0,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=3,KW=3,s0=2,s1=2,s2=2,p0=1,p1=1,p2=1,d0=2,d1=2,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=2,IC=3,ID=18,IH=22,IW=20,OC=4,KD=3,KH=1,KW=5,s0=2,s1=1,s2=1,p0=2,p1=0,p2=1,d0=1,d1=1,d2=2,type_kernel=f16","support","0","no","ET"
+"ET","CONV_3D","N=1,IC=4,ID=8,IH=8,IW=8,OC=8,KD=1,KH=1,KW=1,s0=1,s1=1,s2=1,p0=0,p1=0,p2=0,d0=1,d1=1,d2=1,type_kernel=f16","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","no","ET"
+"ET","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","no","ET"
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+"ET","CONT","type=f32,ne=[2,1,3,5],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f32,ne=[2,3,5,7],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f32,ne=[1,4,4,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f32,ne=[1,8,17,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f32,ne=[10,10,10,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=i32,ne=[2,1,1,1],use_view_slice=1","support","0","no","ET"
+"ET","CONT","type=i32,ne=[2,1,3,5],use_view_slice=1","support","0","no","ET"
+"ET","CONT","type=i32,ne=[2,3,5,7],use_view_slice=1","support","0","no","ET"
+"ET","CONT","type=i32,ne=[1,4,4,1],use_view_slice=1","support","0","no","ET"
+"ET","CONT","type=i32,ne=[1,8,17,1],use_view_slice=1","support","0","no","ET"
+"ET","CONT","type=i32,ne=[10,10,10,1],use_view_slice=1","support","0","no","ET"
+"ET","CONT","type=i32,ne=[2,1,1,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=i32,ne=[2,1,3,5],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=i32,ne=[2,3,5,7],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=i32,ne=[1,4,4,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=i32,ne=[1,8,17,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=i32,ne=[10,10,10,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=f16,ne=[2,1,1,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f16,ne=[2,1,3,5],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f16,ne=[2,3,5,7],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f16,ne=[1,4,4,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f16,ne=[1,8,17,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=f16,ne=[10,10,10,1],use_view_slice=0","support","1","yes","ET"
+"ET","CONT","type=bf16,ne=[2,1,1,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=bf16,ne=[2,1,3,5],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=bf16,ne=[2,3,5,7],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=bf16,ne=[1,4,4,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=bf16,ne=[1,8,17,1],use_view_slice=0","support","0","no","ET"
+"ET","CONT","type=bf16,ne=[10,10,10,1],use_view_slice=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,6],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,6],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,6],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,6],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","ADD","type=f16,ne=[10,5,4,5],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","SUB","type=f16,ne=[10,5,4,5],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","MUL","type=f16,ne=[10,5,4,5],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","DIV","type=f16,ne=[10,5,4,5],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,120,120],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,120,120],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,120,120],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,120,120],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,4,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,4,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,4,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,4,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=1","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,65536,1],nr=[256,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f16,ne=[64,262144,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1,perm1=0,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","SUB","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","MUL","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","1","yes","ET"
+"ET","DIV","type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
+"ET","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1,perm1=1,src_overlap=0","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=0,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=1,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=113,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=1,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=3,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[8,1],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[16,1],kv=512,nb=75,mask=0,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[16,1],kv=512,nb=75,mask=1,sinks=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,2,1,3]","support","1","yes","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=113,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=75,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=1,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
+"ET","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[8,1],kv=512,nb=3,mask=1,sinks=0,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_K=f16,type_V=f16,permute=[0,1,2,3]","support","0","no","ET"
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+"ET","GATED_DELTA_NET","type=f32,head_count=16,head_size=64,n_seq_tokens=1,n_seqs=2,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=8,head_size=32,n_seq_tokens=4,n_seqs=2,v_repeat=2,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=1,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=1,v_repeat=1,permuted=1,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=1,n_seqs=1,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=1,n_seqs=2,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=16,n_seq_tokens=1,n_seqs=2,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=32,n_seq_tokens=4,n_seqs=1,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=8,head_size=32,n_seq_tokens=4,n_seqs=2,v_repeat=2,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=1,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=16,n_seq_tokens=4,n_seqs=2,v_repeat=1,permuted=1,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=64,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=127,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=256,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=65,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=100,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=200,n_seqs=1,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=127,n_seqs=2,v_repeat=1,permuted=0,kda=0","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=64,n_seqs=1,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=33,n_seqs=1,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"
+"ET","GATED_DELTA_NET","type=f32,head_count=4,head_size=64,n_seq_tokens=100,n_seqs=1,v_repeat=1,permuted=0,kda=1","support","1","yes","ET"

diff --git a/ggml/CMakeLists.txt b/ggml/CMakeLists.txt
index 0ec62a3773d6024fd7d5c849af65aab04cd10583..0c4e94e38cd7e2135dcb36b3a997cfe6745158da 100644 (file)
--- a/ggml/CMakeLists.txt
+++ b/ggml/CMakeLists.txt
@@ -257,6 +257,8 @@ set   (GGML_SYCL_DEVICE_ARCH "" CACHE STRING
                                             "ggml: sycl device architecture")
 
 option(GGML_OPENVINO                        "ggml: use OPENVINO"                              OFF)
+option(GGML_ET                              "ggml: use ET backend"                            OFF)
+option(GGML_ET_SYSEMU                       "ggml: use ET backend via sysemu"                 OFF)
 
 option(GGML_OPENCL                          "ggml: use OpenCL"                                OFF)
 option(GGML_OPENCL_PROFILING                "ggml: use OpenCL profiling (increases overhead)" OFF)

diff --git a/ggml/include/ggml-et.h b/ggml/include/ggml-et.h
new file mode 100644 (file)
index 0000000..8b78f39
--- /dev/null
+++ b/ggml/include/ggml-et.h
@@ -0,0 +1,28 @@
+#pragma once
+
+#include "ggml.h"
+#include "ggml-backend.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GGML_ET_NAME "ET"
+
+// backend API
+GGML_BACKEND_API ggml_guid_t     ggml_backend_et_guid(void);
+GGML_BACKEND_API ggml_backend_t ggml_backend_et_init(size_t devidx);
+
+GGML_BACKEND_API bool ggml_backend_is_et(ggml_backend_t backend);
+GGML_BACKEND_API int  ggml_backend_et_get_device_count(void);
+GGML_BACKEND_API void ggml_backend_et_get_device_description(int devidx, char * description, size_t description_size);
+GGML_BACKEND_API void ggml_backend_et_get_device_memory(int devidx, size_t * free, size_t * total);
+
+GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_et_buffer_type(size_t dev_num);
+GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_et_host_buffer_type(void);
+
+GGML_BACKEND_API ggml_backend_reg_t ggml_backend_et_reg(void);
+
+#ifdef  __cplusplus
+}
+#endif

diff --git a/ggml/src/CMakeLists.txt b/ggml/src/CMakeLists.txt
index 89e5180d931f0ab2c8c827e17b12ca4baab350e2..11583474a9a976268d84407a003476659202332e 100644 (file)
--- a/ggml/src/CMakeLists.txt
+++ b/ggml/src/CMakeLists.txt
@@ -473,6 +473,7 @@ endif()
 ggml_add_backend(BLAS)
 ggml_add_backend(CANN)
 ggml_add_backend(CUDA)
+ggml_add_backend(ET)
 ggml_add_backend(HIP)
 ggml_add_backend(METAL)
 ggml_add_backend(MUSA)

diff --git a/ggml/src/ggml-backend-reg.cpp b/ggml/src/ggml-backend-reg.cpp
index 8165ae2c8bbea5105b113348fab4e814820f5ac8..e5959467071d583131ecebe462a9b4155cc04f2c 100644 (file)
--- a/ggml/src/ggml-backend-reg.cpp
+++ b/ggml/src/ggml-backend-reg.cpp
@@ -86,6 +86,10 @@
 #include "ggml-openvino.h"
 #endif
 
+#ifdef GGML_USE_ET
+#include "ggml-et.h"
+#endif
+
 namespace fs = std::filesystem;
 
 static std::string path_str(const fs::path & path) {
@@ -161,6 +165,9 @@ struct ggml_backend_registry {
 #ifdef GGML_USE_OPENVINO
         register_backend(ggml_backend_openvino_reg());
 #endif
+#ifdef GGML_USE_ET
+        register_backend(ggml_backend_et_reg());
+#endif
 #ifdef GGML_USE_CPU
         register_backend(ggml_backend_cpu_reg());
 #endif

diff --git a/ggml/src/ggml-et/CMakeLists.txt b/ggml/src/ggml-et/CMakeLists.txt
new file mode 100644 (file)
index 0000000..ee0ee37
--- /dev/null
+++ b/ggml/src/ggml-et/CMakeLists.txt
@@ -0,0 +1,246 @@
+
+message(STATUS "Using ET backend")
+
+# Configure ET platform path
+if (DEFINED ENV{ET_PLATFORM})
+    set(ET_PLATFORM_PATH $ENV{ET_PLATFORM})
+else()
+    set(ET_PLATFORM_PATH "/opt/et")
+endif()
+
+# Use sysemu for ET backend if compiled with `-DGGML_ET_SYSEMU=ON`
+if (GGML_ET_SYSEMU)
+    message(STATUS "Using ET backend with sysemu instead of hardware")
+else()
+    message(STATUS "Using ET backend with hardware device")
+endif()
+
+# Add ET platform CMake modules and config files to search paths
+list(APPEND CMAKE_PREFIX_PATH ${ET_PLATFORM_PATH}/lib/cmake)
+list(APPEND CMAKE_MODULE_PATH ${ET_PLATFORM_PATH}/lib/cmake)
+include(aifoundry-utils/ProjectFunctions)
+
+message(STATUS "Using ET Platform at ${ET_PLATFORM_PATH}")
+
+find_package(runtime REQUIRED)
+
+# Kernel list
+set(KERNELS
+    el_map_f32
+    flash_attn_ext_f32
+    glu_f32
+    scale_f32
+    mul_mat_f32
+    mul_mat_f32_matrix_engine
+    mul_mat_id_f32
+    mul_mat_id_Q4_0
+    mul_mat_id_Q8_0
+    mul_mat_Q8_0
+    mul_mat_Q4_0
+    mul_mat_Q4_0_matrix_engine
+    mul_mat_f16
+    mul_mat_f16_matrix_engine
+    rope_f32
+    unary_f32
+    sqr_f32
+    clamp_f32
+    sum_rows_f32
+    mean_f32
+    cumsum_f32
+    norm_f32
+    l2_norm_f32
+    group_norm_f32
+    rms_norm_f32
+    rms_norm_mul_f32
+    softmax_f32
+    im2col
+    get_rows_f32
+    concat_f32
+    repeat_f32
+    rwkv_wkv6_f32
+    rwkv_wkv7_f32
+    gated_delta_net_f32
+    cont_f32
+    cont_f16
+    cpy_f32_f16
+    flash_attn_ext_f16_me
+    set_rows_f32
+    set_f32
+    fill_f32
+    pad_f32
+    diag_f32
+    tri_f32
+    solve_tri_f32
+    ssm_conv_f32
+    ssm_scan_f32
+    conv_2d_f32_me
+    memops
+    uberkernel
+)
+
+# Kernels that we support dispatch form Uberkernel
+set(UBERKERNEL_SUPPORTED_KERNELS
+    el_map_f32
+    # unary_f32
+    # cpy_f32_f16
+    # cont_f32
+    # get_rows_f32
+    concat_f32
+    cont_f16
+    cumsum_f32
+    diag_f32
+    fill_f32
+    flash_attn_ext_f16_me
+    flash_attn_ext_f32
+    gated_delta_net_f32
+    glu_f32
+    group_norm_f32
+    im2col
+    l2_norm_f32
+    mul_mat_f16
+    mul_mat_f16_matrix_engine
+    mul_mat_f32
+    mul_mat_f32_matrix_engine
+    mul_mat_id_f32
+    mul_mat_Q4_0
+    mul_mat_Q8_0
+    norm_f32
+    pad_f32
+    repeat_f32
+    rms_norm_f32
+    rms_norm_mul_f32
+    rope_f32
+    rwkv_wkv6_f32
+    rwkv_wkv7_f32
+    scale_f32
+    set_f32
+    set_rows_f32
+    softmax_f32
+    solve_tri_f32
+    sqr_f32
+    # ssm_conv_f32
+    ssm_scan_f32
+    sum_rows_f32
+    tri_f32
+)
+
+set(UBERKERNEL_MAP_HPP ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-uberkernel-kernel-map.h)
+set(UBERKERNEL_MAP_CPP ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-uberkernel-kernel-map.cpp)
+
+set(UBERKERNEL_KERNELS_SORTED ${UBERKERNEL_SUPPORTED_KERNELS})
+list(SORT UBERKERNEL_KERNELS_SORTED)
+
+set(UBERKERNEL_ENUM_ENTRIES "")
+set(UBERKERNEL_MAP_ENTRIES "")
+set(_uk_idx 1)
+foreach(KERNEL ${UBERKERNEL_KERNELS_SORTED})
+    string(TOUPPER ${KERNEL} _uk_upper)
+    string(APPEND UBERKERNEL_ENUM_ENTRIES
+        "    GGML_ET_UBERKERNEL_KERNEL_${_uk_upper} = ${_uk_idx},\n")
+    string(APPEND UBERKERNEL_MAP_ENTRIES
+        "        {\"${KERNEL}\", GGML_ET_UBERKERNEL_KERNEL_${_uk_upper}},\n")
+    math(EXPR _uk_idx "${_uk_idx} + 1")
+endforeach()
+
+configure_file(
+    ${CMAKE_CURRENT_SOURCE_DIR}/cmake/ggml-et-uberkernel-kernel-map.h.in
+    ${UBERKERNEL_MAP_HPP}
+    @ONLY)
+configure_file(
+    ${CMAKE_CURRENT_SOURCE_DIR}/cmake/ggml-et-uberkernel-kernel-map.cpp.in
+    ${UBERKERNEL_MAP_CPP}
+    @ONLY)
+
+add_custom_target(et-uberkernel-map
+    DEPENDS ${UBERKERNEL_MAP_HPP} ${UBERKERNEL_MAP_CPP}
+)
+
+# Build ET kernels (cross-compiled in subdirectory scope)
+add_subdirectory(et-kernels)
+
+# Embed kernels into C++ source
+set(EMBED_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/cmake/embed_one_kernel.cmake)
+set(EMBED_HPP ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-kernels-embed.hpp)
+set(EMBED_CPP ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-kernels-embed.cpp)
+set(EMBED_DIR ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/embed)
+file(MAKE_DIRECTORY ${EMBED_DIR})
+
+set(EMBED_KERNEL_SOURCES)
+set(EMBED_EXTERNS "")
+set(EMBED_MAP_ENTRIES "")
+
+foreach(KERNEL ${KERNELS})
+    set(ELF_PATH ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/${KERNEL}.elf)
+    set(OUT_CPP ${EMBED_DIR}/${KERNEL}.cpp)
+
+    add_custom_command(
+        OUTPUT ${OUT_CPP}
+        COMMAND ${CMAKE_COMMAND}
+            -DELF_FILE=${ELF_PATH}
+            -DOUT_FILE=${OUT_CPP}
+            -DVAR_NAME=${KERNEL}
+            -P ${EMBED_SCRIPT}
+        DEPENDS ${KERNEL}.elf ${EMBED_SCRIPT}
+        COMMENT "Embedding ${KERNEL}.elf"
+        VERBATIM
+    )
+    list(APPEND EMBED_KERNEL_SOURCES ${OUT_CPP})
+
+    string(APPEND EMBED_EXTERNS
+        "extern unsigned char ${KERNEL}_data[];\n"
+        "extern const uint64_t ${KERNEL}_len;\n")
+    string(APPEND EMBED_MAP_ENTRIES
+        "    {\"${KERNEL}\", {${KERNEL}_data, ${KERNEL}_len}},\n")
+endforeach()
+
+configure_file(
+    ${CMAKE_CURRENT_SOURCE_DIR}/cmake/ggml-et-kernels-embed.hpp.in
+    ${EMBED_HPP}
+    @ONLY)
+configure_file(
+    ${CMAKE_CURRENT_SOURCE_DIR}/cmake/ggml-et-kernels-embed.cpp.in
+    ${EMBED_CPP}
+    @ONLY)
+
+add_custom_target(et-kernels-embed ALL
+    DEPENDS ${EMBED_KERNEL_SOURCES} ${EMBED_HPP} ${EMBED_CPP} et-uberkernel-map
+)
+
+ggml_add_backend_library(ggml-et
+                         ggml-et.cpp
+                         ggml-et-kernels.cpp
+                         ggml-et-memops.cpp
+                         ggml-et-ops.cpp
+                         ggml-et-cpu-compare.cpp
+                        )
+
+# Mark generated files as such
+set_source_files_properties(
+    ${EMBED_CPP}
+    ${EMBED_HPP}
+    ${EMBED_KERNEL_SOURCES}
+    ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-uberkernel-kernel-map.cpp
+    ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-uberkernel-kernel-map.h
+    PROPERTIES GENERATED TRUE
+)
+
+# Add embedded kernel sources
+target_sources(ggml-et PRIVATE
+    ${EMBED_CPP}
+    ${EMBED_HPP}
+    ${EMBED_KERNEL_SOURCES}
+    ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-uberkernel-kernel-map.cpp
+    ${CMAKE_CURRENT_BINARY_DIR}/et-kernels/ggml-et-uberkernel-kernel-map.h
+)
+
+# Include directory for embedded headers
+target_include_directories(ggml-et PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/et-kernels)
+
+target_link_libraries(ggml-et PRIVATE runtime::etrt_static deviceLayer::deviceLayer)
+target_compile_definitions(ggml-et PRIVATE GGML_ET_UBERKERNEL_HOST_LOOKUP)
+if (GGML_ET_SYSEMU)
+    target_compile_definitions(ggml-et PRIVATE GGML_ET_SYSEMU=1)
+endif()
+
+# Ensure kernels are built and embedded before the backend library
+add_dependencies(ggml-et et-kernels-embed et-uberkernel-map)

diff --git a/ggml/src/ggml-et/cmake/embed_one_kernel.cmake b/ggml/src/ggml-et/cmake/embed_one_kernel.cmake
new file mode 100644 (file)
index 0000000..cc01ecb
--- /dev/null
+++ b/ggml/src/ggml-et/cmake/embed_one_kernel.cmake
@@ -0,0 +1,15 @@
+# Inputs (via -D):
+#   ELF_FILE  - path to source .elf
+#   OUT_FILE  - path to output .cpp
+#   VAR_NAME  - C symbol base name (kernel name)
+
+file(READ "${ELF_FILE}" HEX HEX)
+string(LENGTH "${HEX}" HEX_LEN)
+math(EXPR SIZE "${HEX_LEN} / 2")
+string(REGEX REPLACE "(..)" "0x\\1," BYTES "${HEX}")
+
+file(WRITE "${OUT_FILE}"
+"// Auto-generated by embed_one_kernel.cmake. Do not edit.\n"
+"#include <cstdint>\n"
+"unsigned char ${VAR_NAME}_data[${SIZE}] = { ${BYTES} };\n"
+"extern const uint64_t ${VAR_NAME}_len = ${SIZE};\n")

diff --git a/ggml/src/ggml-et/cmake/ggml-et-kernels-embed.cpp.in b/ggml/src/ggml-et/cmake/ggml-et-kernels-embed.cpp.in
new file mode 100644 (file)
index 0000000..95f6e40
--- /dev/null
+++ b/ggml/src/ggml-et/cmake/ggml-et-kernels-embed.cpp.in
@@ -0,0 +1,6 @@
+// Auto-generated kernel embeddings. Do not edit.
+#include "ggml-et-kernels-embed.hpp"
+
+const std::unordered_map<std::string, std::pair<const unsigned char*, uint64_t>> ggml_et_embedded_kernels = {
+@EMBED_MAP_ENTRIES@
+};

diff --git a/ggml/src/ggml-et/cmake/ggml-et-kernels-embed.hpp.in b/ggml/src/ggml-et/cmake/ggml-et-kernels-embed.hpp.in
new file mode 100644 (file)
index 0000000..dd2c6ab
--- /dev/null
+++ b/ggml/src/ggml-et/cmake/ggml-et-kernels-embed.hpp.in
@@ -0,0 +1,12 @@
+// Auto-generated kernel embeddings. Do not edit.
+#pragma once
+
+#include <cstdint>
+#include <unordered_map>
+#include <string>
+#include <utility>
+
+@EMBED_EXTERNS@
+
+// Kernel name -> (data, length) lookup map
+extern const std::unordered_map<std::string, std::pair<const unsigned char*, uint64_t>> ggml_et_embedded_kernels;

diff --git a/ggml/src/ggml-et/cmake/ggml-et-uberkernel-kernel-map.cpp.in b/ggml/src/ggml-et/cmake/ggml-et-uberkernel-kernel-map.cpp.in
new file mode 100644 (file)
index 0000000..ccee5d4
--- /dev/null
+++ b/ggml/src/ggml-et/cmake/ggml-et-uberkernel-kernel-map.cpp.in
@@ -0,0 +1,18 @@
+// Auto-generated uberkernel kernel-id mapping. Do not edit.
+#include "ggml-et-uberkernel-kernel-map.h"
+
+#ifdef GGML_ET_UBERKERNEL_HOST_LOOKUP
+#include <string>
+#include <unordered_map>
+
+uint16_t ggml_et_uberkernel_kernel_id_from_name(const char * kernel_name) {
+    if (kernel_name == nullptr) {
+        return GGML_ET_UBERKERNEL_KERNEL_INVALID;
+    }
+    static const std::unordered_map<std::string, uint16_t> kernel_id_map = {
+@UBERKERNEL_MAP_ENTRIES@
+    };
+    auto it = kernel_id_map.find(std::string(kernel_name));
+    return it == kernel_id_map.end() ? GGML_ET_UBERKERNEL_KERNEL_INVALID : it->second;
+}
+#endif

diff --git a/ggml/src/ggml-et/cmake/ggml-et-uberkernel-kernel-map.h.in b/ggml/src/ggml-et/cmake/ggml-et-uberkernel-kernel-map.h.in
new file mode 100644 (file)
index 0000000..cebfb8a
--- /dev/null
+++ b/ggml/src/ggml-et/cmake/ggml-et-uberkernel-kernel-map.h.in
@@ -0,0 +1,13 @@
+// Auto-generated uberkernel kernel-id mapping. Do not edit.
+#pragma once
+
+#include <stdint.h>
+
+enum ggml_et_uberkernel_kernel_id {
+    GGML_ET_UBERKERNEL_KERNEL_INVALID = 0,
+@UBERKERNEL_ENUM_ENTRIES@
+};
+
+#ifdef GGML_ET_UBERKERNEL_HOST_LOOKUP
+uint16_t ggml_et_uberkernel_kernel_id_from_name(const char * kernel_name);
+#endif

diff --git a/ggml/src/ggml-et/et-kernels/CMakeLists.txt b/ggml/src/ggml-et/et-kernels/CMakeLists.txt
new file mode 100644 (file)
index 0000000..4b6baab
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/CMakeLists.txt
@@ -0,0 +1,137 @@
+# ggml-et: Device kernels (cross-compiled within the main build)
+#
+# The RISC-V toolchain is set up in-scope so these targets use the
+# cross-compiler while the rest of the build uses the host compiler.
+# This keeps kernels in compile_commands.json for full IDE support.
+
+# --- RISC-V toolchain setup (scoped to this directory) ---
+set(TOOLCHAIN_DIR ${ET_PLATFORM_PATH})
+include(${ET_PLATFORM_PATH}/lib/cmake/riscv64-ec-toolchain.cmake)
+set(CMAKE_ADDR2LINE "${TOOLCHAIN_DIR}/bin/riscv64-unknown-elf-addr2line")
+set(CMAKE_LINKER_TYPE LLD)
+
+# Ensure kernels are built in this directory even if a global output directory is set
+set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
+
+message(STATUS "ET kernels using RISC-V toolchain at: ${TOOLCHAIN_DIR}")
+
+# DeviceUtils provides the add_riscv_executable macro
+list(APPEND CMAKE_MODULE_PATH "${ET_PLATFORM_PATH}/lib/cmake/cmake-modules")
+list(APPEND CMAKE_PREFIX_PATH "${ET_PLATFORM_PATH}/lib/cmake")
+include(DeviceUtils)
+
+find_package(et-common-libs REQUIRED)
+find_package(esperantoTrace REQUIRED)
+
+# --- Kernel configuration ---
+if(NOT DEFINED ADDRESS)
+    set(ADDRESS "0x8005801000")
+    message(STATUS "ADDRESS not specified, using default: ${ADDRESS}")
+endif()
+
+set(LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/src/linker.ld)
+set(CHECK_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/scripts/check_unimplemented_instructions.sh)
+
+# Track address changes to trigger relinking
+set(ADDRESS_FILE ${CMAKE_CURRENT_BINARY_DIR}/et_address.txt)
+file(CONFIGURE OUTPUT ${ADDRESS_FILE} CONTENT "${ADDRESS}" @ONLY)
+
+# KERNELS defined in upper CMakeLists.txt
+foreach(KERNEL ${KERNELS})
+    add_riscv_executable(${KERNEL})
+    target_sources(${KERNEL}.elf PRIVATE
+        src/${KERNEL}.c
+        src/crt.S
+    )
+    target_include_directories(${KERNEL}.elf PRIVATE
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        ${CMAKE_CURRENT_SOURCE_DIR}/..
+        ${CMAKE_CURRENT_BINARY_DIR}
+        ${CMAKE_SOURCE_DIR}/ggml/include
+        ${CMAKE_SOURCE_DIR}/ggml/src
+    )
+    target_link_libraries(${KERNEL}.elf PRIVATE et-common-libs::cm-umode)
+    # C-only flags — must not apply to .S files
+    target_compile_options(${KERNEL}.elf PRIVATE
+        $<$<COMPILE_LANGUAGE:C>:-fno-zero-initialized-in-bss>
+        $<$<COMPILE_LANGUAGE:C>:-ffreestanding>
+        $<$<COMPILE_LANGUAGE:C>:-std=gnu99>
+        $<$<COMPILE_LANGUAGE:C>:-ffat-lto-objects>
+        $<$<COMPILE_LANGUAGE:C>:-mcmodel=medany>
+        $<$<COMPILE_LANGUAGE:C>:-mabi=lp64f>
+        $<$<COMPILE_LANGUAGE:C>:-march=rv64imf>
+        $<$<COMPILE_LANGUAGE:C>:-ffunction-sections>
+        $<$<COMPILE_LANGUAGE:C>:-fdata-sections>
+        $<$<COMPILE_LANGUAGE:C>:-O3>
+        $<$<COMPILE_LANGUAGE:C>:-g0>
+        $<$<COMPILE_LANGUAGE:C>:-nostdlib>
+        $<$<COMPILE_LANGUAGE:C>:-ffreestanding>
+    )
+    target_link_options(${KERNEL}.elf PRIVATE
+        -Wl,--defsym=BASE_ADDRESS=${ADDRESS}
+        -Wl,--entry=_start
+    )
+    # Append to LINK_DEPENDS (macro already sets it for the linker script)
+    set_property(TARGET ${KERNEL}.elf APPEND PROPERTY
+        LINK_DEPENDS "${ADDRESS_FILE}"
+    )
+
+    # Post-build: strip and check (fails build if check script fails)
+    add_custom_command(TARGET ${KERNEL}.elf POST_BUILD
+        COMMAND ${CMAKE_STRIP} --strip-debug $<TARGET_FILE:${KERNEL}.elf>
+        COMMAND ${CHECK_SCRIPT}
+            ${CMAKE_OBJDUMP} ${CMAKE_ADDR2LINE} $<TARGET_FILE:${KERNEL}.elf>
+        DEPENDS ${CHECK_SCRIPT}
+        VERBATIM
+    )
+endforeach()
+
+add_dependencies(uberkernel.elf et-uberkernel-map)
+
+# Each supported kernel is compiled in its own translation unit with
+#   -Dentry_point=<kernel>_entry
+# so symbols and macros don't leak between kernels. The dispatcher
+# (uberkernel.c) calls the renamed entries via extern declarations.
+#
+# HACK: we need to supresse _me kernels from setting up SCP themselves
+set(_UBER_ME_KERNELS mul_mat_f16_matrix_engine mul_mat_f32_matrix_engine flash_attn_ext_f16_me)
+
+foreach(UK_KERNEL ${UBERKERNEL_SUPPORTED_KERNELS})
+    set(_obj uber_${UK_KERNEL})
+    add_library(${_obj} OBJECT src/${UK_KERNEL}.c)
+    target_compile_definitions(${_obj} PRIVATE "entry_point=${UK_KERNEL}_entry" ET_UBERKERNEL)
+    target_include_directories(${_obj} PRIVATE
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        ${CMAKE_CURRENT_SOURCE_DIR}/..
+        ${CMAKE_CURRENT_BINARY_DIR}
+        ${CMAKE_SOURCE_DIR}/ggml/include
+        ${CMAKE_SOURCE_DIR}/ggml/src
+    )
+    target_link_libraries(${_obj} PRIVATE et-common-libs::cm-umode)
+    target_compile_options(${_obj} PRIVATE
+        $<$<COMPILE_LANGUAGE:C>:-fno-zero-initialized-in-bss>
+        $<$<COMPILE_LANGUAGE:C>:-ffreestanding>
+        $<$<COMPILE_LANGUAGE:C>:-std=gnu99>
+        $<$<COMPILE_LANGUAGE:C>:-ffat-lto-objects>
+        $<$<COMPILE_LANGUAGE:C>:-mcmodel=medany>
+        $<$<COMPILE_LANGUAGE:C>:-mabi=lp64f>
+        $<$<COMPILE_LANGUAGE:C>:-march=rv64imf>
+        $<$<COMPILE_LANGUAGE:C>:-ffunction-sections>
+        $<$<COMPILE_LANGUAGE:C>:-fdata-sections>
+        $<$<COMPILE_LANGUAGE:C>:-O3>
+        $<$<COMPILE_LANGUAGE:C>:-g0>
+        $<$<COMPILE_LANGUAGE:C>:-nostdlib>
+    )
+    # ME kernels: suppress setup_cache_scp() (called once by the dispatcher)
+    if(UK_KERNEL IN_LIST _UBER_ME_KERNELS)
+        target_compile_definitions(${_obj} PRIVATE UBERKERNEL_SUPPRESS_SCP_SETUP)
+    endif()
+    target_sources(uberkernel.elf PRIVATE $<TARGET_OBJECTS:${_obj}>)
+endforeach()
+
+# Print summary
+message(STATUS "GGML ET Kernels configured:")
+foreach(KERNEL ${KERNELS})
+    message(STATUS "  - ${KERNEL}")
+endforeach()
+message(STATUS "Base address: ${ADDRESS}")

diff --git a/ggml/src/ggml-et/et-kernels/scripts/check_unimplemented_instructions.sh b/ggml/src/ggml-et/et-kernels/scripts/check_unimplemented_instructions.sh
new file mode 100755 (executable)
index 0000000..83f7992
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/scripts/check_unimplemented_instructions.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+
+OBJDUMP=$1
+ADDR2LINE=$2
+TARGET_DEBUG=$3
+TARGET_ASM=${TARGET_DEBUG}.S
+BAD_INST_FILE=${TARGET_DEBUG}-BAD-INST.log
+
+# grep expression to find unimplemented instructions
+UNIMPLEMENTED_EXPR="fdiv.s\\|fsqrt.s\\|fcvt.l.s\\|fcvt.lu.s\\|fcvt.s.l\\|fcvt.s.lu\\|fdiv.pi\\|fdivu.pi\\|fremu.pi\\|frem.pi\\|fdiv.ps\\|fsqrt.ps\\|frsq.ps\\|fsin.ps"
+
+# dump assembly into .S file
+${OBJDUMP} -lwdSC ${TARGET_DEBUG} > ${TARGET_ASM}
+
+# check with grep for unimplemented instructions
+# Note: The exit status is 0 if selected lines are found, and 1 if not found.
+grep ${UNIMPLEMENTED_EXPR} ${TARGET_ASM} > /dev/null
+ret=$?
+
+if [ ${ret} -eq 0 ]
+then
+    # unimplemented instructions are found
+    echo -e "BUILD ERROR: Executable file ${TARGET_DEBUG} contains unimplemented instructions. Please review the lines of code listed in ${BAD_INST_FILE}"
+    echo -e "\t     For further details, please read paragraph 3.4 of the ETSoC-1 Programmer's Reference Manual (PRM)"
+
+    # addr2line
+    grep ${UNIMPLEMENTED_EXPR} ${TARGET_ASM} | cut -d: -f 1 | ${ADDR2LINE} -i -e ${TARGET_DEBUG} > ${BAD_INST_FILE}
+    grep ${UNIMPLEMENTED_EXPR} ${TARGET_ASM} >> ${BAD_INST_FILE}
+    echo "------------------------------------------------------------"
+    cat ${BAD_INST_FILE}
+    echo "------------------------------------------------------------"
+    exit 1
+
+else
+   rm -f ${BAD_INST_FILE}
+fi

diff --git a/ggml/src/ggml-et/et-kernels/src/RunBackend.sh b/ggml/src/ggml-et/et-kernels/src/RunBackend.sh
new file mode 100644 (file)
index 0000000..b302e2a
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/RunBackend.sh
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+LOG="llama_bench_$(date +%Y%m%d_%H%M%S).log"
+
+{
+  echo "===== START ====="
+  date
+  hostname
+  uname -a
+  echo "Command:"
+  echo "./build/bin/llama-bench -m ../../models/Llama-3.2-1B-Instruct-Q8_0.gguf -fa 0 -p 32,64,128,256,512 -n 32,64,128,256,512"
+  echo "================="
+
+  ./build/bin/llama-bench \
+    -m ../../models/Llama-3.2-1B-Instruct-Q8_0.gguf \
+    -fa 0 \
+    -p 32,64,128,256,512 \
+    -n 32,64,128,256,512
+
+  echo "===== END ====="
+  date
+} 2>&1 | tee "$LOG"

diff --git a/ggml/src/ggml-et/et-kernels/src/block_ops.h b/ggml/src/ggml-et/et-kernels/src/block_ops.h
new file mode 100644 (file)
index 0000000..78ffbde
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/block_ops.h
@@ -0,0 +1,997 @@
+//******************************************************************************
+// ET Vectorized Block Operations Library
+// Provides optimized block-level operations using ET hardware vector instructions
+//******************************************************************************
+
+#ifndef BLOCK_OPS_H
+#    define BLOCK_OPS_H
+
+#    include "math_fp.h"
+#    include "quants.h"
+
+#    include <stdint.h>
+
+//******************************************************************************
+// Block Dot Product Operations
+//******************************************************************************
+inline void __attribute__((always_inline)) excl_mode(uint64_t val) {
+    __asm__ __volatile__("csrw 0x7d3, %[csr_enc]\n" : : [csr_enc] "r"(val) : "x31");
+}
+
+static inline float compute_block_dot_product_q4_0(const block_q4_0 * a_block, const float * b_col_start) {
+    // Set mask register to enable all 8 vector elements
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+
+    // Use f10 as accumulator, init to 0
+    __asm__ volatile("fbci.ps f10, 0" ::: "f10");
+
+    static const int32_t gather_pattern[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+    __asm__ volatile("flw.ps f31, %[gather]\n" : : [gather] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+
+    // Process 32 elements in 2 chunks of 16 elements (8 bytes) each
+    for (int chunk = 0; chunk < 2; chunk++) {
+        int offset_a      = chunk * 8;
+        int offset_b_low  = chunk * 8;       // Activations for lower nibbles
+        int offset_b_high = chunk * 8 + 16;  // Activations for upper nibbles (16 elements later)
+
+        __asm__ volatile(
+            "fgb.ps f11, f31(%[a_ptr])\n"  // Gather 8 bytes (16 packed q4_0 weights)
+
+            // 1. Extract & Multiply Lower Nibbles
+            "fandi.pi f12, f11, 15\n"             // Mask lower 4 bits (x & 0xF)
+            "faddi.pi f12, f12, -8\n"             // GGML offset to signed: (x & 0xF) - 8
+            "fcvt.ps.pw f12, f12, rne\n"          // Convert INT32 to FP32
+            "flw.ps f13, 0(%[b_low])\n"           // Load 8 B values (floats)
+            "fmadd.ps f10, f12, f13, f10, rne\n"  // acc += A_low * B_low
+
+            // 2. Extract & Multiply Upper Nibbles
+            "fsrli.pi f14, f11, 4\n"              // Shift upper 4 bits down
+            "fandi.pi f14, f14, 15\n"             // Mask new lower 4 bits
+            "faddi.pi f14, f14, -8\n"             // GGML offset to signed
+            "fcvt.ps.pw f14, f14, rne\n"          // Convert INT32 to FP32
+            "flw.ps f15, 0(%[b_high])\n"          // Load next 8 B values (floats)
+            "fmadd.ps f10, f14, f15, f10, rne\n"  // acc += A_high * B_high
+            :
+            : [a_ptr] "r"(&a_block->qs[offset_a]), [b_low] "r"(&b_col_start[offset_b_low]),
+              [b_high] "r"(&b_col_start[offset_b_high])
+            // Note: f10 is explicitly NOT listed in the clobbers here to ensure the compiler
+            // preserves the running sum across C loop iterations safely.
+            : "f11", "f12", "f13", "f14", "f15");
+    }
+
+    // Horizontal sum: reduce f10 into a single scalar
+    float final_sum;
+    __asm__ __volatile__(
+        // Pairwise sum within each 128-bit half
+        "fswizz.ps f1, f10, 0xB1 \n\t"  // Swaps: e0<->e1 and e2<->e3
+        "fadd.ps   f2, f10, f1, rne \n\t"
+        // Complete the sum for each 128-bit half
+        "fswizz.ps f3, f2, 0x4E \n\t"  // Swaps: e0,e1 <-> e2,e3
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        // Sum across the two 128b halfs
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(final_sum)::"t0", "f1", "f2", "f3", "f4", "f5", "f10");
+
+    // Restore original mask
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    const float scale = fp16_to_fp32(a_block->d);
+    return final_sum * scale;
+}
+
+// Compute dot product between dequantized q8_0 block and f32 column vector
+// Vectorized: processes 8 elements at a time using ET vector instructions
+// Block size: 32 int8 values (QK8_0)
+static inline float compute_block_dot_product_q8_0(const block_q8_0 * a_block, const float * b_col_start) {
+    // Set mask register to enable all 8 vector elements
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+    __asm__ volatile("fbci.pi f10, 0" ::: "f10");       // Use f10 as accumulator, init to 0
+
+    static const int32_t gather_pattern[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+    __asm__ volatile("flw.ps f31, %[gather]\n" : : [gather] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+
+    // Process 32 elements in 4 chunks of 8 elements each
+    for (int chunk = 0; chunk < 4; chunk++) {
+        int offset = chunk << 3;  // chunk * 8
+
+        __asm__ volatile(
+            "flw.ps f12, %[b_vec]\n"         // Load 8 B values (floats)
+            "fgb.ps f11, f31(%[a_ptr])\n"    // Gather 8 int8 bytes from A using pattern
+            "fcvt.ps.pw f11, f11\n"          // Convert int8 vector to float vector
+            "fmadd.ps f10, f11, f12, f10\n"  // acc += a_vec * b_vec (8-wide)
+            :
+            : [a_ptr] "r"(&a_block->qs[offset]), [b_vec] "m"(*(const float (*)[8]) & b_col_start[offset]),
+              [scale] "m"(a_block->d)
+            : "f10", "f11", "f12");
+    }
+
+    // Horizontal sum: reduce f10 into a single scalar
+    float final_sum;
+    __asm__ __volatile__(
+        // Pairwise sum within each 128-bit half
+        "fswizz.ps f1, f10, 0xB1 \n\t"  // Swaps: e0<->e1 and e2<->e3
+        "fadd.ps   f2, f10, f1, rne \n\t"
+        // Complete the sum for each 128-bit half
+        "fswizz.ps f3, f2, 0x4E \n\t"  // Swaps: e0,e1 <-> e2,e3
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        // Sum across the two 128b halfs
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(final_sum)::"t0", "f10", "f2", "f3", "f4", "f5");
+
+    // Restore original mask
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    const float scale = fp16_to_fp32(a_block->d);
+    return final_sum * scale;
+}
+
+//******************************************************************************
+// Split-phase Q8_0 dot product API
+//
+//   q8_dot_begin(st)      — save mask, set mask 0xFF
+//   q8_dot_reset()        — zero vector accumulator f20
+//   q8_dot_tile(q, b, n)  — accumulate n Q8_0 blocks into f20
+//   q8_dot_reduce()       — horizontal sum of f20, return scalar float
+//   q8_dot_teardown(st)   — restore original mask
+//
+// Register contract:
+//   f20       — row accumulator (persistent across tiles, reset per row)
+//   f31       — gather pattern (reloaded per q8_dot_tile call)
+//   f10-f12   — scratch within tile
+//   f15       — scale broadcast within tile
+//   f1-f5, t0 — scratch within reduce
+//******************************************************************************
+
+static inline void __attribute__((always_inline)) q8_dot_reset(void) {
+    __asm__ volatile("fbci.pi f20, 0" ::: "f20");
+}
+
+// Accumulate n_blocks Q8_0 blocks into f20.
+// Uses fg32b.ps (fast gather with scalar pattern) for aligned chunks,
+// falls back to fgb.ps for chunks crossing a 32-byte boundary.
+static inline void __attribute__((always_inline)) q8_dot_tile(const block_q8_0 * q_row,
+                                                              const float *      b_col,
+                                                              int64_t            n_blocks) {
+    const int32_t  gather_pattern[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+    const uint64_t gather_0_to_7     = 0x398a418820ULL;
+
+    __asm__ volatile("flw.ps f31, %[g]\n" : : [g] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+
+    for (int64_t kb = 0; kb < n_blocks; kb++) {
+        const block_q8_0 * blk         = q_row + kb;
+        const float *      b_ptr       = b_col + (kb << 5);
+        const uintptr_t    qs_addr     = (uintptr_t) blk->qs;
+        const uintptr_t    qs_aligned  = qs_addr & ~(uintptr_t) 31;
+        const uintptr_t    qs_low      = qs_addr & 31;
+        const int          fast_chunks = (int) ((32 - qs_low) >> 3);
+
+        if (fast_chunks >= 3) {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "flw.ps      f12, %[bv0]\n"
+                "fg32b.ps    f11, %[gi](%[ap0])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv1]\n"
+                "fg32b.ps    f11, %[gi](%[ap1])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv2]\n"
+                "fg32b.ps    f11, %[gi](%[ap2])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv3]\n"
+                "fgb.ps      f11, f31(%[ap3])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                :
+                : [gi] "r"(gather_0_to_7), [ap0] "r"(qs_addr), [ap1] "r"(qs_aligned | ((qs_addr + 8) & 31)),
+                  [ap2] "r"(qs_aligned | ((qs_addr + 16) & 31)), [ap3] "r"(&blk->qs[24]),
+                  [bv0] "m"(*(const float (*)[8]) & b_ptr[0]), [bv1] "m"(*(const float (*)[8]) & b_ptr[8]),
+                  [bv2] "m"(*(const float (*)[8]) & b_ptr[16]), [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12");
+        } else if (fast_chunks == 2) {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "flw.ps      f12, %[bv0]\n"
+                "fg32b.ps    f11, %[gi](%[ap0])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv1]\n"
+                "fg32b.ps    f11, %[gi](%[ap1])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv2]\n"
+                "fgb.ps      f11, f31(%[ap2])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv3]\n"
+                "fgb.ps      f11, f31(%[ap3])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                :
+                : [gi] "r"(gather_0_to_7), [ap0] "r"(qs_addr), [ap1] "r"(qs_aligned | ((qs_addr + 8) & 31)),
+                  [ap2] "r"(&blk->qs[16]), [ap3] "r"(&blk->qs[24]), [bv0] "m"(*(const float (*)[8]) & b_ptr[0]),
+                  [bv1] "m"(*(const float (*)[8]) & b_ptr[8]), [bv2] "m"(*(const float (*)[8]) & b_ptr[16]),
+                  [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12");
+        } else if (fast_chunks == 1) {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "flw.ps      f12, %[bv0]\n"
+                "fg32b.ps    f11, %[gi](%[ap0])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv1]\n"
+                "fgb.ps      f11, f31(%[ap1])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv2]\n"
+                "fgb.ps      f11, f31(%[ap2])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv3]\n"
+                "fgb.ps      f11, f31(%[ap3])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                :
+                : [gi] "r"(gather_0_to_7), [ap0] "r"(qs_addr), [ap1] "r"(&blk->qs[8]), [ap2] "r"(&blk->qs[16]),
+                  [ap3] "r"(&blk->qs[24]), [bv0] "m"(*(const float (*)[8]) & b_ptr[0]),
+                  [bv1] "m"(*(const float (*)[8]) & b_ptr[8]), [bv2] "m"(*(const float (*)[8]) & b_ptr[16]),
+                  [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12");
+        } else {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "flw.ps      f12, %[bv0]\n"
+                "fgb.ps      f11, f31(%[ap0])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv1]\n"
+                "fgb.ps      f11, f31(%[ap1])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv2]\n"
+                "fgb.ps      f11, f31(%[ap2])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                "flw.ps      f12, %[bv3]\n"
+                "fgb.ps      f11, f31(%[ap3])\n"
+                "fcvt.ps.pw  f11, f11\n"
+                "fmadd.ps    f10, f11, f12, f10\n"
+                :
+                : [ap0] "r"(&blk->qs[0]), [ap1] "r"(&blk->qs[8]), [ap2] "r"(&blk->qs[16]), [ap3] "r"(&blk->qs[24]),
+                  [bv0] "m"(*(const float (*)[8]) & b_ptr[0]), [bv1] "m"(*(const float (*)[8]) & b_ptr[8]),
+                  [bv2] "m"(*(const float (*)[8]) & b_ptr[16]), [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12");
+        }
+
+        // f20 += f10 * broadcast(scale) — hardware fp16→fp32 via FCVT.PS.F16
+        uint32_t scale_raw = (uint32_t) blk->d;
+        __asm__ volatile(
+            "fbcx.ps f15, %[sb]\n"
+            "fcvt.ps.f16 f15, f15\n"
+            "fmadd.ps f20, f10, f15, f20\n"
+            :
+            : [sb] "r"(scale_raw)
+            : "f15", "f20");
+    }
+}
+
+// Horizontal sum of 8-element vector accumulator f20.
+static inline float __attribute__((always_inline)) q8_dot_reduce(void) {
+    float result;
+    __asm__ __volatile__(
+        "fswizz.ps f1, f20, 0xB1 \n\t"
+        "fadd.ps   f2, f20, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result)::"t0", "f1", "f2", "f3", "f4", "f5");
+    return result;
+}
+
+// Full-row dot product (convenience wrapper)
+static inline float compute_row_dot_q8_0(const block_q8_0 * q_row, const float * b_col, int64_t K_blocks) {
+    unsigned long saved_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+    q8_dot_reset();
+    q8_dot_tile(q_row, b_col, K_blocks);
+    float result = q8_dot_reduce();
+    __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    return result;
+}
+
+//******************************************************************************
+// Hoisted Q8_0 dot API
+//
+// q8_dot_begin/end save/restore the vector mask once around a long sequence of
+// dot products, so the per-row mask shuffles are hoisted out of the inner
+// loops. q8_dot_compute does a full-row dot (no mask handling). The _x2
+// variant computes two rows together while reusing each loaded B chunk —
+// only safe when both row pointers share the same 32-byte alignment phase
+// (i.e. the Q8 row stride is a multiple of 32).
+//******************************************************************************
+
+typedef struct {
+    unsigned long saved_mask;
+} q8_dot_state;
+
+static inline void q8_dot_begin(q8_dot_state * state) {
+    __asm__ volatile("mova.x.m %0" : "=r"(state->saved_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+}
+
+static inline void q8_dot_end(const q8_dot_state * state) {
+    __asm__ volatile("mova.m.x %0" ::"r"(state->saved_mask));
+}
+
+// Equivalent to q8_dot_reset+tile+reduce, without touching the mask register.
+// Caller is responsible for q8_dot_begin/end around the surrounding loop.
+static inline float q8_dot_compute(const block_q8_0 * q_row, const float * b_col, int64_t K_blocks) {
+    q8_dot_reset();
+    q8_dot_tile(q_row, b_col, K_blocks);
+    return q8_dot_reduce();
+}
+
+// Compute two row dots together while reusing the same loaded B chunks.
+//
+// Safe when every row starts at the same 32-byte offset, i.e. the Q8 row stride
+// is a multiple of 32. In that case the gather/alignment pattern is the same
+// for both rows at a given `kb`, so one set of B vector loads feeds both row
+// accumulators.
+static inline void q8_dot_compute_x2_aligned(const block_q8_0 * q_row0,
+                                             const block_q8_0 * q_row1,
+                                             const float *      b_col,
+                                             int64_t            K_blocks,
+                                             float *            out0,
+                                             float *            out1) {
+    const int32_t  gather_pattern[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+    const uint64_t gather_0_to_7     = 0x398a418820ULL;
+    __asm__ volatile("flw.ps f31, %[g]\n" : : [g] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+    __asm__ volatile(
+        "fbci.pi f20, 0\n"
+        "fbci.pi f21, 0\n" ::
+            : "f20", "f21");
+
+    for (int64_t kb = 0; kb < K_blocks; kb++) {
+        const block_q8_0 * blk0  = q_row0 + kb;
+        const block_q8_0 * blk1  = q_row1 + kb;
+        const float *      b_ptr = b_col + (kb << 5);
+
+        const uintptr_t qs_addr0    = (uintptr_t) blk0->qs;
+        const uintptr_t qs_addr1    = (uintptr_t) blk1->qs;
+        const uintptr_t qs_aligned0 = qs_addr0 & ~(uintptr_t) 31;
+        const uintptr_t qs_aligned1 = qs_addr1 & ~(uintptr_t) 31;
+        const int       fast_chunks = (int) ((32 - (qs_addr0 & 31)) >> 3);
+
+        if (fast_chunks >= 3) {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "fbci.pi     f11, 0\n"
+
+                "flw.ps      f12, %[bv0]\n"
+                "fg32b.ps    f16, %[gi](%[r0ap0])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f12, f10\n"
+                "fg32b.ps    f17, %[gi](%[r1ap0])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f12, f11\n"
+
+                "flw.ps      f13, %[bv1]\n"
+                "fg32b.ps    f16, %[gi](%[r0ap1])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f13, f10\n"
+                "fg32b.ps    f17, %[gi](%[r1ap1])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f13, f11\n"
+
+                "flw.ps      f14, %[bv2]\n"
+                "fg32b.ps    f16, %[gi](%[r0ap2])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f14, f10\n"
+                "fg32b.ps    f17, %[gi](%[r1ap2])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f14, f11\n"
+
+                "flw.ps      f15, %[bv3]\n"
+                "fgb.ps      f16, f31(%[r0ap3])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f15, f10\n"
+                "fgb.ps      f17, f31(%[r1ap3])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f15, f11\n"
+                :
+                : [gi] "r"(gather_0_to_7), [r0ap0] "r"(qs_addr0), [r0ap1] "r"(qs_aligned0 | ((qs_addr0 + 8) & 31)),
+                  [r0ap2] "r"(qs_aligned0 | ((qs_addr0 + 16) & 31)), [r0ap3] "r"(&blk0->qs[24]), [r1ap0] "r"(qs_addr1),
+                  [r1ap1] "r"(qs_aligned1 | ((qs_addr1 + 8) & 31)), [r1ap2] "r"(qs_aligned1 | ((qs_addr1 + 16) & 31)),
+                  [r1ap3] "r"(&blk1->qs[24]), [bv0] "m"(*(const float (*)[8]) & b_ptr[0]),
+                  [bv1] "m"(*(const float (*)[8]) & b_ptr[8]), [bv2] "m"(*(const float (*)[8]) & b_ptr[16]),
+                  [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17");
+        } else if (fast_chunks == 2) {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "fbci.pi     f11, 0\n"
+
+                "flw.ps      f12, %[bv0]\n"
+                "fg32b.ps    f16, %[gi](%[r0ap0])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f12, f10\n"
+                "fg32b.ps    f17, %[gi](%[r1ap0])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f12, f11\n"
+
+                "flw.ps      f13, %[bv1]\n"
+                "fg32b.ps    f16, %[gi](%[r0ap1])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f13, f10\n"
+                "fg32b.ps    f17, %[gi](%[r1ap1])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f13, f11\n"
+
+                "flw.ps      f14, %[bv2]\n"
+                "fgb.ps      f16, f31(%[r0ap2])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f14, f10\n"
+                "fgb.ps      f17, f31(%[r1ap2])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f14, f11\n"
+
+                "flw.ps      f15, %[bv3]\n"
+                "fgb.ps      f16, f31(%[r0ap3])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f15, f10\n"
+                "fgb.ps      f17, f31(%[r1ap3])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f15, f11\n"
+                :
+                : [gi] "r"(gather_0_to_7), [r0ap0] "r"(qs_addr0), [r0ap1] "r"(qs_aligned0 | ((qs_addr0 + 8) & 31)),
+                  [r0ap2] "r"(&blk0->qs[16]), [r0ap3] "r"(&blk0->qs[24]), [r1ap0] "r"(qs_addr1),
+                  [r1ap1] "r"(qs_aligned1 | ((qs_addr1 + 8) & 31)), [r1ap2] "r"(&blk1->qs[16]),
+                  [r1ap3] "r"(&blk1->qs[24]), [bv0] "m"(*(const float (*)[8]) & b_ptr[0]),
+                  [bv1] "m"(*(const float (*)[8]) & b_ptr[8]), [bv2] "m"(*(const float (*)[8]) & b_ptr[16]),
+                  [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17");
+        } else if (fast_chunks == 1) {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "fbci.pi     f11, 0\n"
+
+                "flw.ps      f12, %[bv0]\n"
+                "fg32b.ps    f16, %[gi](%[r0ap0])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f12, f10\n"
+                "fg32b.ps    f17, %[gi](%[r1ap0])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f12, f11\n"
+
+                "flw.ps      f13, %[bv1]\n"
+                "fgb.ps      f16, f31(%[r0ap1])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f13, f10\n"
+                "fgb.ps      f17, f31(%[r1ap1])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f13, f11\n"
+
+                "flw.ps      f14, %[bv2]\n"
+                "fgb.ps      f16, f31(%[r0ap2])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f14, f10\n"
+                "fgb.ps      f17, f31(%[r1ap2])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f14, f11\n"
+
+                "flw.ps      f15, %[bv3]\n"
+                "fgb.ps      f16, f31(%[r0ap3])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f15, f10\n"
+                "fgb.ps      f17, f31(%[r1ap3])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f15, f11\n"
+                :
+                : [gi] "r"(gather_0_to_7), [r0ap0] "r"(qs_addr0), [r0ap1] "r"(&blk0->qs[8]), [r0ap2] "r"(&blk0->qs[16]),
+                  [r0ap3] "r"(&blk0->qs[24]), [r1ap0] "r"(qs_addr1), [r1ap1] "r"(&blk1->qs[8]),
+                  [r1ap2] "r"(&blk1->qs[16]), [r1ap3] "r"(&blk1->qs[24]), [bv0] "m"(*(const float (*)[8]) & b_ptr[0]),
+                  [bv1] "m"(*(const float (*)[8]) & b_ptr[8]), [bv2] "m"(*(const float (*)[8]) & b_ptr[16]),
+                  [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17");
+        } else {
+            __asm__ volatile(
+                "fbci.pi     f10, 0\n"
+                "fbci.pi     f11, 0\n"
+
+                "flw.ps      f12, %[bv0]\n"
+                "fgb.ps      f16, f31(%[r0ap0])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f12, f10\n"
+                "fgb.ps      f17, f31(%[r1ap0])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f12, f11\n"
+
+                "flw.ps      f13, %[bv1]\n"
+                "fgb.ps      f16, f31(%[r0ap1])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f13, f10\n"
+                "fgb.ps      f17, f31(%[r1ap1])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f13, f11\n"
+
+                "flw.ps      f14, %[bv2]\n"
+                "fgb.ps      f16, f31(%[r0ap2])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f14, f10\n"
+                "fgb.ps      f17, f31(%[r1ap2])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f14, f11\n"
+
+                "flw.ps      f15, %[bv3]\n"
+                "fgb.ps      f16, f31(%[r0ap3])\n"
+                "fcvt.ps.pw  f16, f16\n"
+                "fmadd.ps    f10, f16, f15, f10\n"
+                "fgb.ps      f17, f31(%[r1ap3])\n"
+                "fcvt.ps.pw  f17, f17\n"
+                "fmadd.ps    f11, f17, f15, f11\n"
+                :
+                : [r0ap0] "r"(&blk0->qs[0]), [r0ap1] "r"(&blk0->qs[8]), [r0ap2] "r"(&blk0->qs[16]),
+                  [r0ap3] "r"(&blk0->qs[24]), [r1ap0] "r"(&blk1->qs[0]), [r1ap1] "r"(&blk1->qs[8]),
+                  [r1ap2] "r"(&blk1->qs[16]), [r1ap3] "r"(&blk1->qs[24]), [bv0] "m"(*(const float (*)[8]) & b_ptr[0]),
+                  [bv1] "m"(*(const float (*)[8]) & b_ptr[8]), [bv2] "m"(*(const float (*)[8]) & b_ptr[16]),
+                  [bv3] "m"(*(const float (*)[8]) & b_ptr[24])
+                : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17");
+        }
+
+        const uint32_t scale_raw0 = (uint32_t) blk0->d;
+        const uint32_t scale_raw1 = (uint32_t) blk1->d;
+        __asm__ volatile(
+            "fbcx.ps     f24, %[s0]\n"
+            "fcvt.ps.f16 f24, f24\n"
+            "fmadd.ps    f20, f10, f24, f20\n"
+            "fbcx.ps     f25, %[s1]\n"
+            "fcvt.ps.f16 f25, f25\n"
+            "fmadd.ps    f21, f11, f25, f21\n"
+            :
+            : [s0] "r"(scale_raw0), [s1] "r"(scale_raw1)
+            : "f20", "f21", "f24", "f25");
+    }
+
+    float result0;
+    float result1;
+    __asm__ __volatile__(
+        "fswizz.ps f1, f20, 0xB1 \n\t"
+        "fadd.ps   f2, f20, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result0)::"t0", "f1", "f2", "f3", "f4", "f5");
+    __asm__ __volatile__(
+        "fswizz.ps f1, f21, 0xB1 \n\t"
+        "fadd.ps   f2, f21, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result1)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+    *out0 = result0;
+    *out1 = result1;
+}
+
+// Compute dot product between f16 block and f32 column vector (NAIVE VERSION)
+// Scalar implementation for debugging - no vectorization
+// Block size: 32 f16 values (64 bytes = 1 cache line)
+static inline float compute_block_dot_product_f16_naive(const uint16_t * a_block, const float * b_col_start) {
+    float                acc_vec[8] __attribute__((aligned(32))) = { 0.0f };
+    // Byte offsets for 16-bit (half-word) elements
+    static const int32_t gather_pattern[8]                       = { 0, 2, 4, 6, 8, 10, 12, 14 };
+    unsigned long        temp_mask;
+
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    // Load the pattern once into f31 for the duration of all 4 chunks
+    __asm__ volatile("flw.ps f31, %[gather]\n" : : [gather] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+
+    for (int chunk = 0; chunk < 4; chunk++) {
+        // Correct pointers:
+        // a_block elements are 2 bytes, b_col elements are 4 bytes
+        const uint16_t * a_ptr = &a_block[chunk << 3];      // chunk * 8
+        const float *    b_ptr = &b_col_start[chunk << 3];  // chunk * 8
+
+        __asm__ volatile(
+            "flw.ps f10, %[acc]\n"
+            "fgh.ps f11, f31(%[a_p])\n"  // Uses {0,2,4,6,8,10,12,14} byte offsets
+            "fcvt.ps.f16 f11, f11\n"
+            "flw.ps f12, (%[b_p])\n"     // Standard vector load (32-bit floats)
+            "fmadd.ps f10, f11, f12, f10\n"
+            "fsw.ps f10, %[result]\n"
+
+            : [result] "=m"(*(float (*)[8]) acc_vec)
+            : [acc] "m"(*(const float (*)[8]) acc_vec), [a_p] "r"(a_ptr), [b_p] "r"(b_ptr)
+            : "f10", "f11", "f12");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    return acc_vec[0] + acc_vec[1] + acc_vec[2] + acc_vec[3] + acc_vec[4] + acc_vec[5] + acc_vec[6] + acc_vec[7];
+}
+
+// Compute dot product between f16 block and f32 column vector
+// SCALAR implementation for partial blocks
+// Block size: up to 32 f16 values (can handle partial blocks for misaligned K)
+static inline float compute_block_dot_product_f16_partial(const uint16_t * a_block,
+                                                          const float *    b_col_start,
+                                                          int              elements) {
+    // This matches compute_block_dot_product_f16_naive behavior
+    float sum = 0.0f;
+
+    for (int i = 0; i < elements; i++) {
+        float a_val = fp16_to_fp32(a_block[i]);
+        float b_val = b_col_start[i];
+        sum += a_val * b_val;
+    }
+
+    return sum;
+}
+
+// Compute dot product between f16 block and f16 column vector
+// Scalar implementation for generic non-matrix-engine fallback paths.
+static inline float compute_block_dot_product_f16_f16_partial(const uint16_t * a_block,
+                                                              const uint16_t * b_col_start,
+                                                              int              elements) {
+    float sum = 0.0f;
+
+    for (int i = 0; i < elements; i++) {
+        sum += fp16_to_fp32(a_block[i]) * fp16_to_fp32(b_col_start[i]);
+    }
+
+    return sum;
+}
+
+// Compute dot product between f16 block and f32 column vector
+// Vectorized: processes 8 elements at a time using ET vector instructions
+// Block size: 32 f16 values (64 bytes = 1 cache line)
+static inline float compute_block_dot_product_f16(const uint16_t * a_block, const float * b_col_start) {
+    return compute_block_dot_product_f16_partial(a_block, b_col_start, QK_F16);
+}
+
+// Compute dot product between f32 block and f32 column vector
+// Vectorized: processes 8 elements at a time using ET vector instructions
+// Block size: up to 16 f32 values (can handle partial blocks for misaligned K)
+static inline float compute_block_dot_product_f32_partial(const float * a_block,
+                                                          const float * b_col_start,
+                                                          int           elements) {
+    float acc_vec[8] = { 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f };  // Accumulator vector
+
+    // Calculate how many full 8-element chunks we can process
+    int vec_end = (elements / 8) * 8;
+
+    if (vec_end > 0) {
+        // Set mask register to enable all 8 vector elements
+        unsigned long temp_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+
+        // Process full 8-element chunks
+        for (int i = 0; i < vec_end; i += 8) {
+            // Vectorized f32 multiply-accumulate
+            __asm__ volatile(
+                "flw.ps f10, %[acc]\n"           // Load current accumulator (8 floats)
+                "flw.ps f11, %[a_vec]\n"         // Load 8 A values (f32)
+                "flw.ps f12, %[b_vec]\n"         // Load 8 B values (f32)
+                "fmadd.ps f10, f11, f12, f10\n"  // acc += a_vec * b_vec (8-wide)
+                "fsw.ps f10, %[result]\n"        // Store back to accumulator
+
+                : [result] "=m"(*(float (*)[8]) acc_vec)
+                : [acc] "m"(*(const float (*)[8]) acc_vec), [a_vec] "m"(*(const float (*)[8])(a_block + i)),
+                  [b_vec] "m"(*(const float (*)[8])(b_col_start + i))
+                : "f10", "f11", "f12");
+        }
+
+        // Restore original mask
+        __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+    }
+
+    // Horizontal sum: reduce 8 accumulator elements to single scalar
+    float final_sum = 0.0f;
+    for (int i = 0; i < 8; i++) {
+        final_sum += acc_vec[i];
+    }
+
+    // Handle remaining elements (< 8) with scalar operations
+    for (int i = vec_end; i < elements; i++) {
+        final_sum += a_block[i] * b_col_start[i];
+    }
+
+    return final_sum;
+}
+
+// Compute dot product between f32 block and f16 column vector
+// Scalar implementation for generic non-matrix-engine fallback paths.
+static inline float compute_block_dot_product_f32_f16_partial(const float *    a_block,
+                                                              const uint16_t * b_col_start,
+                                                              int              elements) {
+    float sum = 0.0f;
+
+    for (int i = 0; i < elements; i++) {
+        sum += a_block[i] * fp16_to_fp32(b_col_start[i]);
+    }
+
+    return sum;
+}
+
+// Compute dot product between f32 block and f32 column vector
+// Vectorized: processes 8 elements at a time using ET vector instructions
+// Block size: 16 f32 values (64 bytes = 1 cache line)
+static inline float compute_block_dot_product_f32(const float * a_block, const float * b_col_start) {
+    return compute_block_dot_product_f32_partial(a_block, b_col_start, QK_F32);
+
+    // float acc_vec[8];
+    // unsigned long old_mask;
+    // __asm__ volatile(
+    //     // Save current mask
+    //     "mova.x.m %[old_mask]\n"
+    //     // Enable all 8 lanes
+    //     "mov.m.x m0, x0, 0xFF\n"
+
+    //     "flw.ps  f11, %[a]\n"
+    //     "flw.ps  f12, %[b]\n"
+    //     "fmadd.ps f10, f11, f12, f10\n"
+    //     "fsw.ps  f10, %[out]\n"
+    //     "mova.m.x %[old_mask]\n"
+
+    //     : [out] "=m" (*(float(*)[8])acc_vec),
+    //       [old_mask] "=r"(old_mask)
+    //     : [a] "m" (*(const float(*)[8])a_block),
+    //       [b] "m" (*(const float(*)[8])b_col_start)
+    //     : "f10", "f11", "f12"
+    // );
+
+    // // Horizontal reduction
+    // return acc_vec[0] + acc_vec[1] + acc_vec[2] + acc_vec[3] +
+    //        acc_vec[4] + acc_vec[5] + acc_vec[6] + acc_vec[7];
+}
+
+#endif  // BLOCK_OPS_H
+
+static inline void __attribute__((always_inline)) q4_dot_reset(void) {
+    __asm__ volatile("fbci.pi f20, 0" ::: "f20");
+}
+
+static inline void __attribute__((always_inline)) q4_dot_tile(const block_q4_0 * q_row,
+                                                              const float *      b_col,
+                                                              int64_t            n_blocks) {
+    const int32_t gather_pattern[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+    __asm__ volatile("flw.ps f31, %[g]\n" : : [g] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+
+    for (int64_t kb = 0; kb < n_blocks; kb++) {
+        const block_q4_0 * blk   = q_row + kb;
+        const float *      b_ptr = b_col + (kb << 5);
+
+        __asm__ volatile(
+            "fbci.pi     f10, 0\n"
+
+            "fgb.ps      f11, f31(%[a_ptr0])\n"
+            "fandi.pi    f12, f11, 15\n"
+            "faddi.pi    f12, f12, -8\n"
+            "fcvt.ps.pw  f12, f12, rne\n"
+            "flw.ps      f13, %[b_low0]\n"
+            "fmadd.ps    f10, f12, f13, f10, rne\n"
+
+            "fsrli.pi    f14, f11, 4\n"
+            "fandi.pi    f14, f14, 15\n"
+            "faddi.pi    f14, f14, -8\n"
+            "fcvt.ps.pw  f14, f14, rne\n"
+            "flw.ps      f15, %[b_high0]\n"
+            "fmadd.ps    f10, f14, f15, f10, rne\n"
+
+            "fgb.ps      f11, f31(%[a_ptr1])\n"
+            "fandi.pi    f12, f11, 15\n"
+            "faddi.pi    f12, f12, -8\n"
+            "fcvt.ps.pw  f12, f12, rne\n"
+            "flw.ps      f13, %[b_low1]\n"
+            "fmadd.ps    f10, f12, f13, f10, rne\n"
+
+            "fsrli.pi    f14, f11, 4\n"
+            "fandi.pi    f14, f14, 15\n"
+            "faddi.pi    f14, f14, -8\n"
+            "fcvt.ps.pw  f14, f14, rne\n"
+            "flw.ps      f15, %[b_high1]\n"
+            "fmadd.ps    f10, f14, f15, f10, rne\n"
+            :
+            : [a_ptr0] "r"(&blk->qs[0]), [b_low0] "m"(*(const float (*)[8]) & b_ptr[0]),
+              [b_high0] "m"(*(const float (*)[8]) & b_ptr[16]), [a_ptr1] "r"(&blk->qs[8]),
+              [b_low1] "m"(*(const float (*)[8]) & b_ptr[8]), [b_high1] "m"(*(const float (*)[8]) & b_ptr[24])
+            : "f10", "f11", "f12", "f13", "f14", "f15");
+
+        uint32_t scale_raw = (uint32_t) blk->d;
+        __asm__ volatile(
+            "fbcx.ps f15, %[sb]\n"
+            "fcvt.ps.f16 f15, f15\n"
+            "fmadd.ps f20, f10, f15, f20\n"
+            :
+            : [sb] "r"(scale_raw)
+            : "f15", "f20");
+    }
+}
+
+static inline float __attribute__((always_inline)) q4_dot_reduce(void) {
+    float result;
+    __asm__ __volatile__(
+        "fswizz.ps f1, f20, 0xB1 \n\t"
+        "fadd.ps   f2, f20, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result)::"t0", "f1", "f2", "f3", "f4", "f5");
+    return result;
+}
+
+static inline float compute_row_dot_q4_0(const block_q4_0 * q_row, const float * b_col, int64_t K_blocks) {
+    unsigned long saved_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+    q4_dot_reset();
+    q4_dot_tile(q_row, b_col, K_blocks);
+    float result = q4_dot_reduce();
+    __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    return result;
+}
+
+typedef struct {
+    unsigned long saved_mask;
+} q4_dot_state;
+
+static inline void q4_dot_begin(q4_dot_state * state) {
+    __asm__ volatile("mova.x.m %0" : "=r"(state->saved_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+}
+
+static inline void q4_dot_end(const q4_dot_state * state) {
+    __asm__ volatile("mova.m.x %0" ::"r"(state->saved_mask));
+}
+
+static inline float q4_dot_compute(const block_q4_0 * q_row, const float * b_col, int64_t K_blocks) {
+    q4_dot_reset();
+    q4_dot_tile(q_row, b_col, K_blocks);
+    return q4_dot_reduce();
+}
+
+static inline void q4_dot_compute_x2_aligned(const block_q4_0 * q_row0,
+                                             const block_q4_0 * q_row1,
+                                             const float *      b_col,
+                                             int64_t            K_blocks,
+                                             float *            out0,
+                                             float *            out1) {
+    const int32_t gather_pattern[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+    __asm__ volatile("flw.ps f31, %[g]\n" : : [g] "m"(*(const int32_t (*)[8]) gather_pattern) : "f31");
+    __asm__ volatile(
+        "fbci.pi f20, 0\n"
+        "fbci.pi f21, 0\n" ::
+            : "f20", "f21");
+
+    for (int64_t kb = 0; kb < K_blocks; kb++) {
+        const block_q4_0 * blk0  = q_row0 + kb;
+        const block_q4_0 * blk1  = q_row1 + kb;
+        const float *      b_ptr = b_col + (kb << 5);
+
+        __asm__ volatile(
+            "fbci.pi     f10, 0\n"
+            "fbci.pi     f16, 0\n"
+
+            "flw.ps      f13, %[b_low0]\n"
+            "flw.ps      f15, %[b_high0]\n"
+
+            "fgb.ps      f11, f31(%[a_ptr0_0])\n"
+            "fgb.ps      f17, f31(%[a_ptr1_0])\n"
+
+            "fandi.pi    f12, f11, 15\n"
+            "faddi.pi    f12, f12, -8\n"
+            "fcvt.ps.pw  f12, f12, rne\n"
+            "fmadd.ps    f10, f12, f13, f10, rne\n"
+
+            "fandi.pi    f18, f17, 15\n"
+            "faddi.pi    f18, f18, -8\n"
+            "fcvt.ps.pw  f18, f18, rne\n"
+            "fmadd.ps    f16, f18, f13, f16, rne\n"
+
+            "fsrli.pi    f14, f11, 4\n"
+            "fandi.pi    f14, f14, 15\n"
+            "faddi.pi    f14, f14, -8\n"
+            "fcvt.ps.pw  f14, f14, rne\n"
+            "fmadd.ps    f10, f14, f15, f10, rne\n"
+
+            "fsrli.pi    f19, f17, 4\n"
+            "fandi.pi    f19, f19, 15\n"
+            "faddi.pi    f19, f19, -8\n"
+            "fcvt.ps.pw  f19, f19, rne\n"
+            "fmadd.ps    f16, f19, f15, f16, rne\n"
+
+            "flw.ps      f13, %[b_low1]\n"
+            "flw.ps      f15, %[b_high1]\n"
+
+            "fgb.ps      f11, f31(%[a_ptr0_1])\n"
+            "fgb.ps      f17, f31(%[a_ptr1_1])\n"
+
+            "fandi.pi    f12, f11, 15\n"
+            "faddi.pi    f12, f12, -8\n"
+            "fcvt.ps.pw  f12, f12, rne\n"
+            "fmadd.ps    f10, f12, f13, f10, rne\n"
+
+            "fandi.pi    f18, f17, 15\n"
+            "faddi.pi    f18, f18, -8\n"
+            "fcvt.ps.pw  f18, f18, rne\n"
+            "fmadd.ps    f16, f18, f13, f16, rne\n"
+
+            "fsrli.pi    f14, f11, 4\n"
+            "fandi.pi    f14, f14, 15\n"
+            "faddi.pi    f14, f14, -8\n"
+            "fcvt.ps.pw  f14, f14, rne\n"
+            "fmadd.ps    f10, f14, f15, f10, rne\n"
+
+            "fsrli.pi    f19, f17, 4\n"
+            "fandi.pi    f19, f19, 15\n"
+            "faddi.pi    f19, f19, -8\n"
+            "fcvt.ps.pw  f19, f19, rne\n"
+            "fmadd.ps    f16, f19, f15, f16, rne\n"
+            :
+            : [a_ptr0_0] "r"(&blk0->qs[0]), [a_ptr0_1] "r"(&blk0->qs[8]), [a_ptr1_0] "r"(&blk1->qs[0]),
+              [a_ptr1_1] "r"(&blk1->qs[8]), [b_low0] "m"(*(const float (*)[8]) & b_ptr[0]),
+              [b_high0] "m"(*(const float (*)[8]) & b_ptr[16]), [b_low1] "m"(*(const float (*)[8]) & b_ptr[8]),
+              [b_high1] "m"(*(const float (*)[8]) & b_ptr[24])
+            : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19");
+
+        const uint32_t scale_raw0 = (uint32_t) blk0->d;
+        const uint32_t scale_raw1 = (uint32_t) blk1->d;
+        __asm__ volatile(
+            "fbcx.ps     f24, %[s0]\n"
+            "fcvt.ps.f16 f24, f24\n"
+            "fmadd.ps    f20, f10, f24, f20\n"
+            "fbcx.ps     f25, %[s1]\n"
+            "fcvt.ps.f16 f25, f25\n"
+            "fmadd.ps    f21, f16, f25, f21\n"
+            :
+            : [s0] "r"(scale_raw0), [s1] "r"(scale_raw1)
+            : "f20", "f21", "f24", "f25");
+    }
+
+    float result0, result1;
+    __asm__ __volatile__(
+        "fswizz.ps f1, f20, 0xB1 \n\t"
+        "fadd.ps   f2, f20, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result0)::"t0", "f1", "f2", "f3", "f4", "f5");
+    __asm__ __volatile__(
+        "fswizz.ps f1, f21, 0xB1 \n\t"
+        "fadd.ps   f2, f21, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result1)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+    *out0 = result0;
+    *out1 = result1;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/clamp_f32.c b/ggml/src/ggml-et/et-kernels/src/clamp_f32.c
new file mode 100644 (file)
index 0000000..cf091b4
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/clamp_f32.c
@@ -0,0 +1,120 @@
+//******************************************************************************
+// CLAMP F32 Kernel
+// Element-wise: dst[i] = min(max(src0[i], min_val), max_val)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_clamp_params {
+    struct ggml_tensor src0;  // F32 input  (contiguous)
+    struct ggml_tensor dst;   // F32 output (contiguous; may alias src0.data)
+    float              min_val;
+    float              max_val;
+};
+
+// Vectorized fmax/fmin clamp with scalar tail. n may be any non-negative int.
+static inline void clamp_block_f32(float * dst, const float * src, float min_val, float max_val, int32_t n) {
+    int32_t       i       = 0;
+    const int32_t vec_end = (n / 8) * 8;
+
+    if (vec_end > 0) {
+        unsigned long temp_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+        for (; i < vec_end; i += 8) {
+            __asm__ volatile(
+                "flw.ps  f10, %[s]\n"
+                "fbc.ps  f11, %[mn]\n"
+                "fbc.ps  f12, %[mx]\n"
+                "fmax.ps f13, f10, f11\n"
+                "fmin.ps f13, f13, f12\n"
+                "fsw.ps  f13, %[d]\n"
+                : [d] "=m"(*(float (*)[8]) & dst[i])
+                : [s] "m"(*(const float (*)[8]) & src[i]), [mn] "m"(min_val), [mx] "m"(max_val)
+                : "f10", "f11", "f12", "f13");
+        }
+
+        __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+    }
+
+    for (; i < n; i++) {
+        float v = src[i];
+        if (v < min_val) {
+            v = min_val;
+        }
+        if (v > max_val) {
+            v = max_val;
+        }
+        dst[i] = v;
+    }
+}
+
+int entry_point(struct ggml_et_clamp_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t total_elements = src0->ne[0] * src0->ne[1] * src0->ne[2] * src0->ne[3];
+    if (total_elements <= 0) {
+        return 0;
+    }
+
+    const float min_val = params->min_val;
+    const float max_val = params->max_val;
+
+    // Distribute by cache lines (16 F32 elements). Each thread owns disjoint
+    // cache lines, so a partial trailing line is written by exactly one
+    // thread — safe under non-coherent caches.
+    const int64_t elems_per_cl = 16;
+    const int64_t total_cl     = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+    const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+    const int64_t cl_start      = (int64_t) thread_id * cl_per_thread;
+    int64_t       cl_end        = cl_start + cl_per_thread;
+    if (cl_end > total_cl) {
+        cl_end = total_cl;
+    }
+    if (cl_start >= total_cl) {
+        return 0;
+    }
+
+    const int64_t es = cl_start * elems_per_cl;
+    int64_t       ee = cl_end * elems_per_cl;
+    if (ee > total_elements) {
+        ee = total_elements;
+    }
+
+    clamp_block_f32(dst_data + es, src0_data + es, min_val, max_val, (int32_t) (ee - es));
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/concat_f32.c b/ggml/src/ggml-et/et-kernels/src/concat_f32.c
new file mode 100644 (file)
index 0000000..dbdf4ae
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/concat_f32.c
@@ -0,0 +1,175 @@
+//******************************************************************************
+// Concat F32 Kernel
+// Concatenates two F32 tensors along a specified dimension.
+// All copies are aligned to cacheline boundaries (64 bytes = 16 floats).
+//
+// For dim >= 1, entire rows are copied from src0 or src1 into dst.
+// For dim == 0, use:
+// - a fast vector path when both source row segments are cacheline-aligned
+// - a scalar stride-aware path otherwise
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+#include <string.h>
+
+struct ggml_et_concat_params {
+    struct ggml_tensor src0;  // F32 input tensor 0
+    struct ggml_tensor src1;  // F32 input tensor 1
+    struct ggml_tensor dst;   // F32 output tensor
+    int32_t            dim;   // Concatenation dimension
+};
+
+// Copy n floats from src to dst using 8-wide vector loads/stores.
+// n must be a multiple of 16 (cacheline-aligned).
+static inline void copy_row_aligned(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps f11, %[src_vec]\n"
+            "fsw.ps f11, %[dst_vec]\n"
+            : [dst_vec] "=m"(*(float (*)[8]) & dst[i])
+            : [src_vec] "m"(*(const float (*)[8]) & src[i])
+            : "f11");
+    }
+}
+
+int entry_point(struct ggml_et_concat_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * dst  = &params->dst;
+    int32_t              dim  = params->dim;
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * src1_data = (float *) src1->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3];
+    const int64_t ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3];
+    const int64_t ne0 = dst->ne[0], ne1 = dst->ne[1], ne2 = dst->ne[2], ne3 = dst->ne[3];
+
+    // src strides in bytes
+    const size_t nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    const size_t nb10 = src1->nb[0], nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3];
+    // dst strides in bytes
+    const size_t dnb1 = dst->nb[1], dnb2 = dst->nb[2], dnb3 = dst->nb[3];
+
+    // Total rows across all higher dimensions
+    const int64_t total_rows = ne1 * ne2 * ne3;
+
+    // Generic slow path for dim==0 when either source segment is not suitable for
+    // aligned vector copies. Threading is done by cacheline-aligned row groups,
+    // so writers do not share destination cache lines.
+    if (dim == 0 && (ne00 % 16 != 0 || ne10 % 16 != 0 || nb00 != sizeof(float) || nb10 != sizeof(float))) {
+        const int64_t rows_per_group = et_rows_per_cacheline_group(ne0, sizeof(float));
+        const int64_t total_groups   = (total_rows + rows_per_group - 1) / rows_per_group;
+
+        for (int64_t grp = thread_id; grp < total_groups; grp += num_threads) {
+            const int64_t row_start = grp * rows_per_group;
+            int64_t       row_end   = row_start + rows_per_group;
+            if (row_end > total_rows) {
+                row_end = total_rows;
+            }
+
+            for (int64_t row = row_start; row < row_end; row++) {
+                int64_t i1 = row % ne1;
+                int64_t i2 = (row / ne1) % ne2;
+                int64_t i3 = row / (ne1 * ne2);
+
+                float * dst_row = (float *) ((char *) dst_data + i1 * dnb1 + i2 * dnb2 + i3 * dnb3);
+
+                const char * s0_base = (const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03;
+                for (int64_t i0 = 0; i0 < ne00; i0++) {
+                    dst_row[i0] = *(const float *) (s0_base + i0 * nb00);
+                }
+
+                const char * s1_base = (const char *) src1_data + i1 * nb11 + i2 * nb12 + i3 * nb13;
+                for (int64_t i0 = 0; i0 < ne10; i0++) {
+                    dst_row[ne00 + i0] = *(const float *) (s1_base + i0 * nb10);
+                }
+            }
+        }
+        return 0;
+    }
+
+    // Standard path: ne0 % 16 == 0, aligned rows
+    for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+        // Decompose linear row index into (i1, i2, i3)
+        int64_t i1 = row % ne1;
+        int64_t i2 = (row / ne1) % ne2;
+        int64_t i3 = row / (ne1 * ne2);
+
+        float * dst_row = (float *) ((char *) dst_data + i1 * dnb1 + i2 * dnb2 + i3 * dnb3);
+
+        if (dim == 0) {
+            // Concat along innermost dimension: [src0_row | src1_row]
+            // Both ne00 and ne10 are multiples of 16 (cacheline-aligned)
+            const float * s0_row = (const float *) ((const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03);
+            const float * s1_row = (const float *) ((const char *) src1_data + i1 * nb11 + i2 * nb12 + i3 * nb13);
+
+            copy_row_aligned(dst_row, s0_row, (int32_t) ne00);
+            copy_row_aligned(dst_row + ne00, s1_row, (int32_t) ne10);
+
+        } else if (dim == 1) {
+            // Concat along dim 1: first ne01 rows from src0, rest from src1
+            if (i1 < ne01) {
+                const float * s0_row = (const float *) ((const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03);
+                copy_row_aligned(dst_row, s0_row, (int32_t) ne0);
+            } else {
+                const float * s1_row =
+                    (const float *) ((const char *) src1_data + (i1 - ne01) * nb11 + i2 * nb12 + i3 * nb13);
+                copy_row_aligned(dst_row, s1_row, (int32_t) ne0);
+            }
+
+        } else if (dim == 2) {
+            // Concat along dim 2: first ne02 slices from src0, rest from src1
+            if (i2 < ne02) {
+                const float * s0_row = (const float *) ((const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03);
+                copy_row_aligned(dst_row, s0_row, (int32_t) ne0);
+            } else {
+                const float * s1_row =
+                    (const float *) ((const char *) src1_data + i1 * nb11 + (i2 - ne02) * nb12 + i3 * nb13);
+                copy_row_aligned(dst_row, s1_row, (int32_t) ne0);
+            }
+
+        } else {
+            // dim == 3: first ne03 batches from src0, rest from src1
+            if (i3 < ne03) {
+                const float * s0_row = (const float *) ((const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03);
+                copy_row_aligned(dst_row, s0_row, (int32_t) ne0);
+            } else {
+                const float * s1_row =
+                    (const float *) ((const char *) src1_data + i1 * nb11 + i2 * nb12 + (i3 - ne03) * nb13);
+                copy_row_aligned(dst_row, s1_row, (int32_t) ne0);
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/cont_f16.c b/ggml/src/ggml-et/et-kernels/src/cont_f16.c
new file mode 100644 (file)
index 0000000..3ef08da
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/cont_f16.c
@@ -0,0 +1,107 @@
+//******************************************************************************
+// Bare Metal CONT F16 Kernel
+// Converts non-contiguous F16 tensors to contiguous memory layout
+//
+// Note: F16 is represented as uint16_t (IEEE 754 binary16 format)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+struct ggml_et_cont_params {
+    struct ggml_tensor src0;  // F16 input tensor (non-contiguous)
+    struct ggml_tensor dst;   // F16 output tensor (contiguous)
+};
+
+int entry_point(struct ggml_et_cont_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = 2048;  //get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;  // Non-contiguous input
+    struct ggml_tensor * dst  = &params->dst;   // Contiguous output
+
+    if (src0->type != GGML_TYPE_F16 || dst->type != GGML_TYPE_F16) {
+        return -1;  // Unsupported type combination
+    }
+
+    uint16_t * src0_data = (uint16_t *) src0->data;
+    uint16_t * dst_data  = (uint16_t *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    const int64_t src_elements = src0->ne[0] * src0->ne[1] * src0->ne[2] * src0->ne[3];
+    const int64_t dst_elements = dst->ne[0] * dst->ne[1] * dst->ne[2] * dst->ne[3];
+    if (src_elements != dst_elements) {
+        return -1;  // Element count mismatch
+    }
+
+    // Source tensor dimensions and strides
+    const int64_t ne00 = src0->ne[0];
+    const int64_t ne01 = src0->ne[1];
+    const int64_t ne02 = src0->ne[2];
+    const int64_t ne03 = src0->ne[3];
+
+    const int64_t nb00 = src0->nb[0];
+    const int64_t nb01 = src0->nb[1];
+    const int64_t nb02 = src0->nb[2];
+    const int64_t nb03 = src0->nb[3];
+
+    // Parallelize by rows (dimension 1)
+    const int64_t total_rows      = ne01;
+    const int64_t rows_per_thread = (total_rows + num_threads - 1) / num_threads;
+    const int64_t start_row       = thread_id * rows_per_thread;
+    const int64_t end_row = (start_row + rows_per_thread < total_rows) ? (start_row + rows_per_thread) : total_rows;
+
+    if (start_row >= total_rows) {
+        return 0;
+    }
+
+    // Iterate over source tensor dimensions
+    for (int64_t i03 = 0; i03 < ne03; i03++) {
+        for (int64_t i02 = 0; i02 < ne02; i02++) {
+            // Calculate base linear index for this (i03, i02) slice in destination
+            const int64_t dst_linear_base = i03 * ne02 * ne01 * ne00 + i02 * ne01 * ne00;
+
+            // Process this thread's assigned rows
+            for (int64_t i01 = start_row; i01 < end_row; i01++) {
+                // Linear index for start of this row in destination
+                const int64_t dst_linear_row_base = dst_linear_base + i01 * ne00;
+
+                // Inner loop over dimension 0
+                for (int64_t i00 = 0; i00 < ne00; i00++) {
+                    // Source offset using non-contiguous strides
+                    const int64_t    src_offset_bytes = i00 * nb00 + i01 * nb01 + i02 * nb02 + i03 * nb03;
+                    const uint16_t * src_ptr = (const uint16_t *) ((const char *) src0_data + src_offset_bytes);
+
+                    // Destination linear index (contiguous layout)
+                    const int64_t dst_linear_idx = dst_linear_row_base + i00;
+
+                    // Use atomic store for thread safety
+                    atomic_store_f16((volatile uint16_t *) &dst_data[dst_linear_idx], *src_ptr);
+                }
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/cont_f32.c b/ggml/src/ggml-et/et-kernels/src/cont_f32.c
new file mode 100644 (file)
index 0000000..88c8480
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/cont_f32.c
@@ -0,0 +1,248 @@
+//******************************************************************************
+// Bare Metal CONT F32 Kernel
+// Converts non-contiguous tensors to contiguous memory layout
+//
+// Fast path:    src contiguous: flat vectorized copy by cache lines
+// Aligned path: nb00==4 and ne00 % 16 == 0: distribute rows, no coherency issue
+// Unaligned:    nb00==4 and ne00 not aligned: distribute by cache lines,
+//               reverse-compute src coords, handle partial rows at boundaries
+// Fallback:     nb00 != 4: scalar per-element
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct ggml_et_cont_params {
+    struct ggml_tensor src0;  // F32 input tensor (non-contiguous)
+    struct ggml_tensor dst;   // F32 output tensor (contiguous)
+};
+
+// Vectorized copy with scalar tail
+static inline void vec_copy_f32(float * dst, const float * src, int32_t n) {
+    int32_t       i       = 0;
+    const int32_t vec_end = (n / 8) * 8;
+    for (; i < vec_end; i += 8) {
+        __asm__ volatile(
+            "flw.ps f10, %[s]\n"
+            "fsw.ps f10, %[d]\n"
+            : [d] "=m"(*(float (*)[8]) & dst[i])
+            : [s] "m"(*(const float (*)[8]) & src[i])
+            : "f10");
+    }
+    for (; i < n; i++) {
+        dst[i] = src[i];
+    }
+}
+
+// Scalar copy
+static inline void scalar_copy_f32(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        dst[i] = src[i];
+    }
+}
+
+// static inline size_t tensor_bytes(const struct ggml_tensor *t) {
+//     return (size_t)t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+// }
+
+int entry_point(struct ggml_et_cont_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+    // evict_region_past_l2(src0_data, tensor_bytes(src0));
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne00 = src0->ne[0];
+    const int64_t ne01 = src0->ne[1];
+    const int64_t ne02 = src0->ne[2];
+    const int64_t ne03 = src0->ne[3];
+
+    const int64_t nb00 = src0->nb[0];
+    const int64_t nb01 = src0->nb[1];
+    const int64_t nb02 = src0->nb[2];
+    const int64_t nb03 = src0->nb[3];
+
+    const int64_t total_elements = ne00 * ne01 * ne02 * ne03;
+
+    if (total_elements == 0) {
+        return 0;
+    }
+
+    const bool src_contiguous = ggml_tensor_is_contiguous(src0, 4);
+
+    //==========================================================================
+    // Fast path: src is contiguous: flat vectorized copy by cache lines
+    //==========================================================================
+    if (src_contiguous) {
+        const int64_t elems_per_cl = 16;
+        const int64_t total_cl     = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+        const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+        const int64_t cl_start      = thread_id * cl_per_thread;
+        int64_t       cl_end        = cl_start + cl_per_thread;
+        if (cl_end > total_cl) {
+            cl_end = total_cl;
+        }
+        if (cl_start >= total_cl) {
+            return 0;
+        }
+
+        const int64_t es = cl_start * elems_per_cl;
+        int64_t       ee = cl_end * elems_per_cl;
+        if (ee > total_elements) {
+            ee = total_elements;
+        }
+
+        vec_copy_f32(dst_data + es, src0_data + es, (int32_t) (ee - es));
+        return 0;
+    }
+
+    //==========================================================================
+    // Non-contiguous paths: require nb00==4 (dim 0 contiguous in src)
+    //==========================================================================
+    if (nb00 != 4) {
+        // Fully non-contiguous scalar fallback — distribute by cache lines
+        const int64_t elems_per_cl = 16;
+        const int64_t total_cl     = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+        const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+        const int64_t cl_start      = thread_id * cl_per_thread;
+        int64_t       cl_end        = cl_start + cl_per_thread;
+        if (cl_end > total_cl) {
+            cl_end = total_cl;
+        }
+        if (cl_start >= total_cl) {
+            return 0;
+        }
+
+        const int64_t es = cl_start * elems_per_cl;
+        int64_t       ee = cl_end * elems_per_cl;
+        if (ee > total_elements) {
+            ee = total_elements;
+        }
+
+        for (int64_t idx = es; idx < ee; idx++) {
+            const int64_t i00  = idx % ne00;
+            const int64_t rem1 = idx / ne00;
+            const int64_t i01  = rem1 % ne01;
+            const int64_t rem2 = rem1 / ne01;
+            const int64_t i02  = rem2 % ne02;
+            const int64_t i03  = rem2 / ne02;
+
+            const float * sp =
+                (const float *) ((const char *) src0_data + i00 * nb00 + i01 * nb01 + i02 * nb02 + i03 * nb03);
+            dst_data[idx] = *sp;
+        }
+        return 0;
+    }
+
+    // nb00 == 4 from here: dim 0 is contiguous in src
+
+    //==========================================================================
+    // Aligned path: ne00 % 16 == 0: rows are cache-line aligned, distribute rows
+    //==========================================================================
+    if (ne00 % 16 == 0) {
+        const int64_t total_rows      = ne01 * ne02 * ne03;
+        const int64_t rows_per_thread = (total_rows + num_threads - 1) / num_threads;
+        const int64_t start_row       = thread_id * rows_per_thread;
+        const int64_t end_row = (start_row + rows_per_thread < total_rows) ? (start_row + rows_per_thread) : total_rows;
+
+        if (start_row >= total_rows) {
+            return 0;
+        }
+
+        for (int64_t ir = start_row; ir < end_row; ir++) {
+            const int64_t i03 = ir / (ne02 * ne01);
+            const int64_t i02 = (ir - i03 * ne02 * ne01) / ne01;
+            const int64_t i01 = ir - i03 * ne02 * ne01 - i02 * ne01;
+
+            const float * src_row = (const float *) ((const char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03);
+            float *       dst_row = dst_data + ir * ne00;
+
+            vec_copy_f32(dst_row, src_row, (int32_t) ne00);
+        }
+        return 0;
+    }
+
+    //==========================================================================
+    // Unaligned path: ne00 % 16 != 0, nb00 == 4
+    // Distribute cache-line-aligned chunks of dst, handle partial rows at edges
+    //==========================================================================
+    {
+        const int64_t elems_per_cl = 16;
+        const int64_t total_cl     = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+        const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+        const int64_t cl_start      = thread_id * cl_per_thread;
+        int64_t       cl_end        = cl_start + cl_per_thread;
+        if (cl_end > total_cl) {
+            cl_end = total_cl;
+        }
+        if (cl_start >= total_cl) {
+            return 0;
+        }
+
+        const int64_t es = cl_start * elems_per_cl;
+        int64_t       ee = cl_end * elems_per_cl;
+        if (ee > total_elements) {
+            ee = total_elements;
+        }
+
+        int64_t pos = es;
+
+        // Compute starting row coordinates
+        int64_t row_idx = pos / ne00;
+        int64_t col     = pos % ne00;
+
+        while (pos < ee) {
+            // Decompose row_idx -> (i01, i02, i03)
+            const int64_t i03 = row_idx / (ne02 * ne01);
+            const int64_t i02 = (row_idx - i03 * ne02 * ne01) / ne01;
+            const int64_t i01 = row_idx - i03 * ne02 * ne01 - i02 * ne01;
+
+            const float * src_row = (const float *) ((const char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03);
+
+            // How many elements left in this row and in our chunk
+            int64_t row_remaining   = ne00 - col;
+            int64_t chunk_remaining = ee - pos;
+            int32_t n               = (int32_t) (row_remaining < chunk_remaining ? row_remaining : chunk_remaining);
+
+            vec_copy_f32(dst_data + pos, src_row + col, n);
+
+            pos += n;
+            col = 0;  // subsequent rows start at column 0
+            row_idx++;
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/conv_2d_f32_me.c b/ggml/src/ggml-et/et-kernels/src/conv_2d_f32_me.c
new file mode 100644 (file)
index 0000000..7405379
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/conv_2d_f32_me.c
@@ -0,0 +1,807 @@
+//******************************************************************************
+// 2D F32 convolution on the ET-SoC-1 matrix engine (GGML CONV_2D layout).
+//
+// LAYOUT (matches GGML's standard CONV_2D, cwhn=false; wireable directly):
+//   src1 input :  ne = [W, H, Cin, N=1]      memory: input [n][cin][h][w]
+//   src0 filter:  ne = [Kw, Kh, Cin, Cout]   memory: filter[oc][ic][kh][kw]
+//   dst  output:  ne = [W, H, Cout, N=1]     memory: output[n][oc][h][w]
+//
+// CONSTRAINTS (enforced at supports_op):
+//   F32 throughout, N == 1, Cin % 16 == 0, Cout % 16 == 0, positive
+//   stride/pad, dilation == 1. Tile/L2SCP limits are checked here.
+//
+// MEMORY MODEL:
+//   Each active shire uses its own 2 MB local L2 SCP:
+//     filter slice | pin buffer 0 | pin buffer 1? | output staging? | scratch
+//
+//   The filter slice contains only the output-channel tiles (`mt`) consumed
+//   by this shire's tile assignment. That keeps hart-0's inner-loop
+//   tensor_loads local to the shire and avoids packing unused filter slabs.
+//
+// THREADING (multi-minion, multi-shire):
+//   PHASE 1 (per-shire filter pack): hart-1's pack this shire's filter
+//     slice into local L2 SCP. Work is slab-striped across the 32 minions.
+//
+//   PHASE 2 (per-shire compute): hart-1's pack the input pin chunks while
+//     hart-0's run the matrix engine. Pin double-buffering hides the next
+//     chunk pack behind the current chunk's FMA pipeline when Cin does not
+//     fit in one local buffer.
+//
+// PERFORMANCE STRATEGIES:
+//   1. Local filter slice: pack only the `mt` values this shire consumes;
+//      inner-loop tensor_loads stay shire-local.
+//   2. Pin Cin streaming + chunk double-buffer: pack one
+//      chunk while computing the prior one.
+//   3. TenC save/restore: f0..f31 IS the TenC accumulator;
+//      spill/refill via L2 SCP scratch lets each hart hold multiple
+//      partial accumulators across chunks.
+//   4. OW%16 staging: for partial-tile output, write to a
+//      padded L2 SCP region then have one hart scalar-emit to DRAM.
+//
+// WHY THE FILTER PACK EXISTS:
+//   GGML's OIHW filter has stride Kh*Kw*4 between consecutive Cin elements
+//   (e.g. 36 bytes for 3x3) — usually NOT a multiple of 64, so plain
+//   tensor_load cannot gather it directly. The per-slab pack into a
+//   Cin-innermost form gives every per-tap slab a flat 64-byte row stride
+//   and enables tensor_load.
+//
+//   Picking M=Cout, N=W means TenC's natural row stride matches NCHW
+//   output's per-channel stride (H*W*4) — the output store is a clean
+//   tensor_store with no transpose. The price is that conv_size/conv_ctrl
+//   no longer help with W boundaries (mask gates M, not N), so we handle
+//   boundaries up-front by zero-padding the input in L2SCP.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+#include "tensor.h"
+
+#include <etsoc/common/utils.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#define TILE               16 /* matrix engine native tile in M, K, N */
+/* L1 SCP layout: A double-buffered, B single-buffered. Per the SDK doc
+   `dst_start` is a 6-bit field (max 63) but empirical testing shows the
+   physical L1 SCP per minion is 48 lines — writes to lines >= 48 corrupt.
+   So we get 3 × 16-line buffers max: A_0, A_1, B. Pick A as the
+   double-buffered operand (filter-slab loads, the longer of the two). */
+#define LSCP_A_0           0  /* A buffer 0 at L1 SCP lines 0..15  */
+#define LSCP_A_1           16 /* A buffer 1 at L1 SCP lines 16..31 */
+#define LSCP_B             32 /* B (single buffer) at lines 32..47 */
+#define N_MIN_PER_SHIRE    32 /* ET-SoC-1 geometry: 32 minions/shire  */
+#define N_SHIRES           32 /* default active shire count           */
+#define MAX_TILES_PER_HART 2  /* per-hart TenC slots (save/restore)   */
+#define MAX_DBL_BUFS       2  /* chunk pack buffers (double-buffered) */
+
+/* Per-shire L2 SCP local budget. Per-shire SCP is 2 MB; we cap at
+   1984 KB to leave 64 KB headroom for per-hart TenC scratch (32 minions ×
+   2 slots × 1 KB), which lives at the tail of the SCP outside the pin
+   sizing budget. Bigger budget here means bigger feasible chunk_KT,
+   which means fewer chunks (each chunk costs 2 SHIRE barriers + ~30
+   TenC save/restore events per hart). */
+#define LOCAL_BUDGET (1984 * 1024)
+
+/* Cap on the per-shire filter region in local L2 SCP. The shire packs the
+   mt values it can consume under the current tile assignment, rather than
+   the whole Cout dimension. Reads in the inner loop are then fully
+   shire-local — no NoC fanout. */
+#define LOCAL_FILTER_CAP (1024 * 1024)                      /* 1 MB / shire ceiling */
+
+#define SLAB_BYTES ((uint64_t) TILE * TILE * sizeof(float)) /* 1024 */
+#define SLAB_LINES ((SLAB_BYTES + 63) / 64)                 /* 16   */
+
+/* Upper bound on the number of distinct mt values a single shire may pack.
+   This keeps the mt list stack-resident. Shapes that need more should fall
+   back until the filter-slice bookkeeping is made dynamic. */
+#define MAX_MY_MT (N_MIN_PER_SHIRE * MAX_TILES_PER_HART)
+
+typedef struct {
+    int mt;
+    int mt_idx;
+    int oh;
+    int ow_base;
+} conv_tile_t;
+
+static inline int ceil_div_i32(int x, int y) {
+    return (x + y - 1) / y;
+}
+
+static inline int round_up_tile_i32(int x) {
+    return (x + TILE - 1) & ~(TILE - 1);
+}
+
+static inline int min_i32(int a, int b) {
+    return a < b ? a : b;
+}
+
+static inline uint64_t min_u64(uint64_t a, uint64_t b) {
+    return a < b ? a : b;
+}
+
+/* ===== Vector helpers for hart-1 pack ============================
+   Both assume dst (and src for copy) are 32-byte aligned; n is in floats.
+   The 8-element tail is handled scalar. f30/f31 are scratch — clobbered
+   per-call via the asm clobber list. */
+static inline void vec_zero_aligned(float * dst, int n) {
+    int       i  = 0;
+    const int n8 = n & ~7;
+    for (; i < n8; i += 8) {
+        __asm__ volatile(
+            "fsub.ps f31, f31, f31\n"
+            "fsw.ps  f31, %[d]\n"
+            : [d] "=m"(*(float (*)[8]) & dst[i])
+            :
+            : "f31");
+    }
+    for (; i < n; ++i) {
+        dst[i] = 0.0f;
+    }
+}
+
+static inline void vec_copy_aligned(float * dst, const float * src, int n) {
+    int       i  = 0;
+    const int n8 = n & ~7;
+    for (; i < n8; i += 8) {
+        __asm__ volatile(
+            "flw.ps f30, %[s]\n"
+            "fsw.ps f30, %[d]\n"
+            : [d] "=m"(*(float (*)[8]) & dst[i])
+            : [s] "m"(*(const float (*)[8]) & src[i])
+            : "f30");
+    }
+    for (; i < n; ++i) {
+        dst[i] = src[i];
+    }
+}
+
+/* ===== TenC save/restore =========================================
+   The TenC accumulator IS the f0..f31 vector register file: row N occupies
+   f(2N) and f(2N+1) (two 8-fp32 vector regs per row). We save by
+   tensor_store-ing TILE rows × 64 bytes, and restore via 32 flw.ps after
+   forcing L1D to refetch from the L2SCP backing (tensor_store bypasses L1D
+   so the backing is always current). See feedback_tenc_save_restore.md. */
+static inline void tenc_restore_from_scratch(uint64_t scr) {
+    FENCE;
+    evict_to_l2((const void *) scr, TILE, 64);
+    WAIT_CACHEOPS;
+    __asm__ volatile(
+        "flw.ps f0,    0(%0)\n"
+        "flw.ps f1,   32(%0)\n"
+        "flw.ps f2,   64(%0)\n"
+        "flw.ps f3,   96(%0)\n"
+        "flw.ps f4,  128(%0)\n"
+        "flw.ps f5,  160(%0)\n"
+        "flw.ps f6,  192(%0)\n"
+        "flw.ps f7,  224(%0)\n"
+        "flw.ps f8,  256(%0)\n"
+        "flw.ps f9,  288(%0)\n"
+        "flw.ps f10, 320(%0)\n"
+        "flw.ps f11, 352(%0)\n"
+        "flw.ps f12, 384(%0)\n"
+        "flw.ps f13, 416(%0)\n"
+        "flw.ps f14, 448(%0)\n"
+        "flw.ps f15, 480(%0)\n"
+        "flw.ps f16, 512(%0)\n"
+        "flw.ps f17, 544(%0)\n"
+        "flw.ps f18, 576(%0)\n"
+        "flw.ps f19, 608(%0)\n"
+        "flw.ps f20, 640(%0)\n"
+        "flw.ps f21, 672(%0)\n"
+        "flw.ps f22, 704(%0)\n"
+        "flw.ps f23, 736(%0)\n"
+        "flw.ps f24, 768(%0)\n"
+        "flw.ps f25, 800(%0)\n"
+        "flw.ps f26, 832(%0)\n"
+        "flw.ps f27, 864(%0)\n"
+        "flw.ps f28, 896(%0)\n"
+        "flw.ps f29, 928(%0)\n"
+        "flw.ps f30, 960(%0)\n"
+        "flw.ps f31, 992(%0)\n"
+        :
+        : "r"(scr)
+        : "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16",
+          "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+          "memory");
+}
+
+/* ===== Pin pack context ==========================================
+   Loop-invariant state hart-1 needs to pack one Cin chunk's worth of
+   pin (Kw shifted, padded copies of input rows) into local L2 SCP. The
+   filter is not touched in this struct; it is packed into the per-shire
+   local slice before the per-chunk loop begins. */
+typedef struct {
+    const float * in_base;  /* DRAM input base [Cin][H][W]         */
+    int           Kw;
+    int           chunk_KT; /* number of K_TILES (=16-wide) per chunk */
+    int           H, W, Hp, Wp_a;
+    int           pad_h, pad_w, s0;
+    int           minion;          /* this hart's minion id (0..31) */
+    uint64_t      pin_copy_floats; /* per-_s pin plane size in floats */
+    uint64_t      l2_pad_in_buf[MAX_DBL_BUFS];
+    uint64_t      pin_chunk_bytes; /* one chunk pin buffer's total size */
+} pin_ctx_t;
+
+static inline int find_mt_idx(const int * my_mt, int n_my_mt, int mt) {
+    for (int j = 0; j < n_my_mt; ++j) {
+        if (my_mt[j] == mt) {
+            return j;
+        }
+    }
+    return 0;
+}
+
+static inline conv_tile_t decode_tile(int t, int M_TILES, int w_tiles, const int * my_mt, int n_my_mt) {
+    conv_tile_t tile;
+    tile.mt = t % M_TILES;
+    t /= M_TILES;
+    const int wt = t % w_tiles;
+    t /= w_tiles;
+    tile.oh      = t;
+    tile.ow_base = wt * TILE;
+    tile.mt_idx  = find_mt_idx(my_mt, n_my_mt, tile.mt);
+    return tile;
+}
+
+static inline uint64_t
+filter_slab_addr(uint64_t l2_filter, int Kw, int K_TILES, int n_my_mt, int mt_idx, int kh, int kw, int kt_global) {
+    return l2_filter + (uint64_t) ((((kh * Kw + kw) * n_my_mt + mt_idx) * K_TILES + kt_global)) * SLAB_BYTES;
+}
+
+static inline uint64_t pin_tile_addr(uint64_t l2_pad_in,
+                                     uint64_t pin_copy_bytes,
+                                     int      ktc,
+                                     int      kw,
+                                     int      Hp,
+                                     int      Wp_a,
+                                     int      oh,
+                                     int      ow_base,
+                                     int      s1,
+                                     int      kh) {
+    const int ir_pad = oh * s1 + kh;
+    return l2_pad_in + (uint64_t) kw * pin_copy_bytes +
+           (((uint64_t) (ktc * TILE) * Hp + ir_pad) * Wp_a + ow_base) * sizeof(float);
+}
+
+static inline char * output_tile_addr(char *              out_base,
+                                      const conv_tile_t * tile,
+                                      uint64_t            out_chan_stride,
+                                      uint64_t            out_row_stride) {
+    return out_base + (size_t) (tile->mt * TILE) * out_chan_stride + (size_t) tile->oh * out_row_stride +
+           (size_t) tile->ow_base * sizeof(float);
+}
+
+static inline void flush_range_to_l2(const void * addr, uint64_t n_bytes) {
+    const uint64_t total_lines = (n_bytes + 63) / 64;
+    const char *   fl_addr     = (const char *) addr;
+    for (uint64_t done = 0; done < total_lines;) {
+        const uint64_t batch = min_u64(total_lines - done, 16);
+        flush_to_l2((const void *) (fl_addr + done * 64), batch, 64);
+        done += batch;
+    }
+}
+
+static inline void evict_range_past_l2(const void * addr, uint64_t n_bytes) {
+    const uint64_t total_lines = (n_bytes + 63) / 64;
+    const char *   fl_addr     = (const char *) addr;
+    for (uint64_t done = 0; done < total_lines;) {
+        const uint64_t batch = min_u64(total_lines - done, 16);
+        evict_past_l2((const void *) (fl_addr + done * 64), batch, 64);
+        done += batch;
+    }
+}
+
+/* One matrix-engine tile for one Cin chunk. This is the main optimization
+   surface: A is double-buffered, B is single-buffered due to L1 SCP space. */
+static inline void compute_tile_chunk(uint64_t            l2_filter,
+                                      uint64_t            l2_pad_in,
+                                      uint64_t            pin_copy_bytes,
+                                      int                 Kh,
+                                      int                 Kw,
+                                      int                 K_TILES,
+                                      int                 chunk_KT,
+                                      int                 kt_base,
+                                      int                 n_my_mt,
+                                      int                 Hp,
+                                      int                 Wp_a,
+                                      int                 s1,
+                                      uint64_t            a_row_stride,
+                                      uint64_t            b_row_stride,
+                                      const conv_tile_t * tile,
+                                      bool                first_fma_clears_tenc) {
+    const int      n_iters   = Kh * Kw * chunk_KT;
+    const uint64_t A_BUFS[2] = { LSCP_A_0, LSCP_A_1 };
+
+    const uint64_t a_addr0 = filter_slab_addr(l2_filter, Kw, K_TILES, n_my_mt, tile->mt_idx, 0, 0, kt_base);
+    tensor_load(false, false, A_BUFS[0], 0, 0, a_addr0, 0, (uint64_t) (TILE - 1), a_row_stride, 0);
+
+    for (int iter = 0; iter < n_iters; ++iter) {
+        const int ktc = iter % chunk_KT;
+        const int rem = iter / chunk_KT;
+        const int kw  = rem % Kw;
+        const int kh  = rem / Kw;
+
+        const uint64_t b_addr =
+            pin_tile_addr(l2_pad_in, pin_copy_bytes, ktc, kw, Hp, Wp_a, tile->oh, tile->ow_base, s1, kh);
+        tensor_load(false, false, LSCP_B, 0, 0, b_addr, 0, (uint64_t) (TILE - 1), b_row_stride, 1);
+
+        tensor_wait(TENSOR_LOAD_WAIT_0);
+        tensor_wait(TENSOR_LOAD_WAIT_1);
+
+        if (iter + 1 < n_iters) {
+            const int      ktc_n = (iter + 1) % chunk_KT;
+            const int      rem_n = (iter + 1) / chunk_KT;
+            const int      kw_n  = rem_n % Kw;
+            const int      kh_n  = rem_n / Kw;
+            const uint64_t a_addr_n =
+                filter_slab_addr(l2_filter, Kw, K_TILES, n_my_mt, tile->mt_idx, kh_n, kw_n, kt_base + ktc_n);
+            tensor_load(false, false, A_BUFS[(iter + 1) & 1], 0, 0, a_addr_n, 0, (uint64_t) (TILE - 1), a_row_stride,
+                        0);
+        }
+
+        tensor_fma(false, 3, (uint64_t) (TILE - 1), (uint64_t) (TILE - 1), 0, false, false, false, false, LSCP_B,
+                   A_BUFS[iter & 1], 0, first_fma_clears_tenc && (iter == 0));
+        tensor_wait(TENSOR_FMA_WAIT);
+    }
+}
+
+/* Pack only the slabs this shire's tiles actually consume, into local
+   L2 SCP. Slab layout in the filter buffer is [Kh][Kw][n_my_mt][K_TILES]
+   of TILE×TILE slabs (Cin-innermost form). Distributed across the 32
+   hart-1's of this shire by `slab % 32 == minion`.
+
+   This deliberately favors local inner-loop reads over global filter fanout.
+   Depending on tile shape, two shires may pack the same mt value; keep that
+   tradeoff visible when experimenting with shared-filter layouts. */
+static void pack_filter_local_mt(const float * flt_base,
+                                 int           Kh,
+                                 int           Kw,
+                                 int           Cin,
+                                 int           K_TILES,
+                                 const int *   my_mt,
+                                 int           n_my_mt,
+                                 int           minion,
+                                 uint64_t      l2_filter_base) {
+    const int    n_slabs = Kh * Kw * n_my_mt * K_TILES;
+    const size_t kstep   = (size_t) Kh * Kw; /* Cin stride in floats */
+
+    for (int slab = minion; slab < n_slabs; slab += N_MIN_PER_SHIRE) {
+        int       t  = slab;
+        const int kt = t % K_TILES;
+        t /= K_TILES;
+        const int mt_idx = t % n_my_mt;
+        t /= n_my_mt;
+        const int kw = t % Kw;
+        t /= Kw;
+        const int kh = t;
+        const int mt = my_mt[mt_idx];
+
+        const uint64_t slab_offset = (uint64_t) slab * SLAB_BYTES;
+        float *        cell        = (float *) (l2_filter_base + slab_offset);
+
+        for (int oc_in = 0; oc_in < TILE; ++oc_in) {
+            const int     oc  = mt * TILE + oc_in;
+            const float * src = flt_base + (((size_t) oc * Cin + (size_t) kt * TILE) * Kh + kh) * Kw + kw;
+            float *       row = cell + (size_t) oc_in * TILE;
+            float         scratch[TILE] __attribute__((aligned(32)));
+            for (int ic_in = 0; ic_in < TILE; ++ic_in) {
+                scratch[ic_in] = src[(size_t) ic_in * kstep];
+            }
+            vec_copy_aligned(row, scratch, TILE);
+        }
+    }
+
+    /* Flush this hart's dirty L1D lines for the slabs it wrote. */
+    FENCE;
+    for (int slab = minion; slab < n_slabs; slab += N_MIN_PER_SHIRE) {
+        const uint64_t slab_offset = (uint64_t) slab * SLAB_BYTES;
+        flush_to_l2((const void *) (l2_filter_base + slab_offset), SLAB_LINES, 64);
+    }
+    WAIT_CACHEOPS;
+}
+
+/* Pack one Cin chunk of the input pin (Kw shifted padded copies) into the
+   buf_idx side of local L2SCP. Work distributed across the 32 hart-1's in
+   the shire by `plane % 32 == minion`. The final flush_to_l2 forces L1D
+   write-back so hart-0's tensor_load sees the freshly written bytes. */
+static void pack_pin_chunk(const pin_ctx_t * ctx, int chunk_id, int buf_idx) {
+    const int kt_base  = chunk_id * ctx->chunk_KT;
+    const int Kw       = ctx->Kw;
+    const int chunk_KT = ctx->chunk_KT;
+    const int H = ctx->H, W = ctx->W, Hp = ctx->Hp, Wp_a = ctx->Wp_a;
+    const int pad_h = ctx->pad_h, pad_w = ctx->pad_w, s0 = ctx->s0;
+    const int minion = ctx->minion;
+
+    /* Pin pack: Kw shifted, padded copies of input rows. Bounds [vlo, vhi)
+       hoisted outside the row loop so the inner loop is three regions
+       (zero-prefix | bulk-copy | zero-suffix) with no per-element predicate. */
+    float *   pin0         = (float *) ctx->l2_pad_in_buf[buf_idx];
+    const int chunk_Cin    = chunk_KT * TILE;
+    const int n_pin_planes = Kw * chunk_Cin;
+    for (int p = minion; p < n_pin_planes; p += N_MIN_PER_SHIRE) {
+        const int s     = p / chunk_Cin;
+        const int icc   = p % chunk_Cin;
+        const int ic    = kt_base * TILE + icc;
+        float *   pin_s = pin0 + (size_t) s * ctx->pin_copy_floats;
+
+        const int offset = s - pad_w;
+        int       vlo    = 0;
+        while (vlo < Wp_a && (s0 * vlo + offset) < 0) {
+            vlo++;
+        }
+        int vhi = Wp_a;
+        while (vhi > vlo && (s0 * (vhi - 1) + offset) >= W) {
+            vhi--;
+        }
+        const bool aligned = (s0 == 1) && ((vlo & 7) == 0) && (((vlo + offset) & 7) == 0);
+
+        for (int r = 0; r < Hp; ++r) {
+            float *   row    = pin_s + ((size_t) icc * Hp + r) * Wp_a;
+            const int real_h = r - pad_h;
+            if (real_h < 0 || real_h >= H) {
+                vec_zero_aligned(row, Wp_a);
+                continue;
+            }
+            const float * src_row = ctx->in_base + ((size_t) ic * H + real_h) * W;
+
+            for (int cc = 0; cc < vlo; ++cc) {
+                row[cc] = 0.0f;
+            }
+
+            if (aligned) {
+                vec_copy_aligned(row + vlo, src_row + vlo + offset, vhi - vlo);
+            } else if (s0 == 1) {
+                const float * csrc = src_row + vlo + offset;
+                const int     n    = vhi - vlo;
+                for (int cc = 0; cc < n; ++cc) {
+                    row[vlo + cc] = csrc[cc];
+                }
+            } else {
+                for (int cc = vlo; cc < vhi; ++cc) {
+                    row[cc] = src_row[s0 * cc + offset];
+                }
+            }
+
+            for (int cc = vhi; cc < Wp_a; ++cc) {
+                row[cc] = 0.0f;
+            }
+        }
+    }
+
+    /* Flush this buffer's L1D-dirty lines down to L2SCP backing. */
+    FENCE;
+    flush_range_to_l2((const void *) ctx->l2_pad_in_buf[buf_idx], ctx->pin_chunk_bytes);
+    WAIT_CACHEOPS;
+}
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    (void) env;
+
+    const int shire   = get_shire_id();
+    const int hart_id = get_hart_id();
+    const int minion  = (hart_id >> 1) & 0x1F;
+    const int hart1   = hart_id & 1;
+
+    const struct ggml_tensor * flt = &params->src0; /* [Kw,Kh,Cin,Cout] */
+    const struct ggml_tensor * in  = &params->src1; /* [W, H, Cin,N=1 ] */
+    struct ggml_tensor *       out = &params->dst;  /* [W, H, Cout,N=1] */
+
+    const int Kw   = (int) flt->ne[0];
+    const int Kh   = (int) flt->ne[1];
+    const int Cin  = (int) flt->ne[2];
+    const int Cout = (int) flt->ne[3];
+
+    const int W  = (int) in->ne[0];
+    const int H  = (int) in->ne[1];
+    const int OW = (int) out->ne[0];
+    const int OH = (int) out->ne[1];
+
+    /* op_params layout (set by ggml_conv_2d):
+         [0]=s0  [1]=s1  [2]=p0  [3]=p1  [4]=d0  [5]=d1   */
+    const int s0    = out->op_params[0];
+    const int s1    = out->op_params[1];
+    const int pad_w = out->op_params[2];
+    const int pad_h = out->op_params[3];
+
+    if (Cin <= 0 || Cout <= 0) {
+        return -1;
+    }
+    if (Cin % TILE != 0 || Cout % TILE != 0) {
+        return -1;
+    }
+    if (W <= 0 || H <= 0) {
+        return -1;
+    }
+    if (s0 <= 0 || s1 <= 0) {
+        return -1;
+    }
+    if (in->ne[2] != Cin || in->ne[3] != 1) {
+        return -1;
+    }
+    if (out->ne[2] != Cout || out->ne[3] != 1) {
+        return -1;
+    }
+    if (!flt->data || !in->data || !out->data) {
+        return -1;
+    }
+
+    const int K_TILES = Cin / TILE;
+    const int M_TILES = Cout / TILE;
+
+    const int  Hp         = H + 2 * pad_h;
+    const int  Wp_a       = round_up_tile_i32(OW);
+    const int  OW_pad     = Wp_a;
+    const bool need_stage = (OW % TILE != 0);
+
+    /* ===================== Tile assignment & active-shire selection =====
+       Computed up front because the per-shire mt set (and thus filter
+       region size) depends on n_active_shires. */
+    const int w_tiles         = ceil_div_i32(OW, TILE);
+    const int total_tiles     = OH * w_tiles * M_TILES;
+    const int n_active_shires = need_stage ? 1 : min_i32(total_tiles, N_SHIRES);
+
+    /* Inactive shires exit immediately. No global barrier — pack and
+       barriers are now per-shire, so unused shires don't need to vote. */
+    if (shire >= n_active_shires) {
+        return 0;
+    }
+
+    /* ===================== Determine this shire's mt set ================
+       Standard tile assignment: tile t is owned by
+         shire  = t % n_active_shires
+         minion = (t / n_active_shires) % N_MIN_PER_SHIRE
+         slot   = t / (n_active_shires * N_MIN_PER_SHIRE)
+       So the set of mt's this shire actually consumes is the set of
+       (t % M_TILES) for all t this shire owns. Enumerate all shire-owned
+       tiles, not just the first MAX_TILES_PER_HART slots; the one-chunk
+       path can process more tiles serially. */
+    int my_mt[MAX_MY_MT];
+    int n_my_mt = 0;
+    for (int t = shire; t < total_tiles; t += n_active_shires) {
+        const int mt    = t % M_TILES;
+        bool      found = false;
+        for (int j = 0; j < n_my_mt; ++j) {
+            if (my_mt[j] == mt) {
+                found = true;
+                break;
+            }
+        }
+        if (!found) {
+            if (n_my_mt >= MAX_MY_MT) {
+                return -1;
+            }
+            my_mt[n_my_mt++] = mt;
+        }
+    }
+    if (n_my_mt == 0) {
+        return 0; /* no tiles for this shire */
+    }
+
+    const uint64_t filter_local_bytes = (uint64_t) Kh * Kw * n_my_mt * K_TILES * SLAB_BYTES;
+    if (filter_local_bytes > LOCAL_FILTER_CAP) {
+        return -1;
+    }
+
+    /* ===================== L2 SCP local layout =========================
+       filter (this shire's mt slice) | pin_buf[0] | pin_buf[1]?
+                                      | output_stage? | scratch (streaming) */
+    const uint64_t l2_base   = (uint64_t) et_shire_l2scp_local(0);
+    const uint64_t l2_filter = l2_base;
+
+    /* Sizing for pin: budget = LOCAL_BUDGET - filter - output_stage.    */
+    const int64_t output_stage_bytes_full = need_stage ? (int64_t) Cout * OH * OW_pad * (int64_t) sizeof(float) : 0;
+    const int64_t budget_for_chunks = (int64_t) LOCAL_BUDGET - (int64_t) filter_local_bytes - output_stage_bytes_full;
+    if (budget_for_chunks <= 0) {
+        return -1;
+    }
+    const int64_t per_KT_pin_bytes = (int64_t) Kw * TILE * Hp * Wp_a * (int64_t) sizeof(float);
+
+    int chunk_KT;
+    int n_buffers;
+    if ((int64_t) K_TILES * per_KT_pin_bytes <= budget_for_chunks) {
+        chunk_KT  = K_TILES;
+        n_buffers = 1;
+    } else {
+        chunk_KT = K_TILES;
+        while (chunk_KT > 1 && 2 * (int64_t) chunk_KT * per_KT_pin_bytes > budget_for_chunks) {
+            chunk_KT--;
+        }
+        while (chunk_KT > 1 && K_TILES % chunk_KT != 0) {
+            chunk_KT--;
+        }
+        n_buffers = (chunk_KT < K_TILES) ? 2 : 1;
+        if (chunk_KT < 1) {
+            return -1;
+        }
+    }
+    const int n_chunks = K_TILES / chunk_KT;
+
+    /* Streaming keeps partial sums in MAX_TILES_PER_HART scratch slots per
+       hart. The one-chunk path does not need scratch and can stream a longer
+       tile list serially, but multi-chunk shapes must fit this fixed slot
+       count until scratch scheduling is made more general. */
+    const int shire_tile_capacity = shire + MAX_TILES_PER_HART * n_active_shires * N_MIN_PER_SHIRE;
+    if (n_chunks > 1 && shire_tile_capacity < total_tiles) {
+        return -1;
+    }
+
+    const uint64_t pin_copy_floats = (uint64_t) chunk_KT * TILE * Hp * Wp_a;
+    const uint64_t pin_copy_bytes  = pin_copy_floats * sizeof(float);
+    const uint64_t pin_chunk_bytes = (uint64_t) Kw * pin_copy_bytes;
+
+    const uint64_t l2_pin_base              = l2_filter + filter_local_bytes;
+    const uint64_t l2_pin_buf[MAX_DBL_BUFS] = {
+        l2_pin_base,
+        l2_pin_base + pin_chunk_bytes,
+    };
+
+    const uint64_t l2_output_stage = need_stage ? l2_pin_base + (uint64_t) n_buffers * pin_chunk_bytes : 0;
+
+    const uint64_t scratch_per_hart = (uint64_t) MAX_TILES_PER_HART * (uint64_t) TILE * TILE * sizeof(float);
+    const uint64_t l2_scratch_base  = need_stage ? l2_output_stage + (uint64_t) output_stage_bytes_full :
+                                                   l2_pin_base + (uint64_t) n_buffers * pin_chunk_bytes;
+
+    /* ===================== PHASE 1: Filter pack (per-shire mt slice) ====
+       Hart-1's pack only this shire's mt slabs into local L2 SCP. The
+       SHIRE barrier below ensures the filter is in L2 SCP backing before
+       hart-0's first tensor_load. */
+    if (hart1) {
+        pack_filter_local_mt((const float *) flt->data, Kh, Kw, Cin, K_TILES, my_mt, n_my_mt, minion, l2_filter);
+    }
+
+    /* ===================== Hart 1: pin packer (per chunk) ==============
+       Double-buffered prefetch: pack chunk 0 synchronously, then per chunk c
+       signal "buf c ready", pack chunk c+1 into the alternate buffer
+       (overlaps hart-0's compute on c), signal "buf c done". */
+    if (hart1) {
+        const pin_ctx_t ctx = {
+            .in_base         = (const float *) in->data,
+            .Kw              = Kw,
+            .chunk_KT        = chunk_KT,
+            .H               = H,
+            .W               = W,
+            .Hp              = Hp,
+            .Wp_a            = Wp_a,
+            .pad_h           = pad_h,
+            .pad_w           = pad_w,
+            .s0              = s0,
+            .minion          = minion,
+            .pin_copy_floats = pin_copy_floats,
+            .l2_pad_in_buf   = { l2_pin_buf[0], l2_pin_buf[1] },
+            .pin_chunk_bytes = pin_chunk_bytes,
+        };
+
+        pack_pin_chunk(&ctx, 0, 0); /* prologue */
+
+        for (int c = 0; c < n_chunks; ++c) {
+            et_barrier(ET_BARRIER_SHIRE); /* signal "buf c ready" */
+            if (n_buffers > 1 && c + 1 < n_chunks) {
+                pack_pin_chunk(&ctx, c + 1, (c + 1) & 1);
+            }
+            et_barrier(ET_BARRIER_SHIRE); /* wait "buf c done" */
+        }
+
+        if (need_stage) {
+            et_barrier(ET_BARRIER_SHIRE);
+        }
+        return 0;
+    }
+
+    /* ===================== Hart 0: matrix engine ======================
+       Two execution modes:
+         - n_chunks == 1: full Cin in one shot. Each hart processes a list
+           of tiles serially; TenC resets between tiles via first_pass=true.
+         - n_chunks  > 1: streaming. Each hart owns up to MAX_TILES_PER_HART
+           tiles. For each chunk c, restore TenC from scratch[k] (skip on
+           c==0), accumulate this chunk's FMAs, then either save TenC back
+           to scratch[k] (c < last) or tensor_store directly (c == last). */
+    setup_cache_scp();
+    CLEAR_TENSOR_ERROR;
+
+    char * const   out_base        = need_stage ? (char *) l2_output_stage : (char *) out->data;
+    const int      compute_OW      = need_stage ? OW_pad : OW;
+    const uint64_t out_chan_stride = (uint64_t) OH * (uint64_t) compute_OW * sizeof(float);
+    const uint64_t out_row_stride  = (uint64_t) compute_OW * sizeof(float);
+
+    const uint64_t a_row_stride = (uint64_t) TILE * sizeof(float); /* 64 */
+    const uint64_t b_row_stride = (uint64_t) Hp * (uint64_t) Wp_a * sizeof(float);
+
+    /* Tile assignment: shire-strided so small workloads spread across
+       shires before stacking minions in one shire. */
+    const int t_start  = shire + minion * n_active_shires;
+    const int t_stride = n_active_shires * N_MIN_PER_SHIRE;
+
+    if (n_chunks == 1) {
+        et_barrier(ET_BARRIER_SHIRE); /* wait for the (only) pin chunk */
+
+        const uint64_t l2_pad_in = l2_pin_buf[0];
+        for (int t = t_start; t < total_tiles; t += t_stride) {
+            const conv_tile_t tile = decode_tile(t, M_TILES, w_tiles, my_mt, n_my_mt);
+            compute_tile_chunk(l2_filter, l2_pad_in, pin_copy_bytes, Kh, Kw, K_TILES, chunk_KT, 0, n_my_mt, Hp, Wp_a,
+                               s1, a_row_stride, b_row_stride, &tile, /*first_fma_clears_tenc=*/true);
+
+            char * dst_addr = output_tile_addr(out_base, &tile, out_chan_stride, out_row_stride);
+            tensor_store(0, 0, 3, (uint64_t) (TILE - 1), (uint64_t) dst_addr, 0, out_chan_stride);
+            tensor_wait(TENSOR_STORE_WAIT);
+        }
+
+        et_barrier(ET_BARRIER_SHIRE); /* matches hart-1's second barrier */
+
+    } else {
+        /* Streaming path: each hart owns up to MAX_TILES_PER_HART tiles. */
+        int my_tiles[MAX_TILES_PER_HART];
+        int n_my_tiles = 0;
+        for (int slot = 0; slot < MAX_TILES_PER_HART; ++slot) {
+            const int t = t_start + slot * t_stride;
+            if (t < total_tiles) {
+                my_tiles[n_my_tiles++] = t;
+            }
+        }
+
+        conv_tile_t tiles[MAX_TILES_PER_HART];
+        for (int k = 0; k < n_my_tiles; ++k) {
+            tiles[k] = decode_tile(my_tiles[k], M_TILES, w_tiles, my_mt, n_my_mt);
+        }
+
+        const uint64_t my_scratch_base = l2_scratch_base + (uint64_t) minion * scratch_per_hart;
+
+        for (int c = 0; c < n_chunks; ++c) {
+            et_barrier(ET_BARRIER_SHIRE); /* pin chunk c packed */
+
+            const int      buf       = c & 1;
+            const uint64_t l2_pad_in = l2_pin_buf[buf];
+            const int      kt_base   = c * chunk_KT;
+
+            for (int k = 0; k < n_my_tiles; ++k) {
+                const conv_tile_t * tile = &tiles[k];
+                const uint64_t      scr  = my_scratch_base + (uint64_t) k * (TILE * TILE * sizeof(float));
+
+                const bool first_pass_chunk = (c == 0);
+                if (!first_pass_chunk) {
+                    tenc_restore_from_scratch(scr);
+                }
+
+                compute_tile_chunk(l2_filter, l2_pad_in, pin_copy_bytes, Kh, Kw, K_TILES, chunk_KT, kt_base, n_my_mt,
+                                   Hp, Wp_a, s1, a_row_stride, b_row_stride, tile, first_pass_chunk);
+
+                if (c == n_chunks - 1) {
+                    char * dst_addr = output_tile_addr(out_base, tile, out_chan_stride, out_row_stride);
+                    tensor_store(0, 0, 3, (uint64_t) (TILE - 1), (uint64_t) dst_addr, 0, out_chan_stride);
+                } else {
+                    tensor_store(0, 0, 3, (uint64_t) (TILE - 1), (uint64_t) scr, 0, 64);
+                }
+                tensor_wait(TENSOR_STORE_WAIT);
+            }
+
+            et_barrier(ET_BARRIER_SHIRE); /* hart-0 done with chunk c */
+        }
+    }
+
+    FENCE;
+
+    /* ----------------------- DRAM emit phase ---------------------------
+       Only relevant when we staged into L2SCP because OW % 16 != 0. */
+    if (need_stage) {
+        et_barrier(ET_BARRIER_SHIRE);
+
+        if (minion == 0) {
+            const float * stage = (const float *) l2_output_stage;
+            float *       dram  = (float *) out->data;
+            for (int oc = 0; oc < Cout; ++oc) {
+                for (int oh2 = 0; oh2 < OH; ++oh2) {
+                    const float * src = stage + ((size_t) oc * OH + oh2) * OW_pad;
+                    float *       dst = dram + ((size_t) oc * OH + oh2) * OW;
+                    for (int ow2 = 0; ow2 < OW; ++ow2) {
+                        dst[ow2] = src[ow2];
+                    }
+                }
+            }
+            FENCE;
+            const uint64_t total_bytes = (uint64_t) Cout * OH * OW * sizeof(float);
+            evict_range_past_l2((const void *) dram, total_bytes);
+            WAIT_CACHEOPS;
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/cpy_f32_f16.c b/ggml/src/ggml-et/et-kernels/src/cpy_f32_f16.c
new file mode 100644 (file)
index 0000000..8bde57d
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/cpy_f32_f16.c
@@ -0,0 +1,110 @@
+//******************************************************************************
+// CPY F32 -> F16 Kernel
+// Copies F32 source tensor to F16 destination tensor (contiguous output).
+// Source may have arbitrary strides; destination must be contiguous.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct ggml_et_cont_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+};
+
+int entry_point(struct ggml_et_cont_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env || !params) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F16) {
+        return -1;
+    }
+
+    const char * src_data = (const char *) src0->data;
+    uint16_t *   dst_data = (uint16_t *) dst->data;
+
+    if (!src_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne00 = src0->ne[0];
+    const int64_t ne01 = src0->ne[1];
+    const int64_t ne02 = src0->ne[2];
+    const int64_t ne03 = src0->ne[3];
+
+    const int64_t nb00 = src0->nb[0];
+    const int64_t nb01 = src0->nb[1];
+    const int64_t nb02 = src0->nb[2];
+    const int64_t nb03 = src0->nb[3];
+
+    const int64_t total_elements = ne00 * ne01 * ne02 * ne03;
+
+    if (total_elements == 0) {
+        return 0;
+    }
+
+    // Check if src is contiguous F32
+    const bool src_contiguous =
+        (nb00 == 4 && nb01 == ne00 * 4 && nb02 == ne00 * ne01 * 4 && nb03 == ne00 * ne01 * ne02 * 4);
+
+    // Distribute by cache lines (16 F16 elements = 32 bytes = half cache line)
+    // Use 32 elements per chunk to keep output cache-line aligned
+    const int64_t elems_per_cl = 32;
+    const int64_t total_cl     = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+    const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+    const int64_t cl_start      = thread_id * cl_per_thread;
+    int64_t       cl_end        = cl_start + cl_per_thread;
+    if (cl_end > total_cl) {
+        cl_end = total_cl;
+    }
+    if (cl_start >= total_cl) {
+        return 0;
+    }
+
+    const int64_t es = cl_start * elems_per_cl;
+    int64_t       ee = cl_end * elems_per_cl;
+    if (ee > total_elements) {
+        ee = total_elements;
+    }
+
+    if (src_contiguous) {
+        // Fast path: src is contiguous F32
+        const float * src_f32 = (const float *) src_data;
+        for (int64_t i = es; i < ee; ++i) {
+            dst_data[i] = fp32_to_fp16(src_f32[i]);
+        }
+    } else {
+        // General path: stride-aware read
+        for (int64_t idx = es; idx < ee; ++idx) {
+            const int64_t i00  = idx % ne00;
+            const int64_t rem1 = idx / ne00;
+            const int64_t i01  = rem1 % ne01;
+            const int64_t rem2 = rem1 / ne01;
+            const int64_t i02  = rem2 % ne02;
+            const int64_t i03  = rem2 / ne02;
+
+            const float val = *(const float *) (src_data + i00 * nb00 + i01 * nb01 + i02 * nb02 + i03 * nb03);
+            dst_data[idx]   = fp32_to_fp16(val);
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/crt.S b/ggml/src/ggml-et/et-kernels/src/crt.S
new file mode 100644 (file)
index 0000000..5f80272
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/crt.S
@@ -0,0 +1,15 @@
+.section .text.init, "ax", @progbits
+.global _start
+_start:
+    # initialize global pointer
+.option push
+.option norelax
+    la    gp, __global_pointer$
+.option pop
+    # Firmware sets stack pointer before launch
+    # bss not allowed, no init
+    call  entry_point
+    li    a2, 0  /* KERNEL_RETURN_SUCCESS (0) */
+    mv    a1, a0
+    li    a0, 8  /* SYSCALL_RETURN_FROM_KERNEL (8) */
+    ecall

diff --git a/ggml/src/ggml-et/et-kernels/src/cumsum_f32.c b/ggml/src/ggml-et/et-kernels/src/cumsum_f32.c
new file mode 100644 (file)
index 0000000..008f78b
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/cumsum_f32.c
@@ -0,0 +1,96 @@
+//******************************************************************************
+// CUMSUM F32 Kernel
+// Computes an inclusive prefix sum along dim 0 for each row in higher dims.
+// First-pass implementation: scalar and row-contiguous input/output only.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_cumsum_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+};
+
+int entry_point(struct ggml_et_cumsum_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne0 = src0->ne[0];
+    const int64_t ne1 = src0->ne[1];
+    const int64_t ne2 = src0->ne[2];
+    const int64_t ne3 = src0->ne[3];
+
+    const size_t snb0 = src0->nb[0];
+    const size_t snb1 = src0->nb[1];
+    const size_t snb2 = src0->nb[2];
+    const size_t snb3 = src0->nb[3];
+
+    const size_t dnb0 = dst->nb[0];
+    const size_t dnb1 = dst->nb[1];
+    const size_t dnb2 = dst->nb[2];
+    const size_t dnb3 = dst->nb[3];
+
+    if (snb0 != sizeof(float) || dnb0 != sizeof(float)) {
+        return -1;
+    }
+
+    const int64_t total_rows     = ne1 * ne2 * ne3;
+    const int64_t rows_per_group = et_rows_per_cacheline_group(ne0, sizeof(float));
+    const int64_t total_groups   = (total_rows + rows_per_group - 1) / rows_per_group;
+
+    for (int64_t grp = thread_id; grp < total_groups; grp += num_threads) {
+        const int64_t row_start = grp * rows_per_group;
+        int64_t       row_end   = row_start + rows_per_group;
+        if (row_end > total_rows) {
+            row_end = total_rows;
+        }
+
+        for (int64_t row = row_start; row < row_end; ++row) {
+            int64_t i1 = row % ne1;
+            int64_t i2 = (row / ne1) % ne2;
+            int64_t i3 = row / (ne1 * ne2);
+
+            const float * src_row = (const float *) ((const char *) src0_data + i1 * snb1 + i2 * snb2 + i3 * snb3);
+            float *       dst_row = (float *) ((char *) dst_data + i1 * dnb1 + i2 * dnb2 + i3 * dnb3);
+
+            float acc = 0.0f;
+            for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                acc += src_row[i0];
+                dst_row[i0] = acc;
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/diag_f32.c b/ggml/src/ggml-et/et-kernels/src/diag_f32.c
new file mode 100644 (file)
index 0000000..50fd3a8
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/diag_f32.c
@@ -0,0 +1,90 @@
+//******************************************************************************
+// Diag F32 Kernel
+// Creates a diagonal matrix from a 1D vector.
+// dst[i][j] = (i == j) ? src0[i] : 0.0f
+//
+// src0: [N, 1, ne2, ne3]   (1D vector per batch)
+// dst:  [N, N, ne2, ne3]   (diagonal matrix per batch)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_diag_params {
+    struct ggml_tensor src0;  // F32 input vector
+    struct ggml_tensor dst;   // F32 output diagonal matrix
+};
+
+int entry_point(struct ggml_et_diag_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne0 = dst->ne[0];  // N (row width = column count)
+    const int64_t ne1 = dst->ne[1];  // N (number of rows)
+    const int64_t ne2 = dst->ne[2];
+    const int64_t ne3 = dst->ne[3];
+
+    const size_t nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+    const size_t nb02 = src0->nb[2], nb03 = src0->nb[3];
+
+    // Total rows across all batches — parallelize over these
+    const int64_t total_rows = ne1 * ne2 * ne3;
+
+    // Prepare zero vector for SIMD zeroing
+    float zero = 0.0f;
+    __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+    for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+        int64_t i1 = row % ne1;
+        int64_t i2 = (row / ne1) % ne2;
+        int64_t i3 = row / (ne1 * ne2);
+
+        float * dst_row = (float *) ((char *) dst_data + i1 * nb1 + i2 * nb2 + i3 * nb3);
+
+        // Zero the entire row with SIMD
+        int64_t       i0      = 0;
+        const int64_t vec_end = (ne0 / 8) * 8;
+        for (; i0 < vec_end; i0 += 8) {
+            __asm__ volatile("fsw.ps f10, %[d]\n" : [d] "=m"(*(float (*)[8]) & dst_row[i0])::"f10");
+        }
+        for (; i0 < ne0; i0++) {
+            dst_row[i0] = 0.0f;
+        }
+
+        // Place the diagonal element: dst[i1][i1] = src0[i1]
+        const float * src_ptr = (const float *) ((const char *) src0_data + i2 * nb02 + i3 * nb03);
+        dst_row[i1]           = src_ptr[i1];
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/el_map_f32.c b/ggml/src/ggml-et/et-kernels/src/el_map_f32.c
new file mode 100644 (file)
index 0000000..c40472f
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/el_map_f32.c
@@ -0,0 +1,377 @@
+// Element-wise operations: dst[i] = src0[i] op src1[i]
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+// Generic m0-gated element-wise block operation.
+// The OP parameter selects the instruction: "fmul.ps", "fadd.ps", "fsub.ps".
+#define DEFINE_BLOCK_OP(name, op_insn)                                                                             \
+    static inline void name(float * dst_block, const float * src0_block, const float * src1_block, int elements) { \
+        const int32_t vec_end = (elements / 8) * 8;                                                                \
+        const int32_t tail    = elements - vec_end;                                                                \
+                                                                                                                   \
+        unsigned long temp_mask;                                                                                   \
+        __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));                                                         \
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");                                                                  \
+                                                                                                                   \
+        for (int32_t i = 0; i < vec_end; i += 8) {                                                                 \
+            __asm__ volatile(                                                                                      \
+                "flw.ps f10, %[s0]\n"                                                                              \
+                "flw.ps f11, %[s1]\n" op_insn                                                                      \
+                " f12, f10, f11\n"                                                                                 \
+                "fsw.ps f12, %[d]\n"                                                                               \
+                : [d] "=m"(*(float (*)[8]) & dst_block[i])                                                         \
+                : [s0] "m"(*(const float (*)[8]) & src0_block[i]), [s1] "m"(*(const float (*)[8]) & src1_block[i]) \
+                : "f10", "f11", "f12");                                                                            \
+        }                                                                                                          \
+        /* Deal with tail chunks */                                                                                \
+        if (tail > 0) {                                                                                            \
+            const unsigned long tail_m0 = (1ul << tail) - 1;                                                       \
+            __asm__ volatile(                                                                                      \
+                "mov.m.x m0, %[tm], 0\n"                                                                           \
+                "flw.ps f10, 0(%[s0])\n"                                                                           \
+                "flw.ps f11, 0(%[s1])\n" op_insn                                                                   \
+                " f12, f10, f11\n"                                                                                 \
+                "fsw.ps f12, 0(%[d])\n"                                                                            \
+                :                                                                                                  \
+                : [s0] "r"(&src0_block[vec_end]), [s1] "r"(&src1_block[vec_end]), [d] "r"(&dst_block[vec_end]),    \
+                  [tm] "r"(tail_m0)                                                                                \
+                : "f10", "f11", "f12", "memory");                                                                  \
+        }                                                                                                          \
+                                                                                                                   \
+        __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));                                                          \
+    }
+
+DEFINE_BLOCK_OP(block_mul_cache_aligned, "fmul.ps")
+DEFINE_BLOCK_OP(block_add_cache_aligned, "fadd.ps")
+DEFINE_BLOCK_OP(block_sub_cache_aligned, "fsub.ps")
+
+// Broadcast variants: src1 is a single scalar, broadcast to all 8 lanes.
+#define DEFINE_BLOCK_OP_BROADCAST(name, op_insn)                                                                     \
+    static inline void name(float * dst_block, const float * src0_block, float scalar, int elements) {               \
+        const int32_t vec_end = (elements / 8) * 8;                                                                  \
+        const int32_t tail    = elements - vec_end;                                                                  \
+                                                                                                                     \
+        unsigned long temp_mask;                                                                                     \
+        __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));                                                           \
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");                                                                    \
+                                                                                                                     \
+        for (int32_t i = 0; i < vec_end; i += 8) {                                                                   \
+            __asm__ volatile(                                                                                        \
+                "flw.ps f10, %[s0]\n"                                                                                \
+                "fbc.ps f11, %[s]\n" op_insn                                                                         \
+                " f12, f10, f11\n"                                                                                   \
+                "fsw.ps f12, %[d]\n"                                                                                 \
+                : [d] "=m"(*(float (*)[8]) & dst_block[i])                                                           \
+                : [s0] "m"(*(const float (*)[8]) & src0_block[i]), [s] "m"(scalar)                                   \
+                : "f10", "f11", "f12");                                                                              \
+        }                                                                                                            \
+                                                                                                                     \
+        if (tail > 0) {                                                                                              \
+            const unsigned long tail_m0 = (1ul << tail) - 1;                                                         \
+            __asm__ volatile(                                                                                        \
+                "mov.m.x m0, %[tm], 0\n"                                                                             \
+                "flw.ps f10, 0(%[s0])\n"                                                                             \
+                "fbc.ps f11, 0(%[ps])\n" op_insn                                                                     \
+                " f12, f10, f11\n"                                                                                   \
+                "fsw.ps f12, 0(%[d])\n"                                                                              \
+                :                                                                                                    \
+                : [s0] "r"(&src0_block[vec_end]), [ps] "r"(&scalar), [d] "r"(&dst_block[vec_end]), [tm] "r"(tail_m0) \
+                : "f10", "f11", "f12", "memory");                                                                    \
+        }                                                                                                            \
+                                                                                                                     \
+        __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));                                                            \
+    }
+
+DEFINE_BLOCK_OP_BROADCAST(block_mul_broadcast, "fmul.ps")
+DEFINE_BLOCK_OP_BROADCAST(block_add_broadcast, "fadd.ps")
+DEFINE_BLOCK_OP_BROADCAST(block_sub_broadcast, "fsub.ps")
+
+static inline float scalar_el_map(float src0, float src1, enum ggml_op operation) {
+    switch (operation) {
+        case GGML_OP_MUL:
+            return src0 * src1;
+        case GGML_OP_ADD:
+            return src0 + src1;
+        case GGML_OP_SUB:
+            return src0 - src1;
+        default:
+            return 0.0f;
+    }
+}
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * src1_data = (float *) src1->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+#ifdef ET_UBERKERNEL
+    // Consumer-side input eviction. Required because ET caches are
+    // incoherent across minions: if a previous kernel in this UK batch
+    // left stale lines for these addresses in this hart's L1, drop them
+    // so we read fresh from L3/DRAM (where the producer flushed its
+    // results). Standalone launches don't need this -- the host-side
+    // runtime boundary between kernel launches handles it.
+    const size_t src0_bytes = (size_t) src0->ne[0] * src0->ne[1] * src0->ne[2] * src0->ne[3] * src0->nb[0];
+    const size_t src1_bytes = (size_t) src1->ne[0] * src1->ne[1] * src1->ne[2] * src1->ne[3] * src1->nb[0];
+    evict_region_past_l2(src0_data, src0_bytes);
+    evict_region_past_l2(src1_data, src1_bytes);
+    WAIT_CACHEOPS;
+    FENCE;
+    et_barrier(ET_BARRIER_GLOBAL);
+#endif
+
+    enum ggml_op operation = dst->op;
+
+    if (operation != GGML_OP_MUL && operation != GGML_OP_ADD && operation != GGML_OP_SUB) {
+        return -1;  // Unsupported operation
+    }
+
+    const int64_t ne0 = dst->ne[0], ne1 = dst->ne[1], ne2 = dst->ne[2], ne3 = dst->ne[3];
+    const int64_t ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3];
+    const int64_t ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3];
+
+    const size_t nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+    const size_t nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    const size_t nb10 = src1->nb[0], nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3];
+
+    const bool cache_aligned = (dst->ne[0] % 16 == 0);
+
+    // Fast path: no broadcasting, contiguous
+    const bool no_broadcast = (ne10 == ne0 && ne11 == ne1 && ne12 == ne2 && ne13 == ne3);
+    const bool all_contiguous =
+        (nb0 == 4 && nb00 == 4 && nb10 == 4 && nb1 == ne0 * 4 && nb01 == ne0 * 4 && nb11 == ne0 * 4);
+
+    if (no_broadcast && all_contiguous) {
+        const int64_t total_elements         = ne0 * ne1 * ne2 * ne3;
+        const int64_t elements_per_cacheline = 16;  // 64 bytes / 4 bytes
+        const int64_t total_cachelines       = (total_elements + elements_per_cacheline - 1) / elements_per_cacheline;
+
+        const int64_t cl_per_thread = (total_cachelines + num_threads - 1) / num_threads;
+        const int64_t cl_start      = thread_id * cl_per_thread;
+        int64_t       cl_end        = cl_start + cl_per_thread;
+        if (cl_end > total_cachelines) {
+            cl_end = total_cachelines;
+        }
+
+        if (cl_start >= total_cachelines) {
+            return 0;
+        }
+
+        const int64_t elem_start = cl_start * elements_per_cacheline;
+        int64_t       elem_end   = cl_end * elements_per_cacheline;
+        if (elem_end > total_elements) {
+            elem_end = total_elements;
+        }
+        const int32_t count = (int32_t) (elem_end - elem_start);
+
+        switch (operation) {
+            case GGML_OP_MUL:
+                block_mul_cache_aligned(dst_data + elem_start, src0_data + elem_start, src1_data + elem_start, count);
+                break;
+            case GGML_OP_ADD:
+                block_add_cache_aligned(dst_data + elem_start, src0_data + elem_start, src1_data + elem_start, count);
+                break;
+            case GGML_OP_SUB:
+                block_sub_cache_aligned(dst_data + elem_start, src0_data + elem_start, src1_data + elem_start, count);
+                break;
+            default:
+                return 1;
+        }
+#ifdef ET_UBERKERNEL
+        // Producer-side flush: ET caches are incoherent across minions, so
+        // a consumer kernel running on a different minion can't see our
+        // dirty L1 lines via its own evict_region_past_l2. Push our writes
+        // all the way to DRAM so the next batched kernel reads fresh.
+        // Standalone launches don't need this -- the host runtime boundary
+        // between kernel launches handles cache writeback.
+        FENCE;
+        evict_region_past_l2(dst_data + elem_start, (size_t) count * sizeof(float));
+        WAIT_CACHEOPS;
+        FENCE;
+#endif
+        return 0;
+    }
+
+    // Slow path: broadcasting or non-contiguous
+    const int64_t total_rows = ne1 * ne2 * ne3;
+
+    int64_t start_row;
+    int64_t end_row;
+
+    if (cache_aligned) {
+        const int64_t rows_per_thread = (total_rows + num_threads - 1) / num_threads;
+        start_row                     = thread_id * rows_per_thread;
+        end_row = (start_row + rows_per_thread < total_rows) ? (start_row + rows_per_thread) : total_rows;
+    } else {
+        const int64_t rows_per_group = et_rows_per_cacheline_group(ne0, sizeof(float));
+        const int64_t total_groups   = (total_rows + rows_per_group - 1) / rows_per_group;
+
+        if (thread_id >= total_groups) {
+            return 0;
+        }
+
+        const int64_t group_start = thread_id;
+        for (int64_t grp = group_start; grp < total_groups; grp += num_threads) {
+            const int64_t group_row_start = grp * rows_per_group;
+            int64_t       group_row_end   = group_row_start + rows_per_group;
+            if (group_row_end > total_rows) {
+                group_row_end = total_rows;
+            }
+
+#ifdef ET_UBERKERNEL
+            // First row written by this group (used for producer-side evict).
+            const int64_t first_i03      = group_row_start / (ne2 * ne1);
+            const int64_t first_i02      = (group_row_start - first_i03 * ne2 * ne1) / ne1;
+            const int64_t first_i01      = (group_row_start - first_i03 * ne2 * ne1 - first_i02 * ne1);
+            char *        group_dst_base = (char *) dst_data + first_i03 * nb3 + first_i02 * nb2 + first_i01 * nb1;
+#endif
+
+            for (int64_t ir = group_row_start; ir < group_row_end; ir++) {
+                const int64_t i03 = ir / (ne2 * ne1);
+                const int64_t i02 = (ir - i03 * ne2 * ne1) / ne1;
+                const int64_t i01 = (ir - i03 * ne2 * ne1 - i02 * ne1);
+
+                const int64_t i13 = i03 % ne13;
+                const int64_t i12 = i02 % ne12;
+                const int64_t i11 = i01 % ne11;
+
+                float *       dst_ptr = (float *) ((char *) dst_data + i03 * nb3 + i02 * nb2 + i01 * nb1);
+                const float * src0_ptr =
+                    (const float *) ((const char *) src0_data + i03 * nb03 + i02 * nb02 + i01 * nb01);
+                const float * src1_ptr =
+                    (const float *) ((const char *) src1_data + i13 * nb13 + i12 * nb12 + i11 * nb11);
+
+                if (ne10 == 1) {
+                    const float scalar = src1_ptr[0];
+                    for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                        dst_ptr[i0] = scalar_el_map(src0_ptr[i0], scalar, operation);
+                    }
+                } else {
+                    for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                        dst_ptr[i0] = scalar_el_map(src0_ptr[i0], src1_ptr[i0 % ne10], operation);
+                    }
+                }
+            }
+
+#ifdef ET_UBERKERNEL
+            // Producer-side flush for this group's rows. Group rows are
+            // contiguous because nb1 = ne0*4 in the cacheline-group layout.
+            // Only needed inside a UK batch; see comment in fast path.
+            const int64_t nrows = group_row_end - group_row_start;
+            if (nrows > 0) {
+                FENCE;
+                evict_region_past_l2(group_dst_base, (size_t) nrows * nb1);
+                WAIT_CACHEOPS;
+                FENCE;
+            }
+#endif
+        }
+
+        return 0;
+    }
+
+    if (start_row >= total_rows) {
+        return 0;
+    }
+
+    for (int64_t ir = start_row; ir < end_row; ir++) {
+        // Convert flat row index to 3D coordinates
+        const int64_t i03 = ir / (ne2 * ne1);
+        const int64_t i02 = (ir - i03 * ne2 * ne1) / ne1;
+        const int64_t i01 = (ir - i03 * ne2 * ne1 - i02 * ne1);
+
+        // Handle broadcasting: src1 coordinates with modulo
+        const int64_t i13 = i03 % ne13;
+        const int64_t i12 = i02 % ne12;
+        const int64_t i11 = i01 % ne11;
+
+        // Calculate base pointers for this row using stride-based addressing
+        float *       dst_ptr  = (float *) ((char *) dst_data + i03 * nb3 + i02 * nb2 + i01 * nb1);
+        const float * src0_ptr = (const float *) ((const char *) src0_data + i03 * nb03 + i02 * nb02 + i01 * nb01);
+        const float * src1_ptr = (const float *) ((const char *) src1_data + i13 * nb13 + i12 * nb12 + i11 * nb11);
+
+        if (ne10 == 1) {
+            // Broadcast scalar: src1 has ne[0]=1, broadcast across entire row
+            float scalar = src1_ptr[0];
+            switch (operation) {
+                case GGML_OP_MUL:
+                    block_mul_broadcast(dst_ptr, src0_ptr, scalar, (int) ne0);
+                    break;
+                case GGML_OP_ADD:
+                    block_add_broadcast(dst_ptr, src0_ptr, scalar, (int) ne0);
+                    break;
+                case GGML_OP_SUB:
+                    block_sub_broadcast(dst_ptr, src0_ptr, scalar, (int) ne0);
+                    break;
+                default:
+                    return 1;
+            }
+        } else {
+            // Broadcasting in dimension 0: src1 repeats across src0
+            const int64_t nr0 = ne0 / ne10;
+
+            for (int64_t r = 0; r < nr0; r++) {
+                const float * src0_block = src0_ptr + r * ne10;
+                float *       dst_block  = dst_ptr + r * ne10;
+
+                switch (operation) {
+                    case GGML_OP_MUL:
+                        block_mul_cache_aligned(dst_block, src0_block, src1_ptr, (int) ne10);
+                        break;
+                    case GGML_OP_ADD:
+                        block_add_cache_aligned(dst_block, src0_block, src1_ptr, (int) ne10);
+                        break;
+                    case GGML_OP_SUB:
+                        block_sub_cache_aligned(dst_block, src0_block, src1_ptr, (int) ne10);
+                        break;
+                    default:
+                        return 1;
+                }
+            }
+        }
+    }
+
+#ifdef ET_UBERKERNEL
+    // Producer-side flush for the cache-aligned slow path. Rows
+    // [start_row, end_row) are contiguous in dst because nb1 = ne0 * 4.
+    // Only needed inside a UK batch; see comment in fast path.
+    if (end_row > start_row) {
+        FENCE;
+        evict_region_past_l2((char *) dst_data + start_row * nb1, (size_t) (end_row - start_row) * nb1);
+        WAIT_CACHEOPS;
+        FENCE;
+    }
+#endif
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/fill_f32.c b/ggml/src/ggml-et/et-kernels/src/fill_f32.c
new file mode 100644 (file)
index 0000000..1847c8d
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/fill_f32.c
@@ -0,0 +1,87 @@
+//******************************************************************************
+// Fill F32 Kernel
+// Fills entire tensor with a constant scalar value.
+// dst[i] = c  for all elements
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_fill_params {
+    struct ggml_tensor dst;  // F32 output tensor (contiguous)
+    float              c;    // Constant value to fill
+};
+
+int entry_point(struct ggml_et_fill_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * dst = &params->dst;
+
+    if (dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * dst_data = (float *) dst->data;
+    if (!dst_data) {
+        return -1;
+    }
+
+    const int64_t total_elements = dst->ne[0] * dst->ne[1] * dst->ne[2] * dst->ne[3];
+
+    if (total_elements == 0) {
+        return 0;
+    }
+
+    // Distribute by cache lines (16 floats = 64 bytes)
+    const int64_t elems_per_cl  = 16;
+    const int64_t total_cl      = (total_elements + elems_per_cl - 1) / elems_per_cl;
+    const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+    const int64_t cl_start      = thread_id * cl_per_thread;
+    int64_t       cl_end        = cl_start + cl_per_thread;
+    if (cl_end > total_cl) {
+        cl_end = total_cl;
+    }
+    if (cl_start >= total_cl) {
+        return 0;
+    }
+
+    const int64_t es = cl_start * elems_per_cl;
+    int64_t       ee = cl_end * elems_per_cl;
+    if (ee > total_elements) {
+        ee = total_elements;
+    }
+
+    // Broadcast constant to all SIMD lanes
+    float c = params->c;
+    __asm__ volatile("fbc.ps f10, %[v]\n" : : [v] "m"(c) : "f10");
+
+    // Vector fill (8-wide)
+    int64_t       i       = es;
+    const int64_t vec_end = es + ((ee - es) / 8) * 8;
+    for (; i < vec_end; i += 8) {
+        __asm__ volatile("fsw.ps f10, %[d]\n" : [d] "=m"(*(float (*)[8]) & dst_data[i])::"f10");
+    }
+    // Scalar tail
+    for (; i < ee; i++) {
+        dst_data[i] = c;
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/flash_attn_ext_f16_me.c b/ggml/src/ggml-et/et-kernels/src/flash_attn_ext_f16_me.c
new file mode 100644 (file)
index 0000000..c905b36
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/flash_attn_ext_f16_me.c
@@ -0,0 +1,1000 @@
+//******************************************************************************
+// Flash Attention with TensorFMA16A32 for QK^T
+//
+// Uses the matrix engine for the QK^T dot products (F16×F16→F32),
+// scalar code for online softmax and V accumulation.
+//
+// Hart 0: tensor engine (Q load, K load from SCP, FMA, softmax, V accum)
+// Hart 1: pack K into double-buffered L2 SCP panels, flush for tensor_load
+//
+// Requirements:
+//   - Q: F32 (converted to F16 internally)
+//   - K, V: F16
+//   - dk must be a multiple of 32 (TensorFMA16A32 K-tile)
+//   - dv ≤ 512 (accumulator in shire-local L2 SCP)
+//
+// Parallelization: each minion independently processes one (qpos, head, batch)
+// row, round-robin across all minion hart-0s. Hart 1 assists with K packing.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "tensor.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+#include <string.h>
+
+#define NUM_COMPUTE_SHIRES 32
+#define MINIONS_PER_SHIRE  32
+
+// QK^T tiles: 16 KV positions at a time, K in chunks of 32 F16
+#define TILE_KV 16
+#define TILE_K  32
+
+// L1 scratchpad layout: A (Q) in lines 0-15, B (K interleaved) in lines 16-31
+#define A_L1_START 0
+#define B_L1_START 16
+
+// Max head dimensions
+#define FA_DV_MAX 512  // max value head dim (dv)
+#define FA_DK_MAX 512  // max key head dim (dk) - some models use hsk > hsv
+
+typedef uint16_t et_fp16_t;
+
+#define ET_NEG_INF_F (-3.402823466e+38f)
+
+// L2 SCP layout per minion:
+//   [0..2047]       accumulator (FA_DV_MAX * sizeof(float))
+//   [2048..4095]    kpanel buffer 0 (32 × 32 × 2 = 2048 bytes)
+//   [4096..6143]    kpanel buffer 1 (2048 bytes)
+//   [6144..6207]    stats line - (M_p at +0, S_p at +4), own cache line
+// Double-buffering ensures hart 0 finishes buf[N%2] before hart 1
+// overwrites it at chunk N+2.
+//
+// The stats line reserves a cache-line-aligned slot for split-KV softmax
+// partials (M_p, S_p). With k_splits=1 the slot is currently unused; step 2
+// will populate it and use peer minions' slots during the reduction.
+#define SCP_ACC_OFF     0
+#define SCP_ACC_STRIDE  (FA_DV_MAX * sizeof(float))       // 2048
+#define SCP_KPANEL_SIZE (32 * 32 * sizeof(et_fp16_t))     // 2048
+#define SCP_KP0_OFF     SCP_ACC_STRIDE                    // 2048
+#define SCP_KP1_OFF     (SCP_KP0_OFF + SCP_KPANEL_SIZE)   // 4096
+#define SCP_STATS_OFF   (SCP_KP1_OFF + SCP_KPANEL_SIZE)   // 6144
+#define SCP_STATS_SIZE  64                                // own cache line
+#define SCP_PER_MINION  (SCP_STATS_OFF + SCP_STATS_SIZE)  // 6208
+
+struct ggml_et_flash_attn_ext_params {
+    struct ggml_tensor src0;  // Q (F32)
+    struct ggml_tensor src1;  // K (F16)
+    struct ggml_tensor src2;  // V (F16)
+    struct ggml_tensor mask;  // mask (F16 or F32), zeroed when absent
+    struct ggml_tensor dst;   // Output (F32)
+    float              scale;
+    int32_t            has_mask;
+};
+
+static inline float get_mask_val(const struct ggml_tensor * mask, int64_t iq1, int64_t ik1, int64_t iq2, int64_t iq3) {
+    const char * base = (const char *) mask->data + iq1 * mask->nb[1] + (iq2 % mask->ne[2]) * mask->nb[2] +
+                        (iq3 % mask->ne[3]) * mask->nb[3];
+
+    if (mask->type == GGML_TYPE_F32) {
+        return *(const float *) (base + ik1 * mask->nb[0]);
+    }
+    return fp16_to_fp32(*(const uint16_t *) (base + ik1 * mask->nb[0]));
+}
+
+static inline const char * get_mask_row_base(const struct ggml_tensor * mask, int64_t iq1, int64_t iq2, int64_t iq3) {
+    return (const char *) mask->data + iq1 * mask->nb[1] + (iq2 % mask->ne[2]) * mask->nb[2] +
+           (iq3 % mask->ne[3]) * mask->nb[3];
+}
+
+static inline float get_mask_val_from_base(const struct ggml_tensor * mask, const char * base, int64_t ik1) {
+    if (mask->type == GGML_TYPE_F32) {
+        return *(const float *) (base + ik1 * mask->nb[0]);
+    }
+    return fp16_to_fp32(*(const uint16_t *) (base + ik1 * mask->nb[0]));
+}
+
+// Pack K rows for TensorLoadTranspose16 (even/odd deinterleave)
+static inline void __attribute__((always_inline)) pack_k_for_transpose16(et_fp16_t *  out,
+                                                                         const char * k_base,
+                                                                         int64_t      kv_start,
+                                                                         int64_t      dk_start,
+                                                                         int64_t      kv_count,
+                                                                         int64_t      nb1_k) {
+    unsigned long old_mask;
+    __asm__ volatile(
+        "mova.x.m  %[ms]            \n\t"
+        "mov.m.x   m0, x0, 0xFF     \n\t"
+        : [ms] "=&r"(old_mask)
+        :
+        :);
+
+    for (int j = 0; j < (int) kv_count; ++j) {
+        const et_fp16_t * k_row    = (const et_fp16_t *) (k_base + (kv_start + j) * nb1_k) + dk_start;
+        et_fp16_t *       even_row = out + (j * 2) * 32;
+        et_fp16_t *       odd_row  = out + (j * 2 + 1) * 32;
+        __asm__ volatile(
+            "flw.ps    f2, 0(%[src0])  \n\t"  // load row[0..15]
+            "flw.ps    f3, 0(%[src1])  \n\t"  // load row[16..31]
+            "fpackreph.pi f4, f2       \n\t"  // even_lo from src0
+            "fpackreph.pi f6, f3       \n\t"  // even_lo from src1 (interleaved)
+            "fsrli.pi  f5, f2, 16      \n\t"  // shift src0 for odd
+            "fsrli.pi  f7, f3, 16      \n\t"  // shift src1 for odd (interleaved)
+            "fpackreph.pi f5, f5       \n\t"  // odd from src0
+            "fpackreph.pi f7, f7       \n\t"  // odd from src1
+            "mov.m.x   m0, x0, 0x0F   \n\t"
+            "fcmovm.ps f4, f4, f6      \n\t"  // merge even halves
+            "fcmovm.ps f5, f5, f7      \n\t"  // merge odd halves
+            "mov.m.x   m0, x0, 0xFF   \n\t"
+            "fsw.ps    f4, 0(%[even])  \n\t"
+            "fsw.ps    f5, 0(%[odd])   \n\t"
+            :
+            : [src0] "r"(k_row), [src1] "r"(k_row + 16), [even] "r"(even_row), [odd] "r"(odd_row)
+            : "f2", "f3", "f4", "f5", "f6", "f7", "memory");
+    }
+
+    __asm__ volatile("mova.m.x  %[ms]            \n\t" : : [ms] "r"(old_mask));
+
+    for (int j = (int) kv_count; j < TILE_KV; ++j) {
+        et_fp16_t * even_row = out + (j * 2) * 32;
+        et_fp16_t * odd_row  = out + (j * 2 + 1) * 32;
+        for (int l = 0; l < TILE_K / 2; ++l) {
+            even_row[l] = 0;
+            odd_row[l]  = 0;
+        }
+    }
+}
+
+// Build interleaved B panel for TensorFMA16A32 (weights @ V).
+static inline void __attribute__((always_inline)) pack_v_interleaved(et_fp16_t *  out,
+                                                                     const char * v_head,
+                                                                     int64_t      kv_base,
+                                                                     int64_t      dv_start,
+                                                                     int64_t      kv_count,
+                                                                     int64_t      nb1_v) {
+    for (int k = 0; k < TILE_KV; ++k) {
+        const int         l   = k >> 1;
+        const int         r   = k & 1;
+        et_fp16_t * const dst = out + l * 32 + r;
+        if (k < (int) kv_count) {
+            const et_fp16_t * v_row = (const et_fp16_t *) (v_head + (kv_base + k) * nb1_v) + dv_start;
+            for (int n = 0; n < 16; ++n) {
+                dst[n * 2] = v_row[n];
+            }
+        } else {
+            for (int n = 0; n < 16; ++n) {
+                dst[n * 2] = 0;
+            }
+        }
+    }
+}
+
+// Prefetch KV rows for one chunk into L2.
+static inline void __attribute__((always_inline)) prefetch_kv_to_l2(const char * head,
+                                                                    int64_t      kv_start,
+                                                                    int64_t      d_start,
+                                                                    int64_t      kv_count,
+                                                                    int64_t      nb1) {
+    const void * base = (const void *) (head + kv_start * nb1 + d_start * 2);
+    l2_prefetch(base, (uint64_t) kv_count, (uint64_t) nb1);
+}
+
+static inline void __attribute__((always_inline)) convert_q_row_f32_to_f16(et_fp16_t *   dst,
+                                                                           const float * src,
+                                                                           int64_t       n) {
+    static const int32_t __attribute__((aligned(32))) offsets[8] = { 0, 2, 4, 6, 8, 10, 12, 14 };
+
+    unsigned long old_mask;
+    __asm__ volatile(
+        "mova.x.m  %[ms]             \n\t"
+        "mov.m.x   m0, x0, 0xFF      \n\t"
+        "flw.ps    f1, 0(%[offs])    \n\t"
+        : [ms] "=&r"(old_mask)
+        : [offs] "r"(offsets)
+        : "f1");
+
+    for (int64_t d = 0; d < n; d += 8) {
+        __asm__ volatile(
+            "flw.ps      f2, 0(%[src])    \n\t"
+            "fcvt.f16.ps f3, f2           \n\t"
+            "fsch.ps     f3, f1(%[dst])   \n\t"
+            :
+            : [src] "r"(src + d), [dst] "r"(dst + d)
+            : "f2", "f3", "memory");
+    }
+
+    __asm__ volatile("mova.m.x  %[ms]             \n\t" : : [ms] "r"(old_mask));
+}
+
+static inline void __attribute__((always_inline)) zero_acc_vec(float * acc, int64_t dv) {
+    const float   zero = 0.0f;
+    unsigned long old_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(old_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+    __asm__ volatile("fbc.ps  f2, 0(%[z])" ::[z] "r"(&zero) : "f2");
+
+    for (int64_t d = 0; d < dv; d += 8) {
+        __asm__ volatile("fsw.ps  f2, 0(%[a])     \n\t" ::[a] "r"(acc + d) : "f2", "memory");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(old_mask));
+}
+
+static inline void __attribute__((always_inline)) scale_acc_vec(float * acc, int64_t dv, float scale) {
+    unsigned long old_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(old_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    for (int64_t d = 0; d < dv; d += 8) {
+        __asm__ volatile(
+            "fbc.ps    f2, 0(%[s])    \n\t"
+            "flw.ps    f3, 0(%[a])    \n\t"
+            "fmul.ps   f3, f3, f2     \n\t"
+            "fsw.ps    f3, 0(%[a])    \n\t"
+            :
+            : [s] "r"(&scale), [a] "r"(acc + d)
+            : "f2", "f3", "memory");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(old_mask));
+}
+
+static inline void __attribute__((always_inline)) normalize_store_vec(float * out,
+                                                                      float * acc,
+                                                                      int64_t dv,
+                                                                      float   inv,
+                                                                      int     use_fast_store) {
+    unsigned long old_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(old_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    for (int64_t d = 0; d < dv; d += 8) {
+        __asm__ volatile(
+            "fbc.ps    f2, 0(%[inv])   \n\t"
+            "flw.ps    f3, 0(%[a])     \n\t"
+            "fmul.ps   f3, f3, f2      \n\t"
+            "fsw.ps    f3, 0(%[a])     \n\t"
+            :
+            : [inv] "r"(&inv), [a] "r"(acc + d)
+            : "f2", "f3", "memory");
+        if (use_fast_store) {
+            __asm__ volatile(
+                "flw.ps  f4, 0(%[a])     \n\t"
+                "fsw.ps  f4, 0(%[o])     \n\t"
+                :
+                : [a] "r"(acc + d), [o] "r"(out + d)
+                : "f4", "memory");
+        } else {
+            atomic_store_f32((volatile float *) &out[d + 0], acc[d + 0]);
+            atomic_store_f32((volatile float *) &out[d + 1], acc[d + 1]);
+            atomic_store_f32((volatile float *) &out[d + 2], acc[d + 2]);
+            atomic_store_f32((volatile float *) &out[d + 3], acc[d + 3]);
+            atomic_store_f32((volatile float *) &out[d + 4], acc[d + 4]);
+            atomic_store_f32((volatile float *) &out[d + 5], acc[d + 5]);
+            atomic_store_f32((volatile float *) &out[d + 6], acc[d + 6]);
+            atomic_store_f32((volatile float *) &out[d + 7], acc[d + 7]);
+        }
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(old_mask));
+}
+
+static inline size_t tensor_bytes_fa(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+// Evict a byte range from L1D to L2 SCP, splitting into batches of ≤16
+// cache lines (the hw limit for evict_to_l2). Use before a barrier when
+// another minion in the shire needs to read the region, or after a barrier
+// on the reader side to drop stale L1D copies before reading peer data.
+static inline void __attribute__((always_inline)) evict_range_to_l2(const void * addr, int64_t bytes) {
+    if (bytes <= 0) {
+        return;
+    }
+    int64_t      lines = (bytes + 63) / 64;
+    const char * p     = (const char *) addr;
+    while (lines > 0) {
+        int64_t batch = lines > 16 ? 16 : lines;
+        evict_to_l2((const void *) p, (uint64_t) batch, 64);
+        p += batch * 64;
+        lines -= batch;
+    }
+}
+
+// Split-KV online merge inner loop:
+//
+//   for d in [0, dv) step 8:
+//       acc[d..d+8] = alpha_own * acc[d..d+8] + alpha_peer * peer_acc[d..d+8]
+//
+// Runs on the reducer (k_split == 0) after all tensor_fma ops for the row are
+// complete, so f0..f31 are dead at entry. We still bracket the loop in inline
+// asm with explicit f2/f3/f4/f5 clobbers to lock register usage down — per the
+// MM register lifetime rule, never let the compiler mingle FP ops into code
+// that sits anywhere near a tensor engine output window.
+static inline void __attribute__((always_inline)) merge_rescale_add_asm(float *       acc,
+                                                                        const float * peer_acc,
+                                                                        int64_t       dv,
+                                                                        float         alpha_own,
+                                                                        float         alpha_peer) {
+    unsigned long old_mask;
+    __asm__ volatile(
+        "mova.x.m  %[ms]              \n\t"
+        "mov.m.x   m0, x0, 0xFF       \n\t"
+        "fbc.ps    f4, 0(%[ao])       \n\t"  // broadcast alpha_own
+        "fbc.ps    f5, 0(%[ap])       \n\t"  // broadcast alpha_peer
+        : [ms] "=&r"(old_mask)
+        : [ao] "r"(&alpha_own), [ap] "r"(&alpha_peer)
+        : "f4", "f5");
+
+    for (int64_t d = 0; d < dv; d += 8) {
+        __asm__ volatile(
+            "flw.ps    f2, 0(%[a])      \n\t"  // own
+            "flw.ps    f3, 0(%[p])      \n\t"  // peer
+            "fmul.ps   f2, f2, f4       \n\t"  // own *= alpha_own
+            "fmul.ps   f3, f3, f5       \n\t"  // peer *= alpha_peer
+            "fadd.ps   f2, f2, f3       \n\t"
+            "fsw.ps    f2, 0(%[a])      \n\t"
+            :
+            : [a] "r"(acc + d), [p] "r"(peer_acc + d)
+            : "f2", "f3", "memory");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(old_mask));
+}
+
+int entry_point(struct ggml_et_flash_attn_ext_params * params, void * env) {
+    (void) env;
+
+    uint64_t hart_id  = get_hart_id();
+    uint64_t shire_id = get_shire_id();
+
+    if (shire_id >= NUM_COMPUTE_SHIRES) {
+        return 0;
+    }
+
+    const int is_hart1     = hart_id & 1;
+    uint64_t  local_minion = (hart_id >> 1) & 0x1F;
+
+    struct ggml_tensor * q        = &params->src0;
+    struct ggml_tensor * k        = &params->src1;
+    struct ggml_tensor * v        = &params->src2;
+    struct ggml_tensor * dst      = &params->dst;
+    const int32_t        has_mask = params->has_mask;
+    struct ggml_tensor * mask     = has_mask ? &params->mask : (struct ggml_tensor *) 0;
+
+    const char * q_data   = (const char *) q->data;
+    const char * k_data   = (const char *) k->data;
+    const char * v_data   = (const char *) v->data;
+    char *       dst_data = (char *) dst->data;
+
+    // et_barrier(ET_BARRIER_GLOBAL);
+    evict_region_past_l2(q->data, tensor_bytes_fa(q));
+    evict_region_past_l2(k->data, tensor_bytes_fa(k));
+    evict_region_past_l2(v->data, tensor_bytes_fa(v));
+    if (mask) {
+        evict_region_past_l2(mask->data, tensor_bytes_fa(mask));
+    }
+    et_barrier(ET_BARRIER_GLOBAL);
+
+    const int64_t dk  = q->ne[0];
+    const int64_t nq  = q->ne[1];
+    const int64_t nhq = q->ne[2];
+    const int64_t no  = q->ne[3];
+    const int64_t nk  = k->ne[1];
+    const int64_t nhk = k->ne[2];
+    const int64_t dv  = v->ne[0];
+
+    if (dv > FA_DV_MAX || dk > FA_DK_MAX) {
+        return -1;
+    }
+    if (k->nb[0] != 2 || v->nb[0] != 2) {
+        return -1;
+    }
+    if ((dk % 8) != 0 || (dv % 16) != 0) {
+        return -1;
+    }
+
+    const int64_t gqa_ratio      = nhq / nhk;
+    const int64_t total_rows     = nq * nhq * no;
+    const float   scale          = params->scale;
+    const int     use_fast_store = (dv % 16 == 0);
+
+    // Split-KV team layout (mirrors mul_mat_f16_matrix_engine.c)
+    //
+    // When total_rows is small compared to the total minion count (typical
+    // for decode: nq=1, nhq small), we group k_splits minions within the
+    // same shire into a team that cooperates on one row by splitting the
+    // KV dimension. Each team member computes a partial (M_p, S_p, acc_p)
+    // over its KV slab; the k_split==0 member merges the partials with the
+    // softmax combine rule.
+    //
+    // k_splits is a power of two, capped at MINIONS_PER_SHIRE (so a team
+    // never spans shires — L2 SCP is shire-local) and at nk_tiles (so each
+    // team member gets at least one KV tile).
+    const int64_t nk_tiles      = (nk + TILE_KV - 1) / TILE_KV;
+    const int64_t total_minions = 2 * NUM_COMPUTE_SHIRES * MINIONS_PER_SHIRE;
+    int64_t       k_splits      = 1;
+    if (total_rows < total_minions) {
+        int64_t target = total_minions / total_rows;
+        int64_t ks     = 1;
+        while (ks * 2 <= target && ks * 2 <= MINIONS_PER_SHIRE && ks * 2 <= nk_tiles) {
+            ks *= 2;
+        }
+        k_splits = ks;
+    }
+
+    const int64_t tiles_per_shire = MINIONS_PER_SHIRE / k_splits;
+    const int64_t k_split         = (int64_t) local_minion % k_splits;
+    const int64_t local_tile_idx  = (int64_t) local_minion / k_splits;
+    const int64_t tiles_stride    = (int64_t) NUM_COMPUTE_SHIRES * tiles_per_shire;
+
+    // KV slab for this k_split. With k_splits=1 this is the full range.
+    const int64_t tiles_per_split_rounded = (nk_tiles + k_splits - 1) / k_splits;
+    const int64_t tile_start              = k_split * tiles_per_split_rounded;
+    int64_t       tile_end                = tile_start + tiles_per_split_rounded;
+    if (tile_end > nk_tiles) {
+        tile_end = nk_tiles;
+    }
+    const int64_t kv_start = tile_start * TILE_KV;
+    int64_t       kv_end   = tile_end * TILE_KV;
+    if (kv_end > nk) {
+        kv_end = nk;
+    }
+
+    // L2 SCP pointers for this minion
+    uint64_t    scp_base  = local_minion * SCP_PER_MINION;
+    et_fp16_t * scp_kp[2] = {
+        (et_fp16_t *) et_shire_l2scp_local(scp_base + SCP_KP0_OFF),
+        (et_fp16_t *) et_shire_l2scp_local(scp_base + SCP_KP1_OFF),
+    };
+
+    // Hart 1 does K-panel packing
+    //
+    // When k_splits > 1, hart 1 must also participate in the two shire
+    // barriers that bracket the merge phase (one before and one after, so
+    // the reducer can read peer partials safely and the writers know when
+    // their acc/stats slab is free to reuse). Hart 1 has no useful work
+    // between those barriers.
+    //
+    // All teams in a shire must iterate the same number of times so the
+    // per-iter shire barriers stay balanced. Teams whose assigned row is
+    // past total_rows still call the barriers but skip the packing work.
+    et_barrier(ET_BARRIER_SHIRE);
+    // et_barrier(ET_BARRIER_GLOBAL);
+    if (is_hart1) {
+        uint32_t      chunk_id = 0;
+        const int64_t row_base = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES;
+
+        int64_t max_iters;
+        if (k_splits > 1) {
+            max_iters = (total_rows + tiles_stride - 1) / tiles_stride;
+        } else {
+            max_iters = (row_base >= total_rows) ? 0 : ((total_rows - row_base - 1) / tiles_stride + 1);
+        }
+
+        for (int64_t iter = 0; iter < max_iters; iter++) {
+            const int64_t row      = row_base + iter * tiles_stride;
+            const int     has_work = (row < total_rows);
+
+            if (has_work) {
+                const int64_t iq3 = row / (nhq * nq);
+                const int64_t rem = row % (nhq * nq);
+                const int64_t iq2 = rem / nq;
+                const int64_t ik2 = iq2 / gqa_ratio;
+
+                const char * k_head = k_data + ik2 * k->nb[2] + iq3 * k->nb[3];
+
+                for (int64_t kv_base = kv_start; kv_base < kv_end; kv_base += TILE_KV) {
+                    const int64_t kv_count = (kv_base + TILE_KV <= nk) ? TILE_KV : (nk - kv_base);
+
+                    for (int64_t dk_chunk = 0; dk_chunk < dk; dk_chunk += TILE_K) {
+                        int buf = chunk_id & 1;
+
+                        // Back-pressure: before overwriting buf[buf] on chunk N
+                        // (which will displace chunk N-2), wait for hart 0 to
+                        // post that it's done with chunk N-2. Gates both
+                        // directions of double-buffering.
+                        //
+                        // NOTE: we use et_sem_* (FCC 0 only) rather than
+                        // et_barrier(ET_BARRIER_MINION) here because the
+                        // minion barrier for minion 0 shares FLB 0 with
+                        // ET_BARRIER_SHIRE. Mixing them deadlocks. See
+                        // feedback_flb_collision.
+                        if (chunk_id >= 2) {
+                            et_sem_wait(ET_BARRIER_MINION);
+                        }
+
+                        // Prefetch K data for this chunk
+                        prefetch_kv_to_l2(k_head, kv_base, dk_chunk, kv_count, k->nb[1]);
+
+                        pack_k_for_transpose16(scp_kp[buf], k_head, kv_base, dk_chunk, kv_count, k->nb[1]);
+
+                        FENCE;
+                        flush_to_l2(scp_kp[buf], 16, 64);
+                        flush_to_l2((et_fp16_t *) ((char *) scp_kp[buf] + 1024), 16, 64);
+                        WAIT_CACHEOPS;
+
+                        // Signal: this buf is ready for hart 0 to consume.
+                        et_sem_post(ET_BARRIER_MINION);
+
+                        chunk_id++;
+                    }
+                }
+            }
+
+            // Shire barriers for split-KV merge (hart 1 is a passive arrival).
+            if (k_splits > 1) {
+                et_barrier(ET_BARRIER_SHIRE);  // A: team has written its partial
+                et_barrier(ET_BARRIER_SHIRE);  // B: reducer has finished merge
+            }
+        }
+
+        // Self-drain phantom FCC 0 credits left by the wait-skip on the
+        // first 2 chunks. Hart 1 issued chunk_id posts but only
+        // (chunk_id - 2) waits (when chunk_id >= 2), so hart 1's FCC 0
+        // carries +min(chunk_id,2) credits from hart 0's matching posts
+        // that hart 1 never consumed.
+        uint32_t drain = (chunk_id < 2) ? chunk_id : 2;
+        for (uint32_t d = 0; d < drain; d++) {
+            et_sem_wait(ET_BARRIER_MINION);
+        }
+
+        // FENCE;
+        // et_barrier(ET_BARRIER_GLOBAL);
+        return 0;
+    }
+
+    // Hart 0: tensor engine compute
+#ifndef UBERKERNEL_SUPPRESS_SCP_SETUP
+    setup_cache_scp();
+#endif
+    CLEAR_TENSOR_ERROR;
+
+    // Q converted to F16 (one row at a time)
+    et_fp16_t q_f16[FA_DK_MAX] __attribute__((aligned(64)));
+
+    // Score buffer for QK^T output (16 scores per KV tile)
+    float scores[TILE_KV] __attribute__((aligned(64)));
+
+    // Small buffers for V accumulation
+    et_fp16_t w_f16_buf[32] __attribute__((aligned(64)));       // 64 bytes
+    et_fp16_t vpanel_buf[8 * 32] __attribute__((aligned(64)));  // 512 bytes
+
+    float * acc = (float *) et_shire_l2scp_local(scp_base + SCP_ACC_OFF);
+
+    uint32_t chunk_id = 0;
+
+    // Iter-based outer loop (matches hart 1). When k_splits > 1 all teams
+    // in a shire iterate the same number of times so the per-row shire
+    // barriers stay balanced; iterations with row >= total_rows skip the
+    // compute but still participate in the barriers.
+    const int64_t hart0_row_base = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES;
+    int64_t       hart0_max_iters;
+    if (k_splits > 1) {
+        hart0_max_iters = (total_rows + tiles_stride - 1) / tiles_stride;
+    } else {
+        hart0_max_iters = (hart0_row_base >= total_rows) ? 0 : ((total_rows - hart0_row_base - 1) / tiles_stride + 1);
+    }
+
+    for (int64_t iter = 0; iter < hart0_max_iters; iter++) {
+        const int64_t row = hart0_row_base + iter * tiles_stride;
+        if (row >= total_rows) {
+            // No-work iteration: only participate in barriers (k_splits > 1).
+            if (k_splits > 1) {
+                et_barrier(ET_BARRIER_SHIRE);  // A
+                et_barrier(ET_BARRIER_SHIRE);  // B
+            }
+            continue;
+        }
+
+        const int64_t iq3 = row / (nhq * nq);
+        const int64_t rem = row % (nhq * nq);
+        const int64_t iq2 = rem / nq;
+        const int64_t iq1 = rem % nq;
+        const int64_t ik2 = iq2 / gqa_ratio;
+
+        // Read Q row (F32) and convert to F16
+        const float * pq = (const float *) (q_data + iq1 * q->nb[1] + iq2 * q->nb[2] + iq3 * q->nb[3]);
+        convert_q_row_f32_to_f16(q_f16, pq, dk);
+
+        // V base for this head + batch (K packing handled by hart 1)
+        const char * v_head = v_data + ik2 * v->nb[2] + iq3 * v->nb[3];
+
+        // Output pointer
+        float * out = (float *) (dst_data + iq2 * dst->nb[1] + iq1 * dst->nb[2] + iq3 * dst->nb[3]);
+
+        zero_acc_vec(acc, dv);
+        float        M         = ET_NEG_INF_F;
+        float        S         = 0.0f;
+        const char * mask_base = has_mask ? get_mask_row_base(mask, iq1, iq2, iq3) : (const char *) 0;
+
+        // Flush Q_f16 to L2 so tensor_load can see it
+        FENCE;
+        flush_to_l2(q_f16, (dk * 2 + 63) / 64, 64);
+        WAIT_CACHEOPS;
+
+        for (int64_t kv_base = kv_start; kv_base < kv_end; kv_base += TILE_KV) {
+            const int64_t kv_count = (kv_base + TILE_KV <= nk) ? TILE_KV : (nk - kv_base);
+
+            // Set tensor_mask for partial tiles
+            if (kv_count < TILE_KV) {
+                uint64_t tmask = (1ULL << kv_count) - 1;
+                __asm__ __volatile__("csrw 0x805, %0" : : "r"(tmask));
+            }
+
+            // ============================================================
+            // QK^T via TensorFMA16A32
+            // ============================================================
+
+            // Pipelined QK^T:
+            //   - Q for the whole row is preloaded once into A_L1[0..n-1].
+            //     Each FMA picks its chunk via scp_loc_a = chunk_idx.
+            //   - K is double-buffered in L1: K_BUFS[0]=lines 16..31,
+            //     K_BUFS[1]=lines 32..47.
+            //   - In iteration i (1..N-1), the K[i] load runs concurrently
+            //     with the FMA on chunk i-1: they touch disjoint L1 regions
+            //     (FMA reads K_BUFS[(i-1)&1], load writes K_BUFS[i&1]; FMA
+            //     reads A_L1[i-1], load doesn't touch A_L1).
+            //
+            // L1 footprint: max dk=512 → Q uses 16 lines (0..15), K uses 32
+            // lines (16..47). Within ET-SoC-1 L1 SCP (≥128 lines per minion).
+            const int64_t  n_dk_chunks = dk / TILE_K;
+            const uint64_t K_BUFS[2]   = {
+                (uint64_t) B_L1_START,         // 16..31
+                (uint64_t) (B_L1_START + 16),  // 32..47
+            };
+
+            // Preload entire Q row into A_L1[0..n_dk_chunks-1] (one tensor_load,
+            // one wait, regardless of dk).
+            tensor_load(false, false, A_L1_START, TENSOR_LOAD_PLAIN, 0, (uint64_t) q_f16, 0,
+                        (uint64_t) (n_dk_chunks - 1), 64, 0);
+
+            // Prologue: wait hart 1's K[0], issue K[0] load, wait both loads.
+            {
+                int buf = chunk_id & 1;
+                et_sem_wait(ET_BARRIER_MINION);
+                tensor_load(false, false, K_BUFS[0], TENSOR_LOAD_TRANSPOSE16, 0, (uint64_t) scp_kp[buf], 0, 15, 64, 1);
+                tensor_wait(TENSOR_LOAD_WAIT_0);  // Q row complete
+                tensor_wait(TENSOR_LOAD_WAIT_1);  // K[0] complete
+                et_sem_post(ET_BARRIER_MINION);
+                chunk_id++;
+            }
+
+            // Main loop: in iter i, issue K[i] load and FMA chunk i-1 in
+            // parallel. The matrix engine is busy on FMA[i-1] while the
+            // load unit fetches K[i] from L2 SCP.
+            //
+            // Order of waits matters: wait K[i] load first, then sem_post
+            // immediately (frees scp_kp[buf] for hart 1 to refill chunk i+2),
+            // then wait FMA. Putting sem_post after FMA wait would stall
+            // hart 1 by a full FMA latency — defeating the producer pipeline.
+            for (int64_t i = 1; i < n_dk_chunks; i++) {
+                int buf         = chunk_id & 1;
+                int k_slot_prev = (int) ((i - 1) & 1);
+                int k_slot      = (int) (i & 1);
+
+                et_sem_wait(ET_BARRIER_MINION);
+                tensor_load(false, false, K_BUFS[k_slot], TENSOR_LOAD_TRANSPOSE16, 0, (uint64_t) scp_kp[buf], 0, 15, 64,
+                            1);
+
+                tensor_fma((kv_count < TILE_KV), 3, 0, 15, 0, false, false, false, false, K_BUFS[k_slot_prev],
+                           (uint64_t) (i - 1), TENSOR_FMA_OP_FP16, (i == 1));
+
+                tensor_wait(TENSOR_LOAD_WAIT_1);  // K[i] in L1
+                et_sem_post(ET_BARRIER_MINION);   // release scp_kp[buf] EARLY
+                tensor_wait(TENSOR_FMA_WAIT);     // then wait FMA[i-1]
+                chunk_id++;
+            }
+
+            // Epilogue: FMA on the last chunk (no overlapping load).
+            {
+                int k_slot_last = (int) ((n_dk_chunks - 1) & 1);
+                tensor_fma((kv_count < TILE_KV), 3, 0, 15, 0, false, false, false, false, K_BUFS[k_slot_last],
+                           (uint64_t) (n_dk_chunks - 1), TENSOR_FMA_OP_FP16, (n_dk_chunks == 1));
+                tensor_wait(TENSOR_FMA_WAIT);
+            }
+
+            // Prefetch V rows for this tile.
+            // Only useful for the partial-tile path below
+            if (kv_count < TILE_KV) {
+                for (int64_t d = 0; d < dv; d += 32) {
+                    prefetch_kv_to_l2(v_head, kv_base, d, kv_count, v->nb[1]);
+                }
+            }
+
+            // Extract QK^T scores from vector register file
+            __asm__ volatile("" ::: "f0", "f1");
+            {
+                unsigned long _ms;
+                __asm__ volatile(
+                    "mova.x.m  %[ms]                \n\t"
+                    "mov.m.x   m0, x0, 0xFF         \n\t"
+                    "fbc.ps    f2, 0(%[p_scale])    \n\t"
+                    "fmul.ps   f0, f0, f2           \n\t"
+                    "fmul.ps   f1, f1, f2           \n\t"
+                    "fsw.ps    f0, 0(%[dst])        \n\t"
+                    "fsw.ps    f1, 32(%[dst])       \n\t"
+                    "mova.m.x  %[ms]                \n\t"
+                    : [ms] "=&r"(_ms)
+                    : [dst] "r"(scores), [p_scale] "r"(&scale)
+                    : "f0", "f1", "f2", "memory");
+            }
+
+            // ============================================================
+            // Two-phase softmax + V accumulation
+            // ============================================================
+
+            float weights[TILE_KV] __attribute__((aligned(64)));
+            {
+                // A1: apply mask to scores, pad unused slots
+                for (int64_t j = 0; j < kv_count; ++j) {
+                    if (has_mask) {
+                        float mv = get_mask_val_from_base(mask, mask_base, kv_base + j);
+                        if (mv == ET_NEG_INF_F || mv != mv) {
+                            scores[j] = ET_NEG_INF_F;
+                        } else {
+                            scores[j] += mv;
+                        }
+                    }
+                }
+                for (int64_t j = kv_count; j < TILE_KV; ++j) {
+                    scores[j] = ET_NEG_INF_F;
+                }
+
+                // A1b: SIMD horizontal max across all 16 scores
+                float tile_max;
+                {
+                    unsigned long _ms;
+                    __asm__ volatile(
+                        "mova.x.m  %[ms]              \n\t"
+                        "mov.m.x   m0, x0, 0xFF       \n\t"
+                        "flw.ps    f2, 0(%[sc])       \n\t"
+                        "flw.ps    f3, 32(%[sc])      \n\t"
+                        "fmax.ps   f2, f2, f3         \n\t"
+                        "fswizz.ps f3, f2, 0xB1       \n\t"
+                        "fmax.ps   f2, f2, f3         \n\t"
+                        "fswizz.ps f3, f2, 0x4E       \n\t"
+                        "fmax.ps   f2, f2, f3         \n\t"
+                        "fmvz.x.ps t0, f2, 4          \n\t"
+                        "fbcx.ps   f3, t0             \n\t"
+                        "fmax.ps   %[tm], f2, f3      \n\t"
+                        "mova.m.x  %[ms]              \n\t"
+                        : [ms] "=&r"(_ms), [tm] "=f"(tile_max)
+                        : [sc] "r"(scores)
+                        : "f2", "f3", "t0", "memory");
+                }
+
+                if (tile_max > ET_NEG_INF_F) {
+                    // A2: rescale accumulator if this tile has a new global max
+                    if (tile_max > M) {
+                        float rescale = et_exp2f((M - tile_max) * 1.4426950408889634f);
+                        scale_acc_vec(acc, dv, rescale);
+                        S *= rescale;
+                        M = tile_max;
+                    }
+
+                    // A3: SIMD exp2 + horizontal sum
+                    // Interleaved: f2/f3 chains alternate to hide ALU latency.
+                    // fexp.ps has multi-cycle latency — the two independent
+                    // exp2 calls naturally pipeline.
+                    {
+                        const float   log2e = 1.4426950408889634f;
+                        float         S_tile;
+                        unsigned long _ms;
+                        __asm__ volatile(
+                            "mova.x.m  %[ms]              \n\t"
+                            "mov.m.x   m0, x0, 0xFF       \n\t"
+                            "flw.ps    f2, 0(%[sc])       \n\t"
+                            "fbc.ps    f4, 0(%[pM])       \n\t"
+                            "flw.ps    f3, 32(%[sc])      \n\t"
+                            "fbc.ps    f5, 0(%[pL])       \n\t"
+                            "fsub.ps   f2, f2, f4         \n\t"
+                            "fsub.ps   f3, f3, f4         \n\t"
+                            "fmul.ps   f2, f2, f5         \n\t"
+                            "fmul.ps   f3, f3, f5         \n\t"
+                            "fexp.ps   f2, f2             \n\t"
+                            "fexp.ps   f3, f3             \n\t"
+                            "fsw.ps    f2, 0(%[wt])       \n\t"
+                            "fsw.ps    f3, 32(%[wt])      \n\t"
+                            "fadd.ps   f2, f2, f3, rne    \n\t"
+                            "fswizz.ps f3, f2, 0xB1       \n\t"
+                            "fadd.ps   f2, f2, f3, rne    \n\t"
+                            "fswizz.ps f3, f2, 0x4E       \n\t"
+                            "fadd.ps   f2, f2, f3, rne    \n\t"
+                            "fmvz.x.ps t0, f2, 4          \n\t"
+                            "fbcx.ps   f3, t0             \n\t"
+                            "fadd.ps   %[st], f2, f3, rne \n\t"
+                            "mova.m.x  %[ms]              \n\t"
+                            : [ms] "=&r"(_ms), [st] "=f"(S_tile)
+                            : [pM] "r"(&M), [pL] "r"(&log2e), [sc] "r"(scores), [wt] "r"(weights)
+                            : "f2", "f3", "f4", "f5", "t0", "memory");
+                        S += S_tile;
+                    }
+
+                    // Phase B: weights @ V via TensorFMA16A32
+                    {
+                        // B1: convert weights F32 → F16
+                        convert_q_row_f32_to_f16(w_f16_buf, weights, TILE_KV);
+
+                        FENCE;
+                        flush_to_l2(w_f16_buf, 1, 64);
+                        WAIT_CACHEOPS;
+
+                        // Issue weights load (wait_id=0) and the first V chunk
+                        // load (wait_id=1) concurrently. Weights comes from
+                        // L2 SCP (just flushed); V[0] comes from DRAM via
+                        // INTERLEAVE16 — running them in parallel hides the
+                        // shorter load behind the longer one. For partial
+                        // tiles, V is software-packed below — we only kick
+                        // off the early V load on the full-tile fast path.
+                        tensor_load(false, false, A_L1_START, TENSOR_LOAD_PLAIN, 0, (uint64_t) w_f16_buf, 0, 0, 64, 0);
+
+                        const int       v_full_tile = (kv_count == TILE_KV);
+                        const uintptr_t v_base      = (uintptr_t) v_head + kv_base * v->nb[1];
+                        const uint64_t  nb1_v       = (uint64_t) v->nb[1];
+                        uint64_t        b_cur       = 8;
+
+                        if (v_full_tile) {
+                            tensor_load(false, false, b_cur, TENSOR_LOAD_INTERLEAVE16, 0, (uint64_t) v_base, 0, 7,
+                                        nb1_v, 1);
+                        }
+
+                        tensor_wait(TENSOR_LOAD_WAIT_0);      // weights in A_L1
+                        if (v_full_tile) {
+                            tensor_wait(TENSOR_LOAD_WAIT_1);  // V[0] in b_cur
+                        }
+
+                        // B2: process dv in chunks of 16
+                        if (v_full_tile) {
+                            for (int64_t dv_off = 0; dv_off < dv; dv_off += 16) {
+                                const uint64_t b_nxt = b_cur ^ 24;
+
+                                if (dv_off + 16 < dv) {
+                                    tensor_load(false, false, b_nxt, TENSOR_LOAD_INTERLEAVE16, 0,
+                                                (uint64_t) (v_base + (dv_off + 16) * 2), 0, 7, nb1_v, 1);
+                                }
+
+                                tensor_fma(false, 3, 0, 7, 0, false, false, false, false, b_cur, A_L1_START,
+                                           TENSOR_FMA_OP_FP16, true);
+                                tensor_wait(TENSOR_FMA_WAIT);
+
+                                __asm__ volatile("" ::: "f0", "f1");
+                                {
+                                    unsigned long _ms;
+                                    __asm__ volatile(
+                                        "mova.x.m  %[ms]            \n\t"
+                                        "mov.m.x   m0, x0, 0xFF     \n\t"
+                                        "flw.ps    f2, 0(%[pa])     \n\t"
+                                        "flw.ps    f3, 32(%[pa])    \n\t"
+                                        "fadd.ps   f0, f0, f2       \n\t"
+                                        "fadd.ps   f1, f1, f3       \n\t"
+                                        "fsw.ps    f0, 0(%[pa])     \n\t"
+                                        "fsw.ps    f1, 32(%[pa])    \n\t"
+                                        "mova.m.x  %[ms]            \n\t"
+                                        : [ms] "=&r"(_ms)
+                                        : [pa] "r"(acc + dv_off)
+                                        : "f0", "f1", "f2", "f3", "memory");
+                                }
+
+                                if (dv_off + 16 < dv) {
+                                    tensor_wait(TENSOR_LOAD_WAIT_1);
+                                    b_cur = b_nxt;
+                                }
+                            }
+                        } else {
+                            // Partial tile: software pack, no pipeline
+                            for (int64_t dv_off = 0; dv_off < dv; dv_off += 16) {
+                                pack_v_interleaved(vpanel_buf, v_head, kv_base, dv_off, kv_count, v->nb[1]);
+                                FENCE;
+                                flush_to_l2(vpanel_buf, 8, 64);
+                                WAIT_CACHEOPS;
+                                tensor_load(false, false, B_L1_START, TENSOR_LOAD_PLAIN, 0, (uint64_t) vpanel_buf, 0, 7,
+                                            64, 0);
+                                tensor_wait(TENSOR_LOAD_WAIT_0);
+
+                                tensor_fma(false, 3, 0, 7, 0, false, false, false, false, B_L1_START, A_L1_START,
+                                           TENSOR_FMA_OP_FP16, true);
+                                tensor_wait(TENSOR_FMA_WAIT);
+
+                                __asm__ volatile("" ::: "f0", "f1");
+                                {
+                                    unsigned long _ms;
+                                    __asm__ volatile(
+                                        "mova.x.m  %[ms]            \n\t"
+                                        "mov.m.x   m0, x0, 0xFF     \n\t"
+                                        "flw.ps    f2, 0(%[pa])     \n\t"
+                                        "flw.ps    f3, 32(%[pa])    \n\t"
+                                        "fadd.ps   f0, f0, f2       \n\t"
+                                        "fadd.ps   f1, f1, f3       \n\t"
+                                        "fsw.ps    f0, 0(%[pa])     \n\t"
+                                        "fsw.ps    f1, 32(%[pa])    \n\t"
+                                        "mova.m.x  %[ms]            \n\t"
+                                        : [ms] "=&r"(_ms)
+                                        : [pa] "r"(acc + dv_off)
+                                        : "f0", "f1", "f2", "f3", "memory");
+                                }
+                            }
+                        }
+                    }
+                }
+            }
+        }
+
+        // Finalize row
+        //
+        // k_splits == 1: this minion computed the full row. Normalize in
+        //                place and store to DRAM.
+        //
+        // k_splits  > 1: this minion computed a KV slab. Publish the
+        //                partial (M, S, acc) to L2 SCP, sync with the
+        //                team, and let the k_split==0 member do the
+        //                softmax combine and the final store. All tensor
+        //                engine ops are complete before this block, so
+        //                f0..f31 are free to use.
+        if (k_splits > 1) {
+            // Publish our partial.
+            volatile float * my_stats = (volatile float *) et_shire_l2scp_local(scp_base + SCP_STATS_OFF);
+            my_stats[0]               = M;
+            my_stats[1]               = S;
+            FENCE;
+            evict_range_to_l2(acc, (int64_t) dv * (int64_t) sizeof(float));
+            evict_to_l2((const void *) my_stats, 1, 64);
+            WAIT_CACHEOPS;
+
+            // A: team members have all written their partials.
+            et_barrier(ET_BARRIER_SHIRE);
+
+            if (k_split == 0) {
+                // Online softmax merge: fold peers 1..k_splits-1 into our
+                // own (M_running, S_running, acc). For each peer p:
+                //   M_new    = max(M_running, M_p)
+                //   α_own    = exp2((M_running - M_new) * log2e)
+                //   α_p      = exp2((M_p     - M_new) * log2e)
+                //   acc[d]   = α_own * acc[d] + α_p * peer_acc[d]
+                //   S_running = α_own * S_running + α_p * S_p
+                float       M_running = M;
+                float       S_running = S;
+                const float log2e     = 1.4426950408889634f;
+
+                for (int64_t p = 1; p < k_splits; p++) {
+                    uint64_t         peer_scp   = (local_tile_idx * k_splits + p) * SCP_PER_MINION;
+                    volatile float * peer_stats = (volatile float *) et_shire_l2scp_local(peer_scp + SCP_STATS_OFF);
+                    float *          peer_acc   = (float *) et_shire_l2scp_local(peer_scp + SCP_ACC_OFF);
+
+                    // Drop stale L1D copies before reading peer's data.
+                    evict_to_l2((const void *) peer_stats, 1, 64);
+                    evict_range_to_l2(peer_acc, (int64_t) dv * (int64_t) sizeof(float));
+                    WAIT_CACHEOPS;
+
+                    const float M_p = peer_stats[0];
+                    const float S_p = peer_stats[1];
+
+                    const float M_new     = (M_p > M_running) ? M_p : M_running;
+                    const float alpha_own = (M_running == ET_NEG_INF_F) ? 0.0f : et_exp2f((M_running - M_new) * log2e);
+                    const float alpha_p   = (M_p == ET_NEG_INF_F) ? 0.0f : et_exp2f((M_p - M_new) * log2e);
+
+                    merge_rescale_add_asm(acc, peer_acc, dv, alpha_own, alpha_p);
+
+                    S_running = alpha_own * S_running + alpha_p * S_p;
+                    M_running = M_new;
+                }
+
+                const float S_inv = (S_running == 0.0f) ? 0.0f : et_fdiv(1.0f, S_running);
+                normalize_store_vec(out, acc, dv, S_inv, use_fast_store);
+            }
+
+            // B: reducer is done, team may reuse its acc/stats slabs.
+            et_barrier(ET_BARRIER_SHIRE);
+        } else {
+            // k_splits == 1 fast path — this minion owns the full row.
+            const float S_inv = S == 0.0f ? 0.0f : et_fdiv(1.0f, S);
+            normalize_store_vec(out, acc, dv, S_inv, use_fast_store);
+        }
+    }
+
+    FENCE;
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/flash_attn_ext_f32.c b/ggml/src/ggml-et/et-kernels/src/flash_attn_ext_f32.c
new file mode 100644 (file)
index 0000000..93b65b2
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/flash_attn_ext_f32.c
@@ -0,0 +1,217 @@
+//******************************************************************************
+// F32 Flash Attention for ET backend
+//
+// Supports:
+// - arbitrary dk/dv (up to 128)
+// - GQA (n_head_q can differ from n_head_kv)
+// - mask (F16 or F32, causal pattern)
+// - F16 or F32 K and V (with non-contiguous strides from KV cache permute)
+//
+// Limitations:
+// - Q and dst must be F32
+// - no sinks, ALiBi, logit softcap
+//
+// Parallelization strategy:
+// - flatten [query position, head, outer batch] into independent rows
+// - assign rows round-robin across ET threads
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct ggml_et_flash_attn_ext_params {
+    struct ggml_tensor src0;      // Q tensor (F32)
+    struct ggml_tensor src1;      // K tensor (F16 or F32)
+    struct ggml_tensor src2;      // V tensor (F16 or F32)
+    struct ggml_tensor mask;      // mask tensor (F16 or F32), zeroed when absent
+    struct ggml_tensor dst;       // Output tensor (F32)
+    float              scale;     // Scale factor applied to QK
+    int32_t            has_mask;  // nonzero if mask is present
+};
+
+// Maximum head dimension supported (128 covers all common LLMs).
+#define FA_DV_MAX 128
+
+// Read element d from a row, handling F16 or F32 type.
+// row_base points to the start of the row (byte address).
+// nb0 is the stride per element (2 for F16, 4 for F32).
+static inline float read_kv_f32(const char * row_base, int64_t d, int64_t nb0, int type) {
+    if (type == GGML_TYPE_F32) {
+        return *(const float *) (row_base + d * nb0);
+    }
+    // F16
+    return fp16_to_fp32(*(const uint16_t *) (row_base + d * nb0));
+}
+
+// Dot product of F32 query vector with a K row (F16 or F32).
+static inline float dot_qk(const float * q, const char * k_row, int64_t dk, int64_t k_nb0, int k_type) {
+    float acc = 0.0f;
+    if (k_type == GGML_TYPE_F32) {
+        const float * kf = (const float *) k_row;
+        for (int64_t i = 0; i < dk; ++i) {
+            acc += q[i] * kf[i];
+        }
+    } else {
+        // F16 stride-aware read
+        for (int64_t i = 0; i < dk; ++i) {
+            acc += q[i] * fp16_to_fp32(*(const uint16_t *) (k_row + i * k_nb0));
+        }
+    }
+    return acc;
+}
+
+static inline float get_mask_val(const struct ggml_tensor * mask, int64_t iq1, int64_t ik1, int64_t iq2, int64_t iq3) {
+    // mask layout: [nk, nq, ne2, ne3] -> broadcast via modulo
+    const char * base = (const char *) mask->data + iq1 * mask->nb[1] + (iq2 % mask->ne[2]) * mask->nb[2] +
+                        (iq3 % mask->ne[3]) * mask->nb[3];
+
+    if (mask->type == GGML_TYPE_F32) {
+        return *(const float *) (base + ik1 * mask->nb[0]);
+    }
+    // F16
+    return fp16_to_fp32(*(const uint16_t *) (base + ik1 * mask->nb[0]));
+}
+
+int entry_point(struct ggml_et_flash_attn_ext_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env || !params) {
+        return -1;
+    }
+
+    const int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    const int num_threads = get_num_threads(kernel_env->shire_mask);
+    if (thread_id < 0 || num_threads <= 0) {
+        return 0;
+    }
+
+    struct ggml_tensor * q        = &params->src0;
+    struct ggml_tensor * k        = &params->src1;
+    struct ggml_tensor * v        = &params->src2;
+    struct ggml_tensor * dst      = &params->dst;
+    const int32_t        has_mask = params->has_mask;
+    struct ggml_tensor * mask     = has_mask ? &params->mask : (struct ggml_tensor *) 0;
+
+    const char * q_data   = (const char *) q->data;
+    const char * k_data   = (const char *) k->data;
+    const char * v_data   = (const char *) v->data;
+    char *       dst_data = (char *) dst->data;
+
+    const int     k_type = k->type;
+    const int     v_type = v->type;
+    const int64_t k_nb0  = k->nb[0];
+    const int64_t v_nb0  = v->nb[0];
+
+    const int64_t dk  = q->ne[0];  // head dim for keys/queries
+    const int64_t nq  = q->ne[1];  // number of query positions
+    const int64_t nhq = q->ne[2];  // number of query heads
+    const int64_t no  = q->ne[3];  // outer batch
+
+    const int64_t nk  = k->ne[1];  // number of key/value positions
+    const int64_t nhk = k->ne[2];  // number of kv heads
+    const int64_t dv  = v->ne[0];  // head dim for values
+
+    if (dv > FA_DV_MAX) {
+        return -1;
+    }
+
+    // GQA: query heads per kv head
+    const int64_t gqa_ratio = nhq / nhk;
+
+    const int64_t total_rows = nq * nhq * no;
+    const float   scale      = params->scale;
+
+    // When dv is a multiple of 16 (64 bytes = cache line), output rows are
+    // cache-line aligned and we can use fast normal stores. Otherwise we must
+    // use atomic stores to avoid cache-line sharing corruption.
+    const int use_fast_store = (dv % 16 == 0);
+
+    for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+        const int64_t iq3 = row / (nhq * nq);
+        const int64_t rem = row % (nhq * nq);
+        const int64_t iq2 = rem / nq;  // query head index
+        const int64_t iq1 = rem % nq;  // query position
+
+        // Map query head -> kv head for GQA
+        const int64_t ik2 = iq2 / gqa_ratio;
+
+        // Q is always F32
+        const float * pq = (const float *) (q_data + iq1 * q->nb[1] + iq2 * q->nb[2] + iq3 * q->nb[3]);
+
+        // dst layout: [dv, nhq, nq, no]
+        float * out = (float *) (dst_data + iq2 * dst->nb[1] + iq1 * dst->nb[2] + iq3 * dst->nb[3]);
+
+        // Base byte offsets for K and V head+batch slice
+        const int64_t kv_base = ik2 * k->nb[2] + iq3 * k->nb[3];
+        const int64_t vv_base = ik2 * v->nb[2] + iq3 * v->nb[3];
+
+        float acc[FA_DV_MAX];
+        for (int64_t d = 0; d < dv; ++d) {
+            acc[d] = 0.0f;
+        }
+
+        float M = -3.402823466e+38f;
+        float S = 0.0f;
+
+        for (int64_t ik1 = 0; ik1 < nk; ++ik1) {
+            // If mask is present, check for -inf (skip masked positions)
+            float mask_val = 0.0f;
+            if (has_mask) {
+                mask_val = get_mask_val(mask, iq1, ik1, iq2, iq3);
+                // llama.cpp uses -inf for masked positions
+                if (mask_val == -3.402823466e+38f || mask_val != mask_val) {
+                    continue;
+                }
+            }
+
+            const char * pk = k_data + ik1 * k->nb[1] + kv_base;
+            const char * pv = v_data + ik1 * v->nb[1] + vv_base;
+
+            float       s    = dot_qk(pq, pk, dk, k_nb0, k_type) * scale + mask_val;
+            const float Mold = M;
+
+            float ms = 1.0f;
+            float vs = 1.0f;
+            if (s > M) {
+                M  = s;
+                ms = et_expf(Mold - M);
+                for (int64_t d = 0; d < dv; ++d) {
+                    acc[d] *= ms;
+                }
+            } else {
+                vs = et_expf(s - M);
+            }
+
+            // Accumulate weighted V
+            if (v_type == GGML_TYPE_F32) {
+                const float * pvf = (const float *) pv;
+                for (int64_t d = 0; d < dv; ++d) {
+                    acc[d] += pvf[d] * vs;
+                }
+            } else {
+                for (int64_t d = 0; d < dv; ++d) {
+                    acc[d] += fp16_to_fp32(*(const uint16_t *) (pv + d * v_nb0)) * vs;
+                }
+            }
+
+            S = S * ms + vs;
+        }
+
+        const float S_inv = S == 0.0f ? 0.0f : et_fdiv(1.0f, S);
+        if (use_fast_store) {
+            for (int64_t d = 0; d < dv; ++d) {
+                out[d] = acc[d] * S_inv;
+            }
+        } else {
+            for (int64_t d = 0; d < dv; ++d) {
+                atomic_store_f32((volatile float *) &out[d], acc[d] * S_inv);
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/gated_delta_net_f32.c b/ggml/src/ggml-et/et-kernels/src/gated_delta_net_f32.c
new file mode 100644 (file)
index 0000000..c09c774
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/gated_delta_net_f32.c
@@ -0,0 +1,346 @@
+//******************************************************************************
+// Gated Delta Net F32 Kernel
+//
+// Implements the gated delta rule recurrence:
+//   For each head h, timestep t:
+//     1. Gate decay:   S *= exp(g)  (scalar or per-element KDA)
+//     2. Delta update: delta[j] = (v[j] - dot(S_row_j, k)) * beta
+//     3. Outer product: S_row_j += k * delta[j]
+//     4. Attention:    attn[j] = dot(S_row_j, q) * scale
+//
+// State is stored transposed: s_out[j*S_v + i] = S[i][j]
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_gated_delta_net_params {
+    struct ggml_tensor q;         // [S_v, H_q, n_tokens, n_seqs_q]
+    struct ggml_tensor k;         // [S_v, H_k, n_tokens, n_seqs_k]
+    struct ggml_tensor v;         // [S_v, H, n_tokens, n_seqs]
+    struct ggml_tensor g;         // [1 or S_v, H, n_tokens, n_seqs]
+    struct ggml_tensor beta;      // [1, H, n_tokens, n_seqs]
+    struct ggml_tensor state_in;  // [S_v*S_v*H, K, n_seqs]
+    struct ggml_tensor dst;       // [S_v*H, n_tokens*n_seqs + S_v*n_seqs*K]
+    int32_t            S_v;       // head dimension
+    int32_t            H;         // number of value heads
+    int32_t            H_q;       // number of Q heads
+    int32_t            H_k;       // number of K heads
+    int32_t            n_tokens;  // total tokens
+    int32_t            n_seqs;    // number of sequences
+    int32_t            n_seqs_q;  // Q sequence count
+    int32_t            n_seqs_k;  // K sequence count
+    int32_t            kda;       // 1 if per-element gate, 0 if scalar
+    int32_t            K;         // snapshot slot count
+    float              scale;     // 1/sqrt(S_v)
+};
+
+static inline float hsum_f10(void) {
+    float result;
+    __asm__ __volatile__(
+        "fswizz.ps f1, f10, 0xB1 \n\t"
+        "fadd.ps   f2, f10, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result)::"t0", "f1", "f2", "f3", "f4", "f5");
+    return result;
+}
+
+int entry_point(struct ggml_et_gated_delta_net_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    const struct ggml_tensor * q_tsr     = &params->q;
+    const struct ggml_tensor * k_tsr     = &params->k;
+    const struct ggml_tensor * v_tsr     = &params->v;
+    const struct ggml_tensor * g_tsr     = &params->g;
+    const struct ggml_tensor * beta_tsr  = &params->beta;
+    const struct ggml_tensor * state_tsr = &params->state_in;
+    const struct ggml_tensor * dst_tsr   = &params->dst;
+
+    const float * q        = (const float *) q_tsr->data;
+    const float * k        = (const float *) k_tsr->data;
+    const float * v        = (const float *) v_tsr->data;
+    const float * g        = (const float *) g_tsr->data;
+    const float * beta     = (const float *) beta_tsr->data;
+    const float * state_in = (const float *) state_tsr->data;
+    float *       dst_data = (float *) dst_tsr->data;
+
+    const int32_t S_v      = params->S_v;
+    const int32_t H        = params->H;
+    const int32_t H_q      = params->H_q;
+    const int32_t H_k      = params->H_k;
+    const int32_t n_tokens = params->n_tokens;
+    const int32_t n_seqs   = params->n_seqs;
+    const int32_t n_seqs_q = params->n_seqs_q;
+    const int32_t n_seqs_k = params->n_seqs_k;
+    const int32_t kda      = params->kda;
+    const int32_t K        = params->K;
+    const float   scale    = params->scale;
+
+    if (!q || !k || !v || !g || !beta || !state_in || !dst_data) {
+        return -1;
+    }
+
+    // Preserve the original contract for every tensor except q, k, and v, which may be
+    // row-contiguous with strided higher dimensions.
+    if (q_tsr->nb[0] != sizeof(float) || k_tsr->nb[0] != sizeof(float) || v_tsr->nb[0] != sizeof(float) ||
+        g_tsr->nb[0] != sizeof(float) || beta_tsr->nb[0] != sizeof(float) || state_tsr->nb[0] != sizeof(float) ||
+        dst_tsr->nb[0] != sizeof(float)) {
+        return -1;
+    }
+
+    const int32_t attn_elems     = S_v * H * n_tokens * n_seqs;
+    float *       attn_out_base  = dst_data;
+    float *       state_out_base = dst_data + attn_elems;
+
+    const int32_t state_plane_floats  = S_v * S_v * H * n_seqs;
+
+    const int32_t G0 = kda ? S_v : 1;
+
+    const size_t  q_nb1      = q_tsr->nb[1];
+    const size_t  q_nb2      = q_tsr->nb[2];
+    const size_t  q_nb3      = q_tsr->nb[3];
+    const size_t  k_nb1      = k_tsr->nb[1];
+    const size_t  k_nb2      = k_tsr->nb[2];
+    const size_t  k_nb3      = k_tsr->nb[3];
+    const size_t  v_nb1      = v_tsr->nb[1];
+    const size_t  v_nb2      = v_tsr->nb[2];
+    const size_t  v_nb3      = v_tsr->nb[3];
+    const int32_t g_stride_h = G0;
+    const int32_t g_stride_t = G0 * H;
+    const int32_t g_stride_s = G0 * H * n_tokens;
+    const int32_t b_stride_t = H;
+    const int32_t b_stride_s = H * n_tokens;
+
+    float exp_g_buf[128];
+
+    // FP and SIMD share the same register file. Scalar FP needs the default
+    // mask; 8-wide .ps blocks need m0=255. Save once, toggle at boundaries.
+    unsigned long default_mask;
+    __asm__ volatile("mova.x.m %[ms]\n" : [ms] "=r"(default_mask));
+
+    // Parallelize over (j_block, head, seq).  J_BLK must satisfy two separate
+    // cache-line alignment constraints at once:
+    //   (a) State: J_BLK consecutive rows of s_out (each S_v floats) span an
+    //       integer number of cache lines.  For S_v * sizeof(float) >= 64 this
+    //       is trivially any J_BLK >= 1.
+    //   (b) Attention output: each j writes exactly one float into
+    //       attn_ptr[j], which is densely packed.  If J_BLK * sizeof(float) is
+    //       less than a cache line, distinct threads will share a line and
+    //       race on scalar stores — ET's L1 isn't coherent so we lose writes.
+    //
+    // (b) dominates: J_BLK must be at least ET_CACHE_LINE_SIZE_BYTES / 4 so
+    // that each thread owns a whole cache line of attn_ptr.  That's 16 on
+    // ET-SoC-1, and it's also a whole number of state rows for every
+    // S_v >= 1, so (a) is automatically satisfied.
+    const int32_t J_BLK      = ET_CACHE_LINE_SIZE_BYTES / (int32_t) sizeof(float);
+    const int32_t n_j_blocks = (S_v + J_BLK - 1) / J_BLK;
+    const int32_t total_work = n_j_blocks * H * n_seqs;
+
+    for (int32_t ir = thread_id; ir < total_work; ir += num_threads) {
+        const int32_t jb   = ir % n_j_blocks;
+        const int32_t head = (ir / n_j_blocks) % H;
+        const int32_t seq  = ir / (n_j_blocks * H);
+
+        const int32_t j_start = jb * J_BLK;
+        const int32_t j_end   = (j_start + J_BLK < S_v) ? j_start + J_BLK : S_v;
+
+        const int32_t h_q   = head % H_q;
+        const int32_t h_k   = head % H_k;
+        const int32_t seq_q = (n_seqs_q == n_seqs) ? seq : (seq * n_seqs_q / n_seqs);
+        const int32_t seq_k = (n_seqs_k == n_seqs) ? seq : (seq * n_seqs_k / n_seqs);
+
+        const int32_t head_state_off = (seq * H + head) * S_v * S_v;
+        // Live RMW buffer = first snapshot plane (slot 0).
+        float *       s_out          = state_out_base + head_state_off;
+        // Input state: seq `seq`, head `head`.
+        const float * s_in           = state_in + head_state_off;
+
+        // Skip the explicit s_in -> s_out copy. At t=0 pass A/B read through
+        // src_state = s_in; pass B writes the first new row to s_out. From
+        // t=1 onward src_state flips to s_out (read-modify-write in place).
+        const float * src_state = s_in;
+
+        const int32_t attn_stride_t = S_v * H;
+        float *       attn_ptr      = attn_out_base + (seq * n_tokens * H + head) * S_v;
+
+        const float zero = 0.0f;
+
+        for (int32_t t = 0; t < n_tokens; t++) {
+            const float * q_t      = (const float *) ((const char *) q + seq_q * q_nb3 + t * q_nb2 + h_q * q_nb1);
+            const float * k_t      = (const float *) ((const char *) k + seq_k * k_nb3 + t * k_nb2 + h_k * k_nb1);
+            const float * v_t      = (const float *) ((const char *) v + seq * v_nb3 + t * v_nb2 + head * v_nb1);
+            const float * g_t      = g + seq * g_stride_s + t * g_stride_t + head * g_stride_h;
+            const float   beta_val = beta[seq * b_stride_s + t * b_stride_t + head];
+
+            // Precompute per-element gate for the kda path; scalar decay
+            // otherwise. Decay is fused into per-j pass A/B below, not
+            // applied to state in a separate pre-pass.
+            float decay = 0.0f;  // only used when !kda
+            if (kda) {
+                const float log2e = 1.4426950408889634f;
+                __asm__ volatile("mov.m.x m0, x0, 255\n" :::);
+                __asm__ volatile("fbc.ps f20, %[l2e]\n" : : [l2e] "m"(log2e) : "f20");
+                for (int32_t i = 0; i < S_v; i += 8) {
+                    __asm__ volatile(
+                        "flw.ps f10, %[g_vec]\n"
+                        "fmul.ps f10, f10, f20, rne\n"
+                        "fexp.ps f10, f10\n"
+                        "fsw.ps f10, %[out]\n"
+                        : [out] "=m"(*(float (*)[8]) & exp_g_buf[i])
+                        : [g_vec] "m"(*(const float (*)[8]) & g_t[i])
+                        : "f10");
+                }
+                __asm__ volatile("mova.m.x %[ms]\n" : : [ms] "r"(default_mask));
+            } else {
+                decay = et_expf(g_t[0]);
+            }
+
+            for (int32_t j = j_start; j < j_end; j++) {
+                const float * src_row = src_state + j * S_v;
+                float *       dst_row = s_out + j * S_v;
+
+                __asm__ volatile("mov.m.x m0, x0, 255\n" :::);
+                if (kda) {
+                    __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+                    for (int32_t i = 0; i < S_v; i += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[s_vec]\n"
+                            "flw.ps f12, %[g_vec]\n"
+                            "flw.ps f13, %[k_vec]\n"
+                            "fmul.ps f11, f11, f12\n"        // row_dec = row * g
+                            "fmadd.ps f10, f11, f13, f10\n"  // acc += row_dec * k
+                            :
+                            : [s_vec] "m"(*(const float (*)[8]) & src_row[i]),
+                              [g_vec] "m"(*(const float (*)[8]) & exp_g_buf[i]),
+                              [k_vec] "m"(*(const float (*)[8]) & k_t[i])
+                            : "f10", "f11", "f12", "f13");
+                    }
+                } else {
+                    __asm__ volatile(
+                        "fbc.ps f10, %[z]\n"
+                        "fbc.ps f22, %[d]\n"
+                        :
+                        : [z] "m"(zero), [d] "m"(decay)
+                        : "f10", "f22");
+                    for (int32_t i = 0; i < S_v; i += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[s_vec]\n"
+                            "flw.ps f13, %[k_vec]\n"
+                            "fmul.ps f11, f11, f22\n"        // row_dec = row * decay
+                            "fmadd.ps f10, f11, f13, f10\n"  // acc += row_dec * k
+                            :
+                            : [s_vec] "m"(*(const float (*)[8]) & src_row[i]), [k_vec] "m"(*(const float (*)[8]) &
+                                                                                           k_t[i])
+                            : "f10", "f11", "f13");
+                    }
+                }
+
+                float dot_sk = hsum_f10();
+                __asm__ volatile("mova.m.x %[ms]\n" : : [ms] "r"(default_mask));
+
+                float delta_j = (v_t[j] - dot_sk) * beta_val;
+
+                // -------- Pass B: decay + outer product + attn --------
+                __asm__ volatile("mov.m.x m0, x0, 255\n" :::);
+                if (kda) {
+                    __asm__ volatile(
+                        "fbc.ps f10, %[z]\n"
+                        "fbc.ps f21, %[dj]\n"
+                        :
+                        : [z] "m"(zero), [dj] "m"(delta_j)
+                        : "f10", "f21");
+                    for (int32_t i = 0; i < S_v; i += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[s_vec]\n"
+                            "flw.ps f12, %[g_vec]\n"
+                            "flw.ps f13, %[k_vec]\n"
+                            "flw.ps f14, %[q_vec]\n"
+                            "fmul.ps f11, f11, f12\n"        // row_dec = row * g
+                            "fmadd.ps f11, f13, f21, f11\n"  // row_new = row_dec + k*delta_j
+                            "fsw.ps f11, %[s_out]\n"
+                            "fmadd.ps f10, f11, f14, f10\n"  // attn_acc += row_new * q
+                            : [s_out] "=m"(*(float (*)[8]) & dst_row[i])
+                            : [s_vec] "m"(*(const float (*)[8]) & src_row[i]),
+                              [g_vec] "m"(*(const float (*)[8]) & exp_g_buf[i]),
+                              [k_vec] "m"(*(const float (*)[8]) & k_t[i]), [q_vec] "m"(*(const float (*)[8]) & q_t[i])
+                            : "f10", "f11", "f12", "f13", "f14");
+                    }
+                } else {
+                    __asm__ volatile(
+                        "fbc.ps f10, %[z]\n"
+                        "fbc.ps f21, %[dj]\n"
+                        "fbc.ps f22, %[d]\n"
+                        :
+                        : [z] "m"(zero), [dj] "m"(delta_j), [d] "m"(decay)
+                        : "f10", "f21", "f22");
+                    for (int32_t i = 0; i < S_v; i += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[s_vec]\n"
+                            "flw.ps f13, %[k_vec]\n"
+                            "flw.ps f14, %[q_vec]\n"
+                            "fmul.ps f11, f11, f22\n"        // row_dec = row * decay
+                            "fmadd.ps f11, f13, f21, f11\n"  // row_new = row_dec + k*delta_j
+                            "fsw.ps f11, %[s_out]\n"
+                            "fmadd.ps f10, f11, f14, f10\n"  // attn_acc += row_new * q
+                            : [s_out] "=m"(*(float (*)[8]) & dst_row[i])
+                            : [s_vec] "m"(*(const float (*)[8]) & src_row[i]),
+                              [k_vec] "m"(*(const float (*)[8]) & k_t[i]), [q_vec] "m"(*(const float (*)[8]) & q_t[i])
+                            : "f10", "f11", "f13", "f14");
+                    }
+                }
+
+                float attn_val = hsum_f10();
+                __asm__ volatile("mova.m.x %[ms]\n" : : [ms] "r"(default_mask));
+
+                attn_ptr[j] = attn_val * scale;
+            }
+
+            // n-way merge snapshot: live state lives in slot 0 (== s_out).
+            // Copies state to target snapshot slots [1, K-1] in reverse chronological order.
+            // target_slot == 0 is the live buffer itself => no copy.
+            // target_slot >= K (when n_tokens > K) => older slots are discarded.
+            if (K > 1) {
+                const int32_t target_slot = (n_tokens - 1) - t;
+                if (target_slot > 0 && target_slot < K) {
+                    float * snap = state_out_base + target_slot * state_plane_floats + head_state_off;
+                    for (int32_t j = j_start; j < j_end; j++) {
+                        const float * src = s_out + j * S_v;
+                        float *       dst = snap + j * S_v;
+                        for (int32_t i = 0; i < S_v; i++) {
+                            dst[i] = src[i];
+                        }
+                    }
+                }
+            }
+
+            // After t=0, state lives in s_out; flip src_state so subsequent
+            // timesteps read-modify-write in place.
+            src_state = s_out;
+            attn_ptr += attn_stride_t;
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/get_rows_f32.c b/ggml/src/ggml-et/et-kernels/src/get_rows_f32.c
new file mode 100644 (file)
index 0000000..701f1db
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/get_rows_f32.c
@@ -0,0 +1,612 @@
+//******************************************************************************
+// Bare Metal GET_ROWS F32 Kernel
+// Extracts specific rows from a source tensor based on row indices
+//
+// Algorithm:
+// 1. Read row indices from src1 (int32 tensor)
+// 2. For each index, extract the corresponding row from src0
+// 3. Copy the row data to the output tensor dst
+// 4. Handle different input types: F32, Q8_0, Q4_0, and Q4_K (quantized)
+//
+// Operation: dst[i] = src0[indices[i]] for i = 0..num_indices
+//
+// Features supported:
+// - F32 input data (direct copy)
+// - Q4_0 quantized input data (dequantized to F32)
+// - Q8_0 quantized input data (dequantized to F32)
+// - Q4_K quantized input data (dequantized to F32)
+// - Int32 row indices
+// - Multi-dimensional tensor support
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CACHE_LINE_SIZE_BYTES 64
+
+struct ggml_et_get_rows_params {
+    struct ggml_tensor src0;  // Data tensor (F32, Q4_0, Q8_0, or Q4_K)
+    struct ggml_tensor src1;  // Row indices tensor (I32)
+    struct ggml_tensor dst;   // Output tensor (F32)
+};
+
+#define CACHE_LINE_SIZE_BYTES     64
+#define CACHE_ELEMENTS(elem_size) (CACHE_LINE_SIZE_BYTES / (elem_size))
+
+// Copy a row of F32 data from source to destination
+static void copy_f32_row(float * dst, const float * src, int64_t num_elements) {
+    // Simple memcpy for F32 data - no conversion needed
+    for (int64_t i = 0; i < num_elements; i++) {
+        dst[i] = src[i];
+    }
+}
+
+static void copy_f16_row(float * dst, const uint16_t * src, int64_t num_elements) {
+    for (int64_t i = 0; i < num_elements; i++) {
+        dst[i] = fp16_to_fp32(src[i]);
+    }
+}
+
+// Copy a row of F32 data from source to destination, aligned to cache line boundaries
+// using FP32 load/store instructions. They don't perform data conversion so is fine.
+// Requirement: n_bytes is a multiple of CACHE_LINE_SIZE (64 bytes)
+static void copy_row_cache_align(float * dst, const float * src, int64_t n_bytes) {
+    int num_f32_elem = n_bytes / sizeof(float);
+
+    // Unrolled to do an entire cache line at a time
+    __asm__ volatile(
+        "1: \n\t"
+        // --- Process 64 Bytes (1 Cache Line) ---
+        // Load 256 bits (32 bytes) into f0 and the other into f1
+        "flq2 f0, 0(%[src]) \n\t"
+        "flq2 f1, 32(%[src]) \n\t"
+
+        // Store 256 bits (32 bytes) from f0 and f1
+        "fsq2 f0, 0(%[dst]) \n\t"
+        "fsq2 f1, 32(%[dst]) \n\t"
+
+        // Increment Pointers by 64 bytes
+        "addi %[src], %[src], 64 \n\t"
+        "addi %[dst], %[dst], 64 \n\t"
+
+        // Decrement count by 16 elements
+        "addi %[n], %[n], -16 \n\t"
+
+        // Loop if at least 16 elements remain
+        "bge %[n], %[stride_count], 1b \n\t"
+
+        : [dst] "+r"(dst), [src] "+r"(src), [n] "+r"(num_f32_elem)
+        : [stride_count] "r"(16L)
+        : "f0", "f1", "memory");
+}
+
+// Copied from GGML: copy a row of Q4_0 data to F32 destination (with dequantization)
+static void copy_q4_0_row(float * dst, const block_q4_0 * src_blocks, int64_t num_elements) {
+    const int64_t num_blocks = (num_elements + QK4_0 - 1) / QK4_0;
+
+    for (int64_t block_idx = 0; block_idx < num_blocks; block_idx++) {
+        const int64_t elements_in_block = (block_idx == num_blocks - 1) ? (num_elements - block_idx * QK4_0) : QK4_0;
+
+        float temp_buffer[QK4_0];
+        dequantize_q4_0_block(&src_blocks[block_idx], temp_buffer);
+
+        for (int64_t i = 0; i < elements_in_block; i++) {
+            dst[block_idx * QK4_0 + i] = temp_buffer[i];
+        }
+    }
+}
+
+// Copy a row of Q8_0 data to F32 destination (with dequantization)
+static void copy_q8_0_row(float * dst, const block_q8_0 * src_blocks, int64_t num_elements) {
+    // Number of Q8_0 blocks needed for this row
+    const int64_t num_blocks = (num_elements + QK8_0 - 1) / QK8_0;  // Round up to handle partial blocks
+
+    for (int64_t block_idx = 0; block_idx < num_blocks; block_idx++) {
+        const int64_t elements_in_block =
+            (block_idx == num_blocks - 1) ? (num_elements - block_idx * QK8_0) : QK8_0;  // Handle last partial block
+
+        // Dequantize the block
+        float temp_buffer[QK8_0];
+        dequantize_q8_0_block(&src_blocks[block_idx], temp_buffer);
+
+        // Copy dequantized values to destination
+        for (int64_t i = 0; i < elements_in_block; i++) {
+            dst[block_idx * QK8_0 + i] = temp_buffer[i];
+        }
+    }
+}
+
+// Copy a row of Q4_K data to F32 destination (with dequantization)
+static void copy_q4_K_row(float * dst, const block_q4_K * src_blocks, int64_t num_elements) {
+    const int64_t num_blocks = (num_elements + QK_K - 1) / QK_K;
+
+    for (int64_t block_idx = 0; block_idx < num_blocks; block_idx++) {
+        const int64_t elements_in_block = (block_idx == num_blocks - 1) ? (num_elements - block_idx * QK_K) : QK_K;
+
+        float temp_buffer[QK_K];
+        dequantize_q4_K_block(&src_blocks[block_idx], temp_buffer);
+
+        for (int64_t i = 0; i < elements_in_block; i++) {
+            dst[block_idx * QK_K + i] = temp_buffer[i];
+        }
+    }
+}
+
+static void dequantize_q8_0_block_cache_aligned(const block_q8_0 * block, float * dst) {
+    const int8_t * qs_ptr = block->qs;
+
+    uint64_t temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+
+    const int32_t __attribute__((aligned(32))) vec_indices[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+    float                                      scale          = fp16_to_fp32(block->d);
+    __asm__ volatile(
+        "fbcx.ps     f0, %0       \n\t"  // Broadcast integer scale to all lanes
+        "flq2        f1, 0(%1)    \n\t"  // Load gether indicies
+        ::"r"(scale),
+        "r"(vec_indices)
+        : "f0", "f1");
+
+    for (int i = 0; i < 4; i++) {
+        __asm__ volatile(
+            "fgb.ps      f2, f1(%0)   \n\t"  // Loads 8 bytes from (qs_ptr + indices) and sign-extends to 32-bit int.
+            "fcvt.ps.pw  f2, f2, rne  \n\t"  // Convert Int32 to Float32
+            "fmul.ps     f2, f2, f0   \n\t"  // f2 = f2 * f0 (scale)
+            "fsq2        f2, 0(%1)    \n\t"  // Store 256 bits (8 floats) to dst.
+
+            ::"r"(qs_ptr),
+            "r"(dst)
+            : "f2", "memory");
+
+        // Advance pointers in C
+        qs_ptr += 8;
+        dst += 8;
+    }
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+}
+
+// Copy a row of Q4_0 data to F32 destination (with dequantization), cache-aligned
+static void copy_q4_0_row_cache_aligned(float * dst, const block_q4_0 * src_blocks, int64_t num_elements) {
+    const int64_t num_blocks = (num_elements + QK4_0 - 1) / QK4_0;
+
+    // Scatter byte offsets: even lanes -> dst[j], odd lanes -> dst[j + QK4_0/2]
+    // For 4 consecutive packed bytes producing [low0, high0, low1, high1, low2, high2, low3, high3]:
+    //   low_i  -> byte offset i*4       (positions 0,1,2,3 in first half)
+    //   high_i -> byte offset (16+i)*4  (positions 16,17,18,19 in second half)
+    const int32_t __attribute__((aligned(32))) scatter_offsets[8] = { 0 * 4, 16 * 4, 1 * 4, 17 * 4,
+                                                                      2 * 4, 18 * 4, 3 * 4, 19 * 4 };
+
+    // Gather indices: each byte loaded twice for low/high nibble extraction
+    const int32_t __attribute__((aligned(32))) gather_indices[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
+
+    uint64_t temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+
+    // Load constant vectors once — shared across all blocks and iterations
+    __asm__ volatile(
+        "flq2        f4, 0(%0)    \n\t"  // f4 = scatter offsets
+        "flq2        f1, 0(%1)    \n\t"  // f1 = gather indices {0,0,1,1,2,2,3,3}
+        ::"r"(scatter_offsets),
+        "r"(gather_indices)
+        : "f1", "f4");
+
+    for (int64_t block_idx = 0; block_idx < num_blocks; block_idx++) {
+        const block_q4_0 * block     = &src_blocks[block_idx];
+        const uint8_t *    qs        = block->qs;
+        float *            block_dst = dst + block_idx * QK4_0;
+
+        float scale = fp16_to_fp32(block->d);
+        float bias  = -8.0f * scale;
+
+        // Per-block: broadcast scale and bias
+        __asm__ volatile(
+            "fbcx.ps     f0, %0       \n\t"  // f0 = broadcast(scale)
+            "fbcx.ps     f3, %1       \n\t"  // f3 = broadcast(-8 * scale)
+            ::"r"(scale),
+            "r"(bias)
+            : "f0", "f3");
+
+        // 4 iterations x 4 packed bytes = 16 bytes = full block -> 32 floats
+        for (int i = 0; i < 4; i++) {
+            __asm__ volatile(
+                "fgb.ps      f2, f1(%0)    \n\t"  // Gather: [b0,b0,b1,b1,b2,b2,b3,b3]
+                "mov.m.x     m0, x0, 0xAA  \n\t"  // Odd lanes only (fills gather latency)
+                "fsrli.pi    f2, f2, 4     \n\t"  // Odd lanes: byte >> 4 (high nibble)
+                "mov.m.x     m0, x0, 0xFF  \n\t"  // Restore full mask
+                "fslli.pi    f2, f2, 28    \n\t"  // Isolate low 4 bits: shift left 28
+                "fsrli.pi    f2, f2, 28    \n\t"  //   then right 28 -> nibble in [3:0]
+                "fcvt.ps.pw  f2, f2, rne   \n\t"  // Int32 -> Float32
+                "fmul.ps     f2, f2, f0    \n\t"  // * scale
+                "fadd.ps     f2, f2, f3    \n\t"  // + bias -> (nibble - 8) * scale
+                "fscw.ps     f2, f4(%1)    \n\t"  // Scatter to GGML positions
+
+                ::"r"(qs),
+                "r"(block_dst)
+                : "f2", "memory");
+
+            qs += 4;         // 4 packed bytes consumed
+            block_dst += 4;  // Advance base by 4 float positions
+        }
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));  // Restore mask
+}
+
+// Copy a row of Q8_0 data to F32 destination (with dequantization)
+static void copy_q8_0_row_cache_aligned(float * dst, const block_q8_0 * src_blocks, int64_t num_elements) {
+    // Number of Q8_0 blocks needed for this row
+    const int64_t num_blocks = (num_elements + QK8_0 - 1) / QK8_0;  // Round up to handle partial blocks
+
+    for (int64_t block_idx = 0; block_idx < num_blocks; block_idx++) {
+        const int64_t elements_in_block =
+            (block_idx == num_blocks - 1) ? (num_elements - block_idx * QK8_0) : QK8_0;  // Handle last partial block
+
+        // Dequantize the block
+        float temp_buffer[QK8_0];
+        dequantize_q8_0_block_cache_aligned(&src_blocks[block_idx], temp_buffer);
+
+        // Copy dequantized values to destination
+        for (int64_t i = 0; i < elements_in_block; i++) {
+            dst[block_idx * QK8_0 + i] = temp_buffer[i];
+        }
+    }
+}
+
+// Vectorized dequantization of a Q4_K super-block (256 elements) to F32
+// Processes 8 groups of 32 elements, using ET SIMD for the inner loops.
+// Output is sequential (no scatter needed unlike Q4_0).
+static void copy_q4_K_row_cache_aligned(float * dst, const block_q4_K * src_blocks, int64_t num_elements) {
+    const int64_t num_blocks = (num_elements + QK_K - 1) / QK_K;
+
+    // Gather indices for sequential byte access: {0,1,2,3,4,5,6,7}
+    const int32_t __attribute__((aligned(32))) gather_indices[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+    uint64_t temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+
+    // Load gather indices once — shared across all blocks
+    __asm__ volatile("flq2        f1, 0(%0)    \n\t"  // f1 = gather indices {0,1,2,3,4,5,6,7}
+                     ::"r"(gather_indices)
+                     : "f1");
+
+    for (int64_t block_idx = 0; block_idx < num_blocks; block_idx++) {
+        const block_q4_K * block     = &src_blocks[block_idx];
+        const uint8_t *    qs        = block->qs;
+        float *            block_dst = dst + block_idx * QK_K;
+
+        const float d   = fp16_to_fp32(block->d);
+        const float min = fp16_to_fp32(block->dmin);
+
+        int is = 0;
+        for (int j = 0; j < QK_K; j += 64) {
+            // Extract per-group scales and mins (scalar — only 8 pairs per super-block)
+            uint8_t sc, m;
+            get_scale_min_k4(is + 0, block->scales, &sc, &m);
+            const float d1     = d * sc;
+            const float neg_m1 = -(min * m);
+            get_scale_min_k4(is + 1, block->scales, &sc, &m);
+            const float d2     = d * sc;
+            const float neg_m2 = -(min * m);
+
+            // Low nibbles: 32 elements using d1, neg_m1
+            __asm__ volatile(
+                "fbcx.ps     f0, %0       \n\t"  // f0 = broadcast(d1)
+                "fbcx.ps     f3, %1       \n\t"  // f3 = broadcast(-m1)
+                ::"r"(d1),
+                "r"(neg_m1)
+                : "f0", "f3");
+
+            const uint8_t * qs_lo  = qs;
+            float *         dst_lo = block_dst + j;
+            for (int k = 0; k < 4; k++) {
+                __asm__ volatile(
+                    "fgb.ps      f2, f1(%0)   \n\t"   // Gather 8 bytes, sign-extend to int32
+                    "fandi.pi    f2, f2, 0xF   \n\t"  // Mask low nibble (imm10=15)
+                    "fcvt.ps.pw  f2, f2, rne   \n\t"  // Int32 -> Float32
+                    "fmadd.ps    f2, f2, f0, f3\n\t"  // d1 * nibble + (-m1)
+                    "fsq2        f2, 0(%1)     \n\t"  // Store 8 floats
+                    ::"r"(qs_lo),
+                    "r"(dst_lo)
+                    : "f2", "memory");
+                qs_lo += 8;
+                dst_lo += 8;
+            }
+
+            // High nibbles: 32 elements using d2, neg_m2
+            __asm__ volatile(
+                "fbcx.ps     f0, %0       \n\t"  // f0 = broadcast(d2)
+                "fbcx.ps     f3, %1       \n\t"  // f3 = broadcast(-m2)
+                ::"r"(d2),
+                "r"(neg_m2)
+                : "f0", "f3");
+
+            const uint8_t * qs_hi  = qs;
+            float *         dst_hi = block_dst + j + 32;
+            for (int k = 0; k < 4; k++) {
+                __asm__ volatile(
+                    "fgb.ps      f2, f1(%0)   \n\t"   // Gather 8 bytes, sign-extend to int32
+                    "fsrli.pi    f2, f2, 4     \n\t"  // Shift right 4: high nibble
+                    "fandi.pi    f2, f2, 0xF   \n\t"  // Mask to 4 bits (clean any sign-ext artifacts)
+                    "fcvt.ps.pw  f2, f2, rne   \n\t"  // Int32 -> Float32
+                    "fmadd.ps    f2, f2, f0, f3\n\t"  // d2 * nibble + (-m2)
+                    "fsq2        f2, 0(%1)     \n\t"  // Store 8 floats
+                    ::"r"(qs_hi),
+                    "r"(dst_hi)
+                    : "f2", "memory");
+                qs_hi += 8;
+                dst_hi += 8;
+            }
+
+            qs += 32;  // Advance to next 32 packed bytes
+            is += 2;
+        }
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));  // Restore mask
+}
+
+// Determine the number of F32 elements per work unit for a given source type.
+// For F32: 1 cacheline (16 elements)
+// For quantized types: 1 quant block
+static int64_t get_elements_per_work_unit(int type) {
+    const int64_t elements_per_cacheline = CACHE_LINE_SIZE_BYTES / sizeof(float);  // 16
+    switch (type) {
+        case GGML_TYPE_Q8_0:
+            return QK8_0;                   // 32 elements = 2 cachelines
+        case GGML_TYPE_Q4_0:
+            return QK4_0;                   // 32 elements = 2 cachelines
+        case GGML_TYPE_Q4_K:
+            return QK_K;                    // 256 elements = 16 cachelines
+        default:
+            return elements_per_cacheline;  // 16 elements = 1 cacheline
+    }
+}
+
+static int get_row_f32_mc_cacheline_aligned(struct ggml_et_get_rows_params * params, void * env) {
+    kernel_environment_t * kernel_env  = (kernel_environment_t *) env;
+    int                    thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int                    num_threads = get_num_threads(kernel_env->shire_mask);
+
+    struct ggml_tensor * src0 = &params->src0;  // Data tensor
+    struct ggml_tensor * src1 = &params->src1;  // Row indices tensor (I32)
+    struct ggml_tensor * dst  = &params->dst;   // Output tensor (F32)
+
+    const int64_t ne00 = src0->ne[0];           // Source columns (row width)
+    const int64_t ne01 = src0->ne[1];           // Source rows (total available rows)
+    const int64_t ne02 = src0->ne[2];           // Source batch dimension
+    const int64_t ne03 = src0->ne[3];           // Source outer batch dimension
+
+    const int64_t ne10 = src1->ne[0];           // Number of indices in dimension 0
+    const int64_t ne11 = src1->ne[1];           // Number of indices in dimension 1
+    const int64_t ne12 = src1->ne[2];           // Batch dimension for indices
+    const int64_t ne13 = src1->ne[3];           // Outer batch dimension for indices
+
+    const int64_t total_rows_to_extract = ne10 * ne11 * ne12 * ne13;
+
+    // Determine work unit size based on source type
+    const int64_t elements_per_wu = get_elements_per_work_unit(src0->type);
+    const int64_t wus_per_row     = ne00 / elements_per_wu;
+    const int64_t total_wus       = total_rows_to_extract * wus_per_row;
+
+    // Distribute work units across threads (contiguous ranges)
+    const int64_t wus_per_thread = (total_wus + num_threads - 1) / num_threads;
+    const int64_t wu_start       = thread_id * wus_per_thread;
+    int64_t       wu_end         = wu_start + wus_per_thread;
+    if (wu_end > total_wus) {
+        wu_end = total_wus;
+    }
+
+    void *    src0_data = src0->data;
+    int32_t * src1_data = (int32_t *) src1->data;
+    float *   dst_data  = (float *) dst->data;
+
+    int64_t wu = wu_start;
+    while (wu < wu_end) {
+        // Determine which row this work unit belongs to and offset within row
+        const int64_t row_idx   = wu / wus_per_row;
+        const int64_t wu_in_row = wu % wus_per_row;
+
+        // How many work units to process in this row (batch contiguous WUs in same row)
+        int64_t wus_remaining_in_row = wus_per_row - wu_in_row;
+        int64_t wus_to_process       = wu_end - wu;
+        if (wus_remaining_in_row < wus_to_process) {
+            wus_to_process = wus_remaining_in_row;
+        }
+
+        // Calculate multi-dimensional index for this row
+        const int64_t i       = row_idx;
+        const int64_t i13_idx = i / (ne12 * ne11 * ne10);
+        const int64_t i12_idx = (i - i13_idx * ne12 * ne11 * ne10) / (ne11 * ne10);
+        const int64_t i11_idx = (i - i13_idx * ne12 * ne11 * ne10 - i12_idx * ne11 * ne10) / ne10;
+        const int64_t i10_idx = i - i13_idx * ne12 * ne11 * ne10 - i12_idx * ne11 * ne10 - i11_idx * ne10;
+
+        // Get the row index from src1
+        const int64_t index_offset = i13_idx * ne12 * ne11 * ne10 + i12_idx * ne11 * ne10 + i11_idx * ne10 + i10_idx;
+        const int32_t row_index    = src1_data[index_offset];
+
+        if (row_index < 0 || row_index >= ne01) {
+            return -1;  // Index out of bounds
+        }
+
+        const int64_t batch_offset =
+            i11_idx * ne01 * ne00 + i12_idx * ne02 * ne01 * ne00 + i13_idx * ne03 * ne02 * ne01 * ne00;
+
+        const int64_t elem_offset_in_row = wu_in_row * elements_per_wu;
+        const int64_t num_elements       = wus_to_process * elements_per_wu;
+
+        float * dst_row = dst_data + row_idx * ne00 + elem_offset_in_row;
+
+        if (src0->type == GGML_TYPE_F32) {
+            // F32 source: direct copy of cacheline-aligned chunk
+            const float * src_row = (const float *) src0_data + row_index * ne00 + batch_offset + elem_offset_in_row;
+            copy_row_cache_align(dst_row, src_row, num_elements * sizeof(float));
+        } else if (src0->type == GGML_TYPE_F16) {
+            // F16 source: scalar conversion over a destination-aligned write chunk.
+            const uint16_t * src_row =
+                (const uint16_t *) src0_data + row_index * ne00 + batch_offset + elem_offset_in_row;
+            copy_f16_row(dst_row, src_row, num_elements);
+        } else if (src0->type == GGML_TYPE_Q8_0) {
+            // Q8_0 source: dequantize work-unit-aligned blocks
+            const int64_t      blocks_per_row   = (ne00 + QK8_0 - 1) / QK8_0;
+            const int64_t      src_block_offset = (row_index * blocks_per_row) + (batch_offset / ne00) * blocks_per_row;
+            const int64_t      block_start      = elem_offset_in_row / QK8_0;
+            const block_q8_0 * src_blocks       = (const block_q8_0 *) src0_data + src_block_offset + block_start;
+            copy_q8_0_row_cache_aligned(dst_row, src_blocks, num_elements);
+        } else if (src0->type == GGML_TYPE_Q4_0) {
+            // Q4_0 source: dequantize work-unit-aligned blocks
+            const int64_t      blocks_per_row   = (ne00 + QK4_0 - 1) / QK4_0;
+            const int64_t      src_block_offset = (row_index * blocks_per_row) + (batch_offset / ne00) * blocks_per_row;
+            const int64_t      block_start      = elem_offset_in_row / QK4_0;
+            const block_q4_0 * src_blocks       = (const block_q4_0 *) src0_data + src_block_offset + block_start;
+            copy_q4_0_row_cache_aligned(dst_row, src_blocks, num_elements);
+        } else if (src0->type == GGML_TYPE_Q4_K) {
+            // Q4_K source: dequantize work-unit-aligned blocks
+            const int64_t      blocks_per_row   = (ne00 + QK_K - 1) / QK_K;
+            const int64_t      src_block_offset = (row_index * blocks_per_row) + (batch_offset / ne00) * blocks_per_row;
+            const int64_t      block_start      = elem_offset_in_row / QK_K;
+            const block_q4_K * src_blocks       = (const block_q4_K *) src0_data + src_block_offset + block_start;
+            copy_q4_K_row_cache_aligned(dst_row, src_blocks, num_elements);
+        }
+
+        wu += wus_to_process;
+    }
+
+    return 0;
+}
+
+static inline size_t tensor_bytes(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+int entry_point(struct ggml_et_get_rows_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+    if (!kernel_env) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;  // Data tensor (F32, Q4_0, Q8_0, or Q4_K)
+    struct ggml_tensor * src1 = &params->src1;  // Row indices tensor (I32)
+    struct ggml_tensor * dst  = &params->dst;   // Output tensor (F32)
+
+    // Fast path - we know how to deal with them multi-core
+    if ((src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_Q8_0 ||
+         src0->type == GGML_TYPE_Q4_0 || src0->type == GGML_TYPE_Q4_K) &&
+        src1->type == GGML_TYPE_I32 && dst->type == GGML_TYPE_F32 && dst->ne[0] % CACHE_ELEMENTS(sizeof(float)) == 0) {
+        return get_row_f32_mc_cacheline_aligned(params, env);
+    }
+
+    int thread_id = get_relative_thread_id(kernel_env->shire_mask);
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (thread_id != 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    if (dst->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_I32) {
+        return -1;  // Invalid output or index type
+    }
+
+    if (src0->type != GGML_TYPE_F32 && src0->type != GGML_TYPE_F16 && src0->type != GGML_TYPE_Q8_0 &&
+        src0->type != GGML_TYPE_Q4_0 && src0->type != GGML_TYPE_Q4_K) {
+        return -1;  // Unsupported input type
+    }
+
+    void *    src0_data = src0->data;
+    int32_t * src1_data = (int32_t *) src1->data;
+    float *   dst_data  = (float *) dst->data;
+#ifdef ET_UBERKERNEL
+    evict_region_past_l2(src0_data, tensor_bytes(src0));
+    evict_region_past_l2(src1_data, tensor_bytes(src1));
+    evict_region_past_l2(dst_data, tensor_bytes(dst));
+#endif
+
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    const int64_t ne00 = src0->ne[0];  // Source columns (row width)
+    const int64_t ne01 = src0->ne[1];  // Source rows (total available rows)
+    const int64_t ne02 = src0->ne[2];  // Source batch dimension
+    const int64_t ne03 = src0->ne[3];  // Source outer batch dimension
+
+    const int64_t ne10 = src1->ne[0];  // Number of indices in dimension 0
+    const int64_t ne11 = src1->ne[1];  // Number of indices in dimension 1
+    const int64_t ne12 = src1->ne[2];  // Batch dimension for indices
+    const int64_t ne13 = src1->ne[3];  // Outer batch dimension for indices
+
+    const int64_t total_rows_to_extract = ne10 * ne11 * ne12 * ne13;
+#ifdef ET_UBERKERNEL
+    et_barrier(ET_BARRIER_GLOBAL);
+#endif
+    // Naive single-threaded implementation - process all rows sequentially
+    // XXX: Do we really need a single-threaded implementation?
+    for (int64_t i = 0; i < total_rows_to_extract; i++) {
+        // Calculate multi-dimensional index for the current output position
+        const int64_t i13_idx = i / (ne12 * ne11 * ne10);
+        const int64_t i12_idx = (i - i13_idx * ne12 * ne11 * ne10) / (ne11 * ne10);
+        const int64_t i11_idx = (i - i13_idx * ne12 * ne11 * ne10 - i12_idx * ne11 * ne10) / ne10;
+        const int64_t i10_idx = i - i13_idx * ne12 * ne11 * ne10 - i12_idx * ne11 * ne10 - i11_idx * ne10;
+
+        // Get the row index from src1
+        const int64_t index_offset = i13_idx * ne12 * ne11 * ne10 + i12_idx * ne11 * ne10 + i11_idx * ne10 + i10_idx;
+        const int32_t row_index    = src1_data[index_offset];
+
+        if (row_index < 0 || row_index >= ne01) {
+            return -1;  // Index out of bounds
+        }
+
+        const int64_t batch_offset =
+            i11_idx * ne01 * ne00 + i12_idx * ne02 * ne01 * ne00 + i13_idx * ne03 * ne02 * ne01 * ne00;
+
+        const int64_t dst_offset = i;
+
+        if (src0->type == GGML_TYPE_F32) {
+            // F32 source: direct copy
+            const float * src_row = (const float *) src0_data + row_index * ne00 + batch_offset;
+            float *       dst_row = dst_data + dst_offset * ne00;
+            copy_f32_row(dst_row, src_row, ne00);
+        } else if (src0->type == GGML_TYPE_F16) {
+            // F16 source: scalar conversion
+            const uint16_t * src_row = (const uint16_t *) src0_data + row_index * ne00 + batch_offset;
+            float *          dst_row = dst_data + dst_offset * ne00;
+            copy_f16_row(dst_row, src_row, ne00);
+        } else if (src0->type == GGML_TYPE_Q8_0) {
+            // Q8_0 source: dequantize while copying
+            const int64_t      blocks_per_row   = (ne00 + QK8_0 - 1) / QK8_0;
+            const int64_t      src_block_offset = (row_index * blocks_per_row) + (batch_offset / ne00) * blocks_per_row;
+            const block_q8_0 * src_blocks       = (const block_q8_0 *) src0_data + src_block_offset;
+            float *            dst_row          = dst_data + dst_offset * ne00;
+            copy_q8_0_row(dst_row, src_blocks, ne00);
+        } else if (src0->type == GGML_TYPE_Q4_0) {
+            // Q4_0 source: dequantize while copying
+            const int64_t      blocks_per_row   = (ne00 + QK4_0 - 1) / QK4_0;
+            const int64_t      src_block_offset = (row_index * blocks_per_row) + (batch_offset / ne00) * blocks_per_row;
+            const block_q4_0 * src_blocks       = (const block_q4_0 *) src0_data + src_block_offset;
+            float *            dst_row          = dst_data + dst_offset * ne00;
+            copy_q4_0_row(dst_row, src_blocks, ne00);
+        } else if (src0->type == GGML_TYPE_Q4_K) {
+            // Q4_K source: dequantize while copying
+            const int64_t      blocks_per_row   = (ne00 + QK_K - 1) / QK_K;
+            const int64_t      src_block_offset = (row_index * blocks_per_row) + (batch_offset / ne00) * blocks_per_row;
+            const block_q4_K * src_blocks       = (const block_q4_K *) src0_data + src_block_offset;
+            float *            dst_row          = dst_data + dst_offset * ne00;
+            copy_q4_K_row(dst_row, src_blocks, ne00);
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/ggml_tensor.h b/ggml/src/ggml-et/et-kernels/src/ggml_tensor.h
new file mode 100644 (file)
index 0000000..8585d56
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/ggml_tensor.h
@@ -0,0 +1,44 @@
+// ET kernel entry-point parameter structs and tensor helpers.
+
+#ifndef GGML_TENSOR_H
+#define GGML_TENSOR_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include "ggml.h"
+
+struct ggml_et_binary_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+// bias.data == NULL -> unfused MUL_MAT; otherwise dst = mat_mul(...) + bias.
+struct ggml_et_mm_q8_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+    struct ggml_tensor bias;
+};
+
+struct ggml_et_mul_mat_id_params {
+    struct ggml_tensor src0;  // [K, M, n_expert]
+    struct ggml_tensor src1;  // [K, n_expert_used, batch]
+    struct ggml_tensor src2;  // [n_expert_used, batch] (I32 expert indices)
+    struct ggml_tensor dst;   // [M, n_expert_used, batch, 1]
+};
+
+// ne[i] == 1 axes are skipped: their stride is unobservable.
+static inline int ggml_tensor_is_contiguous(const struct ggml_tensor * t, int type_size) {
+    int64_t expected = type_size;
+    for (int i = 0; i < GGML_MAX_DIMS; i++) {
+        if (t->ne[i] > 1 && (int64_t) t->nb[i] != expected) {
+            return 0;
+        }
+        expected *= t->ne[i];
+    }
+    return 1;
+}
+
+#endif  // GGML_TENSOR_H

diff --git a/ggml/src/ggml-et/et-kernels/src/glu_f32.c b/ggml/src/ggml-et/et-kernels/src/glu_f32.c
new file mode 100644 (file)
index 0000000..95fe572
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/glu_f32.c
@@ -0,0 +1,551 @@
+//******************************************************************************
+// GLU F32 Kernel (SwiGLU specifically)
+// Gated Linear Unit: y[i] = silu(x[i]) * g[i] where silu(x) = x * sigmoid(x)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+// GLU kernel parameters structure (from ET backend ops)
+struct ggml_et_glu_params {
+    struct ggml_tensor src0;         // F32 input tensor A (or combined tensor if src1 is null)
+    struct ggml_tensor src1;         // F32 input tensor B (null for single tensor mode)
+    struct ggml_tensor dst;          // F32 output tensor (n/2 columns)
+    int32_t            glu_op_type;  // GLU operation type (REGLU=0, GEGLU=1, SWIGLU=2, etc.)
+    int32_t            swapped;      // Whether gate and value are swapped
+    float              alpha;        // SWIGLU_OAI: sigmoid scaling factor
+    float              limit;        // SWIGLU_OAI: clamp limit
+};
+
+// SiLU activation function: silu(x) = x * sigmoid(x) = x / (1 + exp(-x))
+static inline float silu_f32(float x) {
+    // For numerical stability, use the mathematically equivalent form:
+    // silu(x) = x / (1 + exp(-x)) = x * sigmoid(x)
+    // For large negative x, exp(-x) -> inf, so silu(x) -> 0
+    // For large positive x, exp(-x) -> 0, so silu(x) -> x
+
+    if (x > 20.0f) {
+        // For x > 20, exp(-x) is negligible, silu(x) ~ x
+        return x;
+    } else if (x < -20.0f) {
+        // For x < -20, silu(x) ~ 0
+        return 0.0f;
+    } else {
+        // Use standard formula: silu(x) = x / (1 + exp(-x))
+        // Optimized using ET hardware division
+        float exp_neg_x   = et_expf(-x);
+        float denominator = 1.0f + exp_neg_x;
+        return et_fdiv(x, denominator);
+    }
+}
+
+// Vectorized GeGLU block processing (8 elements = 1 cache line, 64B aligned)
+// gelu(x) = 0.5*x*(1 + tanh(z)) = x * (1 - 1/(exp(2z)+1))
+// where z = sqrt(2/pi) * x * (1 + 0.044715*x^2)
+// Reformulated to avoid inf*0 NaN: uses x * sigmoid(2z) identity
+static inline void block_geglu(float * dst_block, const float * x_block, const float * g_block, int elements) {
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    float one_const       = 1.0f;
+    float coef_a_const    = 0.044715f;
+    float sqrt2pi_const   = 0.79788456080286535587989211986876f;  // sqrt(2/pi)
+    float two_log2e_const = 2.8853900817779268f;                  // 2 * log2(e)
+
+    for (int32_t i = 0; i < elements; i += 8) {
+        __asm__ volatile(
+            // Load inputs
+            "flw.ps f10, %[x_vec]\n"  // f10 = x
+            "flw.ps f11, %[g_vec]\n"  // f11 = g
+
+            // Broadcast constants
+            "fbc.ps f20, %[one_ptr]\n"        // f20 = 1.0
+            "fbc.ps f22, %[coef_ptr]\n"       // f22 = 0.044715
+            "fbc.ps f23, %[sqrt2pi_ptr]\n"    // f23 = sqrt(2/pi)
+            "fbc.ps f24, %[two_log2e_ptr]\n"  // f24 = 2*log2(e)
+
+            // inner = 1 + 0.044715 * x^2
+            "fmul.ps f12, f10, f10\n"        // f12 = x^2
+            "fmadd.ps f13, f22, f12, f20\n"  // f13 = 1 + 0.044715*x^2
+
+            // z = sqrt(2/pi) * x * inner
+            "fmul.ps f14, f23, f10\n"  // f14 = sqrt(2/pi) * x
+            "fmul.ps f14, f14, f13\n"  // f14 = z
+
+            // exp(2z) via fexp.ps: feed z * 2*log2(e) since fexp computes 2^input
+            "fmul.ps f15, f14, f24\n"  // f15 = 2z * log2(e)
+            "fexp.ps f15, f15\n"       // f15 = exp(2z)
+
+            // gelu(x) = x * (1 - 1/(exp(2z)+1))  [NaN-safe: no inf*0]
+            // exp(2z)->inf: rcp(inf)=0, 1-0=1, gelu=x
+            // exp(2z)->0:   rcp(1)=1,   1-1=0, gelu=0
+            "fadd.ps f16, f15, f20\n"  // f16 = exp(2z) + 1
+            "frcp.ps f16, f16\n"       // f16 = 1/(exp(2z) + 1)
+            "fsub.ps f16, f20, f16\n"  // f16 = 1 - 1/(exp(2z)+1)
+            "fmul.ps f16, f10, f16\n"  // f16 = gelu(x)
+
+            // Final result
+            "fmul.ps f18, f16, f11\n"  // f18 = gelu(x) * g
+
+            "fsw.ps f18, %[dst_out]\n"
+
+            : [dst_out] "=m"(*(float (*)[8]) & dst_block[i])
+            : [x_vec] "m"(*(const float (*)[8]) & x_block[i]), [g_vec] "m"(*(const float (*)[8]) & g_block[i]),
+              [one_ptr] "m"(one_const), [coef_ptr] "m"(coef_a_const), [sqrt2pi_ptr] "m"(sqrt2pi_const),
+              [two_log2e_ptr] "m"(two_log2e_const)
+            : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f18", "f20", "f22", "f23", "f24");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+}
+
+// Vectorized SwiGLU block processing (16 elements = 1 cache line)
+static inline void block_swiglu(float * dst_block, const float * x_block, const float * g_block, int elements) {
+    // Process 8 elements at a time using vector instructions
+    int32_t vec_end = (elements / 8) * 8;
+
+    // Set mask register to enable all 8 vector elements
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));  // Save current mask
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");           // Enable all 8 elements
+
+    // Constants for broadcasting
+    float zero_const  = 0.0f;
+    float one_const   = 1.0f;
+    float log2e_const = 1.4426950408889634f;  // log2(e)
+
+    for (int32_t i = 0; i < vec_end; i += 8) {
+        // Vectorized SwiGLU: dst = silu(x) * g = (x / (1 + exp(-x))) * g
+        // Using ET hardware: exp, reciprocal, multiply operations
+        __asm__ volatile(
+            // Load input vectors
+            "flw.ps f10, %[x_vec]\n"  // f10 = x[0..7]
+            "flw.ps f11, %[g_vec]\n"  // f11 = g[0..7]
+
+            // Broadcast constants to vector registers
+            "fbc.ps f20, %[zero_ptr]\n"  // f20 = broadcast(0.0f) to all 8 elements
+            "fbc.ps f21, %[one_ptr]\n"   // f21 = broadcast(1.0f) to all 8 elements
+
+            // Compute -x (negate x by subtracting from zero)
+            "fsub.ps f12, f20, f10\n"  // f12 = 0 - x = -x
+
+            // Convert to base-2 exponent: -x * log2(e) = -x * 1.44269504
+            // Load log2(e) constant
+            "fbc.ps f22, %[log2e_ptr]\n"  // f22 = broadcast(1.44269504f)
+            "fmul.ps f13, f12, f22\n"     // f13 = -x * log2(e)
+
+            // Compute 2^(-x * log2(e)) = exp(-x)
+            "fexp.ps f14, f13\n"  // f14 = 2^(-x * log2(e)) = exp(-x)
+
+            // Compute 1 + exp(-x)
+            "fadd.ps f15, f14, f21\n"  // f15 = exp(-x) + 1
+
+            // Compute 1 / (1 + exp(-x)) using reciprocal
+            "frcp.ps f16, f15\n"  // f16 = 1 / (1 + exp(-x))
+
+            // Compute silu(x) = x * (1 / (1 + exp(-x)))
+            "fmul.ps f17, f10, f16\n"  // f17 = x * (1 / (1 + exp(-x))) = silu(x)
+
+            // Compute final result: silu(x) * g
+            "fmul.ps f18, f17, f11\n"  // f18 = silu(x) * g
+
+            // Store result
+            "fsw.ps f18, %[dst_out]\n"  // Store 8 results to destination
+
+            : [dst_out] "=m"(*(float (*)[8]) & dst_block[i])
+            : [x_vec] "m"(*(const float (*)[8]) & x_block[i]), [g_vec] "m"(*(const float (*)[8]) & g_block[i]),
+              [zero_ptr] "m"(zero_const),   // Memory reference to 0.0f for broadcasting
+              [one_ptr] "m"(one_const),     // Memory reference to 1.0f for broadcasting
+              [log2e_ptr] "m"(log2e_const)  // Memory reference to log2(e) for broadcasting
+            : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f20", "f21", "f22");
+    }
+
+    // Restore original mask
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    // Handle remaining elements (< 8) with scalar operations
+    for (int32_t i = vec_end; i < elements; i++) {
+        dst_block[i] = silu_f32(x_block[i]) * g_block[i];
+    }
+}
+
+// Vectorized ReGLU block: dst = max(0, x) * g
+static inline void block_reglu(float * dst_block, const float * x_block, const float * g_block, int elements) {
+    int32_t vec_end = (elements / 8) * 8;
+
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    float zero_const = 0.0f;
+
+    for (int32_t i = 0; i < vec_end; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x_vec]\n"     // f10 = x
+            "flw.ps  f11, %[g_vec]\n"     // f11 = g
+            "fbc.ps  f20, %[zero_ptr]\n"  // f20 = 0.0
+            "fmax.ps f12, f10, f20\n"     // f12 = max(x, 0)
+            "fmul.ps f13, f12, f11\n"     // f13 = relu(x) * g
+            "fsw.ps  f13, %[dst_out]\n"
+            : [dst_out] "=m"(*(float (*)[8]) & dst_block[i])
+            : [x_vec] "m"(*(const float (*)[8]) & x_block[i]), [g_vec] "m"(*(const float (*)[8]) & g_block[i]),
+              [zero_ptr] "m"(zero_const)
+            : "f10", "f11", "f12", "f13", "f20");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    for (int32_t i = vec_end; i < elements; i++) {
+        float xv     = x_block[i];
+        dst_block[i] = (xv > 0.0f) ? xv * g_block[i] : 0.0f;
+    }
+}
+
+// Vectorized GeGLU-Quick block: dst = x * sigmoid(1.702 * x) * g
+// Using gelu_quick(x) = x / (1 + exp(-1.702*x))
+static inline void block_geglu_quick(float * dst_block, const float * x_block, const float * g_block, int elements) {
+    int32_t vec_end = (elements / 8) * 8;
+
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    float zero_const        = 0.0f;
+    float one_const         = 1.0f;
+    // -1.702 * log2(e), so that fexp.ps(x * neg_k_log2e) = exp(-1.702*x)
+    float neg_k_log2e_const = -1.702f * 1.4426950408889634f;
+
+    for (int32_t i = 0; i < vec_end; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x_vec]\n"     // f10 = x
+            "flw.ps  f11, %[g_vec]\n"     // f11 = g
+            "fbc.ps  f20, %[zero_ptr]\n"  // f20 = 0
+            "fbc.ps  f21, %[one_ptr]\n"   // f21 = 1
+            "fbc.ps  f22, %[k_ptr]\n"     // f22 = -1.702*log2(e)
+            "fmul.ps f13, f10, f22\n"     // f13 = -1.702*x*log2(e)
+            "fexp.ps f14, f13\n"          // f14 = exp(-1.702*x)
+            "fadd.ps f15, f14, f21\n"     // f15 = 1 + exp(-1.702*x)
+            "frcp.ps f16, f15\n"          // f16 = sigmoid(1.702*x)
+            "fmul.ps f17, f10, f16\n"     // f17 = gelu_quick(x)
+            "fmul.ps f18, f17, f11\n"     // f18 = gelu_quick(x) * g
+            "fsw.ps  f18, %[dst_out]\n"
+            : [dst_out] "=m"(*(float (*)[8]) & dst_block[i])
+            : [x_vec] "m"(*(const float (*)[8]) & x_block[i]), [g_vec] "m"(*(const float (*)[8]) & g_block[i]),
+              [zero_ptr] "m"(zero_const), [one_ptr] "m"(one_const), [k_ptr] "m"(neg_k_log2e_const)
+            : "f10", "f11", "f13", "f14", "f15", "f16", "f17", "f18", "f20", "f21", "f22");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    for (int32_t i = vec_end; i < elements; i++) {
+        float xv     = x_block[i];
+        // Reuse silu reciprocal path: sigmoid(1.702*x) = 1/(1+exp(-1.702*x))
+        float e      = et_expf(-1.702f * xv);
+        dst_block[i] = et_fdiv(xv, 1.0f + e) * g_block[i];
+    }
+}
+
+// Vectorized SwiGLU-OAI block (OpenAI gpt-oss variant):
+//   x_c = min(x, limit)
+//   y_c = clamp(g, -limit, limit)
+//   out = (x_c / (1 + exp(-alpha * x_c))) * (y_c + 1)
+static inline void block_swiglu_oai(float *       dst_block,
+                                    const float * x_block,
+                                    const float * g_block,
+                                    int           elements,
+                                    float         alpha,
+                                    float         limit) {
+    int32_t vec_end = (elements / 8) * 8;
+
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    float zero_const    = 0.0f;
+    float one_const     = 1.0f;
+    float limit_pos     = limit;
+    float limit_neg     = -limit;
+    // -alpha * log2(e): feed (x * neg_alpha_log2e) into fexp.ps to get exp(-alpha*x)
+    float neg_alpha_l2e = -alpha * 1.4426950408889634f;
+
+    for (int32_t i = 0; i < vec_end; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x_vec]\n"     // f10 = x raw
+            "flw.ps  f11, %[g_vec]\n"     // f11 = g raw
+
+            "fbc.ps  f20, %[zero_ptr]\n"  // f20 = 0
+            "fbc.ps  f21, %[one_ptr]\n"   // f21 = 1
+            "fbc.ps  f23, %[lim_pos]\n"   // f23 = +limit
+            "fbc.ps  f24, %[lim_neg]\n"   // f24 = -limit
+            "fbc.ps  f25, %[k_ptr]\n"     // f25 = -alpha*log2(e)
+
+            // x_c = min(x, +limit)  (no lower bound on x per OAI spec)
+            "fmin.ps f12, f10, f23\n"  // f12 = x_c
+
+            // y_c = clamp(g, -limit, +limit) = min(max(g, -limit), +limit)
+            "fmax.ps f13, f11, f24\n"  // f13 = max(g, -limit)
+            "fmin.ps f13, f13, f23\n"  // f13 = y_c
+
+            // sigmoid(alpha * x_c) = 1 / (1 + exp(-alpha * x_c))
+            "fmul.ps f14, f12, f25\n"  // f14 = -alpha*x_c*log2(e)
+            "fexp.ps f15, f14\n"       // f15 = exp(-alpha*x_c)
+            "fadd.ps f15, f15, f21\n"  // f15 = 1 + exp(-alpha*x_c)
+            "frcp.ps f16, f15\n"       // f16 = sigmoid(alpha*x_c)
+
+            // out_glu = x_c * sigmoid(alpha*x_c)
+            "fmul.ps f17, f12, f16\n"  // f17 = swiglu_oai gate output
+
+            // dst = out_glu * (y_c + 1)
+            "fadd.ps f18, f13, f21\n"  // f18 = y_c + 1
+            "fmul.ps f19, f17, f18\n"  // f19 = final
+            "fsw.ps  f19, %[dst_out]\n"
+
+            : [dst_out] "=m"(*(float (*)[8]) & dst_block[i])
+            : [x_vec] "m"(*(const float (*)[8]) & x_block[i]), [g_vec] "m"(*(const float (*)[8]) & g_block[i]),
+              [zero_ptr] "m"(zero_const), [one_ptr] "m"(one_const), [lim_pos] "m"(limit_pos), [lim_neg] "m"(limit_neg),
+              [k_ptr] "m"(neg_alpha_l2e)
+            : "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f23", "f24", "f25");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    // Scalar tail (mirrors CPU reference exactly)
+    for (int32_t i = vec_end; i < elements; i++) {
+        float xv = x_block[i];
+        float yv = g_block[i];
+        if (xv > limit) {
+            xv = limit;
+        }
+        if (yv > limit) {
+            yv = limit;
+        }
+        if (yv < -limit) {
+            yv = -limit;
+        }
+        float e       = et_expf(-alpha * xv);
+        float out_glu = et_fdiv(xv, 1.0f + e);
+        dst_block[i]  = out_glu * (yv + 1.0f);
+    }
+}
+
+// Scalar erf approximation (Abramowitz & Stegun 7.1.26, max error ~1.5e-7)
+static inline float erf_approx(float x) {
+    const float a1 = 0.254829592f;
+    const float a2 = -0.284496736f;
+    const float a3 = 1.421413741f;
+    const float a4 = -1.453152027f;
+    const float a5 = 1.061405429f;
+    const float p  = 0.3275911f;
+
+    float sign = (x < 0.0f) ? -1.0f : 1.0f;
+    float ax   = (x < 0.0f) ? -x : x;
+    float t    = et_fdiv(1.0f, 1.0f + p * ax);
+    float t2   = t * t;
+    float t3   = t2 * t;
+    float t4   = t3 * t;
+    float t5   = t4 * t;
+    float poly = a1 * t + a2 * t2 + a3 * t3 + a4 * t4 + a5 * t5;
+    float y    = 1.0f - poly * et_expf(-ax * ax);
+    return sign * y;
+}
+
+// GeGLU-Erf block: dst = 0.5 * x * (1 + erf(x / sqrt(2))) * g
+// Scalar implementation — variant is rarely used so we keep complexity low.
+static inline void block_geglu_erf(float * dst_block, const float * x_block, const float * g_block, int elements) {
+    const float sqrt_2_inv = 0.70710678118654752440f;
+    for (int32_t i = 0; i < elements; i++) {
+        float xv     = x_block[i];
+        dst_block[i] = 0.5f * xv * (1.0f + erf_approx(xv * sqrt_2_inv)) * g_block[i];
+    }
+}
+
+// Main entry point for GLU kernel
+int entry_point(struct ggml_et_glu_params * params, void * env) {
+    // Cast env to proper type
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    // Validate environment pointer
+    if (!kernel_env) {
+        return -1;
+    }
+
+    // Get thread info using shire mask from environment
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    // Basic safety check on params
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    // Supported variants: SwiGLU, SwiGLU-OAI, GeGLU, GeGLU-Erf, GeGLU-Quick, ReGLU
+    switch (params->glu_op_type) {
+        case GGML_GLU_OP_SWIGLU:
+        case GGML_GLU_OP_SWIGLU_OAI:
+        case GGML_GLU_OP_GEGLU:
+        case GGML_GLU_OP_GEGLU_ERF:
+        case GGML_GLU_OP_GEGLU_QUICK:
+        case GGML_GLU_OP_REGLU:
+            break;
+        default:
+            return -1;  // Unsupported GLU operation
+    }
+
+    // Extract tensor references
+    struct ggml_tensor * src0    = &params->src0;
+    struct ggml_tensor * src1    = params->src1.data ? &params->src1 : 0;
+    struct ggml_tensor * dst     = &params->dst;
+    int32_t              swapped = params->swapped;
+
+    // Validate tensor types (F32 only)
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    if (src1 && src1->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported src1 type
+    }
+
+    // Get data pointers
+    float * src0_data = (float *) src0->data;
+    float * src1_data = src1 ? (float *) src1->data : src0_data;
+    float * dst_data  = (float *) dst->data;
+
+    // Validate data pointers
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    // Get tensor dimensions
+    const int64_t nc = dst->ne[0];                            // Output columns (input columns / 2)
+    const int64_t nr = dst->ne[1] * dst->ne[2] * dst->ne[3];  // Total rows
+
+    // Get strides
+    const size_t src0_stride = src0->nb[1];                       // Stride between rows in src0
+    const size_t src1_stride = src1 ? src1->nb[1] : src0->nb[1];  // Stride between rows in src1
+    const size_t dst_stride  = dst->nb[1];                        // Stride between rows in dst
+
+    // Validate dimensions for split SwiGLU
+    if (src1) {
+        // Split tensor mode: src0 and src1 should have same shape as dst
+        if (src0->ne[0] != nc || src1->ne[0] != nc) {
+            return -1;  // Dimension mismatch in split mode
+        }
+    } else {
+        // Single tensor mode: src0 should have 2*nc columns
+        if (src0->ne[0] != 2 * nc) {
+            return -1;  // Dimension mismatch in single tensor mode
+        }
+    }
+
+    // Calculate total elements for cache line distribution
+    const int64_t elements_per_cacheline = 16;  // 64 bytes / 4 bytes per float
+    const int64_t total_elements         = nr * nc;
+    const int64_t total_cachelines       = (total_elements + elements_per_cacheline - 1) / elements_per_cacheline;
+
+    // Distribute cache lines across threads
+    int64_t cachelines_per_thread = (total_cachelines + num_threads - 1) / num_threads;
+    int64_t start_cacheline       = thread_id * cachelines_per_thread;
+    int64_t end_cacheline         = start_cacheline + cachelines_per_thread;
+
+    // Clamp end_cacheline to actual number of cache lines
+    if (end_cacheline > total_cachelines) {
+        end_cacheline = total_cachelines;
+    }
+
+    // Thread should return if no work to do
+    if (start_cacheline >= total_cachelines) {
+        return 0;
+    }
+
+    // Process cache lines assigned to this thread
+    for (int64_t cl = start_cacheline; cl < end_cacheline; cl++) {
+        // Map cache line back to element coordinates
+        int64_t global_element_start = cl * elements_per_cacheline;
+        int64_t row                  = global_element_start / nc;
+        int64_t col                  = global_element_start % nc;
+
+        // Skip if we're past the end of data
+        if (global_element_start >= total_elements) {
+            break;
+        }
+
+        // Calculate how many elements to process in this cache line
+        int64_t elements_remaining = total_elements - global_element_start;
+        int     elements_this_block =
+            (int) ((elements_remaining < elements_per_cacheline) ? elements_remaining : elements_per_cacheline);
+
+        // Process elements that span across rows
+        int64_t elements_processed = 0;
+        while (elements_processed < elements_this_block && row < nr) {
+            // Calculate elements to process in current row
+            int64_t elements_in_row     = nc - col;
+            int64_t elements_to_process = elements_this_block - elements_processed;
+            if (elements_to_process > elements_in_row) {
+                elements_to_process = elements_in_row;
+            }
+
+            // Get pointers for current row and column range
+            float * dst_ptr = (float *) ((char *) dst_data + row * dst_stride) + col;
+
+            float * x_ptr;
+            float * g_ptr;
+
+            if (src1) {
+                // Split tensor mode
+                x_ptr = (float *) ((char *) src0_data + row * src0_stride) + col;
+                g_ptr = (float *) ((char *) src1_data + row * src1_stride) + col;
+            } else {
+                // Single tensor mode - src0 contains both x and g
+                float * src0_row = (float *) ((char *) src0_data + row * src0_stride);
+                if (swapped) {
+                    g_ptr = src0_row + col;       // First half is gate
+                    x_ptr = src0_row + nc + col;  // Second half is value
+                } else {
+                    x_ptr = src0_row + col;       // First half is value
+                    g_ptr = src0_row + nc + col;  // Second half is gate
+                }
+            }
+
+            // Process this segment
+            switch (params->glu_op_type) {
+                case GGML_GLU_OP_GEGLU:
+                    block_geglu(dst_ptr, x_ptr, g_ptr, (int) elements_to_process);
+                    break;
+                case GGML_GLU_OP_SWIGLU:
+                    block_swiglu(dst_ptr, x_ptr, g_ptr, (int) elements_to_process);
+                    break;
+                case GGML_GLU_OP_REGLU:
+                    block_reglu(dst_ptr, x_ptr, g_ptr, (int) elements_to_process);
+                    break;
+                case GGML_GLU_OP_GEGLU_QUICK:
+                    block_geglu_quick(dst_ptr, x_ptr, g_ptr, (int) elements_to_process);
+                    break;
+                case GGML_GLU_OP_GEGLU_ERF:
+                    block_geglu_erf(dst_ptr, x_ptr, g_ptr, (int) elements_to_process);
+                    break;
+                case GGML_GLU_OP_SWIGLU_OAI:
+                    block_swiglu_oai(dst_ptr, x_ptr, g_ptr, (int) elements_to_process, params->alpha, params->limit);
+                    break;
+                default:
+                    return -1;
+            }
+
+            // Update counters
+            elements_processed += elements_to_process;
+            col += elements_to_process;
+
+            // Move to next row if current row is complete
+            if (col >= nc) {
+                row++;
+                col = 0;
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/group_norm_f32.c b/ggml/src/ggml-et/et-kernels/src/group_norm_f32.c
new file mode 100644 (file)
index 0000000..600e7c9
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/group_norm_f32.c
@@ -0,0 +1,171 @@
+//******************************************************************************
+// GROUP_NORM F32 Kernel
+// Baseline scalar implementation:
+//   normalize over (ne0 * ne1 * channels_in_group) for each (group, batch).
+//
+// Parallelization:
+// - Work is partitioned across (group, batch) pairs.
+// - For non-cache-aligned ne0, writes are emitted in row-groups so each thread's
+//   destination write footprint still spans an integer number of cache lines.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_group_norm_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+    int32_t            n_groups;
+    float              eps;
+};
+
+int entry_point(struct ggml_et_group_norm_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float * src0_data = (const float *) src0->data;
+    float *       dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int32_t n_groups = params->n_groups;
+    const float   eps      = params->eps;
+
+    if (n_groups <= 0 || eps < 0.0f) {
+        return -1;
+    }
+
+    const int64_t ne0 = dst->ne[0];
+    const int64_t ne1 = dst->ne[1];
+    const int64_t ne2 = dst->ne[2];
+    const int64_t ne3 = dst->ne[3];
+
+    if (src0->ne[0] != ne0 || src0->ne[1] != ne1 || src0->ne[2] != ne2 || src0->ne[3] != ne3) {
+        return -1;
+    }
+
+    const int64_t nb1  = dst->nb[1];
+    const int64_t nb2  = dst->nb[2];
+    const int64_t nb3  = dst->nb[3];
+    const int64_t nb01 = src0->nb[1];
+    const int64_t nb02 = src0->nb[2];
+    const int64_t nb03 = src0->nb[3];
+
+    const int64_t channels_per_group = (ne2 + n_groups - 1) / n_groups;
+    if (channels_per_group <= 0) {
+        return -1;
+    }
+
+    const int64_t active_groups        = (ne2 + channels_per_group - 1) / channels_per_group;
+    const int64_t total_work           = active_groups * ne3;
+    const int64_t rows_per_write_group = et_rows_per_cacheline_group(ne0, sizeof(float));
+
+    for (int64_t work = thread_id; work < total_work; work += num_threads) {
+        const int64_t i3        = work / active_groups;
+        const int64_t group_idx = work % active_groups;
+
+        const int64_t channel_start = group_idx * channels_per_group;
+        int64_t       channel_end   = channel_start + channels_per_group;
+        if (channel_end > ne2) {
+            channel_end = ne2;
+        }
+
+        const int64_t channel_count = channel_end - channel_start;
+        if (channel_count <= 0) {
+            continue;
+        }
+
+        float sum   = 0.0f;
+        float denom = 0.0f;
+        for (int64_t i2 = channel_start; i2 < channel_end; ++i2) {
+            for (int64_t i1 = 0; i1 < ne1; ++i1) {
+                const float * src_row = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                    sum += src_row[i0];
+                    denom += 1.0f;
+                }
+            }
+        }
+
+        const float mean = et_fdiv(sum, denom);
+
+        float var_sum = 0.0f;
+        for (int64_t i2 = channel_start; i2 < channel_end; ++i2) {
+            for (int64_t i1 = 0; i1 < ne1; ++i1) {
+                const float * src_row = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                    const float centered = src_row[i0] - mean;
+                    var_sum += centered * centered;
+                }
+            }
+        }
+
+        const float variance = et_fdiv(var_sum, denom);
+        const float scale    = et_fdiv(1.0f, et_sqrtf(variance + eps));
+
+        if (ne0 % 16 == 0) {
+            for (int64_t i2 = channel_start; i2 < channel_end; ++i2) {
+                for (int64_t i1 = 0; i1 < ne1; ++i1) {
+                    const float * src_row =
+                        (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                    float * dst_row = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+                    for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                        dst_row[i0] = (src_row[i0] - mean) * scale;
+                    }
+                }
+            }
+        } else {
+            const int64_t total_rows_in_group = channel_count * ne1;
+            const int64_t total_write_groups  = (total_rows_in_group + rows_per_write_group - 1) / rows_per_write_group;
+
+            for (int64_t write_group = 0; write_group < total_write_groups; ++write_group) {
+                const int64_t row_start = write_group * rows_per_write_group;
+                int64_t       row_end   = row_start + rows_per_write_group;
+                if (row_end > total_rows_in_group) {
+                    row_end = total_rows_in_group;
+                }
+
+                for (int64_t row = row_start; row < row_end; ++row) {
+                    const int64_t local_i2 = row / ne1;
+                    const int64_t i1       = row % ne1;
+                    const int64_t i2       = channel_start + local_i2;
+
+                    const float * src_row =
+                        (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                    float * dst_row = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+                    for (int64_t i0 = 0; i0 < ne0; ++i0) {
+                        dst_row[i0] = (src_row[i0] - mean) * scale;
+                    }
+                }
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/im2col.c b/ggml/src/ggml-et/et-kernels/src/im2col.c
new file mode 100644 (file)
index 0000000..252e66f
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/im2col.c
@@ -0,0 +1,130 @@
+//******************************************************************************
+// IM2COL Kernel
+// Baseline scalar implementation for:
+//   src1: [N, IC, IH, IW] -> dst: [N, OH, OW, IC*KH*KW] (2D)
+//   src1: [N, IC,    IW] -> dst: [N,  1, OW, IC*   KW] (1D)
+//
+// Work is distributed by row-groups so threads own cache-line-aligned chunks of
+// destination rows even when ne0 is not cache aligned.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+static inline void im2col_store_elem(void * dst_base, enum ggml_type dst_type, int64_t idx, float value) {
+    if (dst_type == GGML_TYPE_F32) {
+        ((float *) dst_base)[idx] = value;
+    } else {
+        ((uint16_t *) dst_base)[idx] = fp32_to_fp16(value);
+    }
+}
+
+static inline float im2col_load_src_elem(const void * src_base, enum ggml_type src_type, int64_t idx) {
+    if (src_type == GGML_TYPE_F32) {
+        return ((const float *) src_base)[idx];
+    }
+
+    return fp16_to_fp32(((const uint16_t *) src_base)[idx]);
+}
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env || params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (!src1->data || !dst->data) {
+        return -1;
+    }
+
+    if (!((dst->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) ||
+          (dst->type == GGML_TYPE_F16 && (src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32)))) {
+        return -1;
+    }
+
+    const int32_t s0    = ((const int32_t *) dst->op_params)[0];
+    const int32_t s1    = ((const int32_t *) dst->op_params)[1];
+    const int32_t p0    = ((const int32_t *) dst->op_params)[2];
+    const int32_t p1    = ((const int32_t *) dst->op_params)[3];
+    const int32_t d0    = ((const int32_t *) dst->op_params)[4];
+    const int32_t d1    = ((const int32_t *) dst->op_params)[5];
+    const int32_t is_2d = ((const int32_t *) dst->op_params)[6];
+
+    const int64_t N  = is_2d ? src1->ne[3] : src1->ne[2];
+    const int64_t IC = is_2d ? src1->ne[2] : src1->ne[1];
+    const int64_t IH = is_2d ? src1->ne[1] : 1;
+    const int64_t IW = src1->ne[0];
+
+    const int64_t KH = is_2d ? src0->ne[1] : 1;
+    const int64_t KW = src0->ne[0];
+
+    const int64_t OH         = is_2d ? dst->ne[2] : 1;
+    const int64_t OW         = dst->ne[1];
+    const int64_t row_elems  = dst->ne[0];
+    const int64_t total_rows = OW * OH * N;
+
+    const size_t src_batch_stride   = is_2d ? src1->nb[3] : src1->nb[2];
+    const size_t src_channel_stride = is_2d ? src1->nb[2] : src1->nb[1];
+
+    const size_t dst_row_stride   = dst->nb[1];
+    const size_t dst_plane_stride = is_2d ? dst->nb[2] : 0;
+    const size_t dst_batch_stride = is_2d ? dst->nb[3] : dst->nb[2];
+
+    const int64_t dst_elem_size  = (dst->type == GGML_TYPE_F32) ? (int64_t) sizeof(float) : (int64_t) sizeof(uint16_t);
+    const int64_t rows_per_group = et_rows_per_cacheline_group(row_elems, dst_elem_size);
+    const int64_t total_groups   = (total_rows + rows_per_group - 1) / rows_per_group;
+
+    for (int64_t grp = thread_id; grp < total_groups; grp += num_threads) {
+        const int64_t row_start = grp * rows_per_group;
+        int64_t       row_end   = row_start + rows_per_group;
+        if (row_end > total_rows) {
+            row_end = total_rows;
+        }
+
+        for (int64_t row = row_start; row < row_end; ++row) {
+            const int64_t in  = row / (OH * OW);
+            const int64_t rem = row % (OH * OW);
+            const int64_t ioh = rem / OW;
+            const int64_t iow = rem % OW;
+
+            void * dst_row = (char *) dst->data + in * dst_batch_stride + ioh * dst_plane_stride + iow * dst_row_stride;
+
+            for (int64_t iic = 0; iic < IC; ++iic) {
+                const void * src_channel = (const char *) src1->data + in * src_batch_stride + iic * src_channel_stride;
+
+                for (int64_t ikh = 0; ikh < KH; ++ikh) {
+                    for (int64_t ikw = 0; ikw < KW; ++ikw) {
+                        const int64_t iiw     = iow * s0 + ikw * d0 - p0;
+                        const int64_t iih     = ioh * s1 + ikh * d1 - p1;
+                        const int64_t dst_idx = iic * (KH * KW) + ikh * KW + ikw;
+
+                        if (iiw < 0 || iiw >= IW || iih < 0 || iih >= IH) {
+                            im2col_store_elem(dst_row, dst->type, dst_idx, 0.0f);
+                        } else {
+                            const int64_t src_idx = iih * IW + iiw;
+                            const float   value   = im2col_load_src_elem(src_channel, src1->type, src_idx);
+                            im2col_store_elem(dst_row, dst->type, dst_idx, value);
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/l2_norm_f32.c b/ggml/src/ggml-et/et-kernels/src/l2_norm_f32.c
new file mode 100644 (file)
index 0000000..8b67117
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/l2_norm_f32.c
@@ -0,0 +1,237 @@
+//******************************************************************************
+// L2 Norm F32 Kernel (L2 Normalization)
+// y[i] = x[i] / max(sqrt(sum(x^2)), eps)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+// L2 Norm kernel parameters structure
+struct ggml_et_l2_norm_params {
+    struct ggml_tensor src0;  // F32 input tensor
+    struct ggml_tensor dst;   // F32 output tensor
+    float              eps;   // Epsilon parameter for numerical stability
+};
+
+int entry_point(struct ggml_et_l2_norm_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+    float                eps  = params->eps;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    if (eps < 0.0f) {
+        return -1;  // Invalid epsilon
+    }
+
+    const int64_t ne0 = dst->ne[0];
+    const int64_t ne1 = dst->ne[1];
+    const int64_t ne2 = dst->ne[2];
+    const int64_t ne3 = dst->ne[3];
+
+    const size_t nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+    const size_t nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+
+    (void) nb0;
+    (void) nb00;
+
+    if (src0->ne[0] != ne0 || src0->ne[1] != ne1 || src0->ne[2] != ne2 || src0->ne[3] != ne3) {
+        return -1;  // Shape mismatch
+    }
+
+    const int32_t total_rows    = (int32_t) (ne1 * ne2 * ne3);
+    const int     shire_threads = SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+
+    if (total_rows >= shire_threads) {
+        // Row-parallel: each thread processes whole rows
+        for (int64_t i3 = 0; i3 < ne3; i3++) {
+            for (int64_t i2 = 0; i2 < ne2; i2++) {
+                for (int64_t i1 = thread_id; i1 < ne1; i1 += num_threads) {
+                    const float * src_ptr =
+                        (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                    float * dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+                    float zero = 0.0f;
+                    __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[x_vec]\n"
+                            "fmadd.ps f10, f11, f11, f10\n"
+                            :
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                            : "f10", "f11");
+                    }
+
+                    float sum_sq;
+                    __asm__ __volatile__(
+                        "fswizz.ps f1, f10, 0xB1 \n\t"
+                        "fadd.ps   f2, f10, f1, rne \n\t"
+                        "fswizz.ps f3, f2, 0x4E \n\t"
+                        "fadd.ps   f4, f2, f3, rne \n\t"
+                        "fmvz.x.ps t0, f4, 4 \n\t"
+                        "fbcx.ps   f5, t0 \n\t"
+                        "fadd.ps   %[vout], f4, f5, rne \n\t"
+                        : [vout] "=f"(sum_sq)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+                    float l2_norm = et_powf(sum_sq, 0.5f);
+                    if (l2_norm < eps) {
+                        l2_norm = eps;
+                    }
+                    const float scale = et_fdiv(1.0f, l2_norm);
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[x_vec]\n"
+                            "fbc.ps f12, %[scale_ptr]\n"
+                            "fmul.ps f13, f11, f12\n"
+                            "fsw.ps f13, %[result]\n"
+                            : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0]), [scale_ptr] "m"(scale)
+                            : "f11", "f12", "f13");
+                    }
+                }
+            }
+        }
+    } else {
+        // Intra-row: threads within each shire cooperate via L2 SCP
+        int shire_tid       = thread_id % shire_threads;
+        int threads_per_row = shire_threads / total_rows;
+        int my_row          = shire_tid / threads_per_row;
+        int local_tid       = shire_tid % threads_per_row;
+        int group_base      = my_row * threads_per_row;
+
+        if (my_row >= total_rows) {
+            FENCE;
+            et_barrier(ET_BARRIER_SHIRE);
+            return 0;
+        }
+
+        int64_t i1 = my_row % ne1;
+        int64_t i2 = (my_row / ne1) % ne2;
+        int64_t i3 = my_row / (ne1 * ne2);
+
+        const float * src_ptr = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+        float *       dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+        const int32_t elems_per_cl   = 16;
+        int32_t       total_cls      = ((int32_t) ne0 + elems_per_cl - 1) / elems_per_cl;
+        int32_t       cls_per_thread = (total_cls + threads_per_row - 1) / threads_per_row;
+        int32_t       my_start       = local_tid * cls_per_thread * elems_per_cl;
+        int32_t       my_end         = my_start + cls_per_thread * elems_per_cl;
+        if (my_end > (int32_t) ne0) {
+            my_end = (int32_t) ne0;
+        }
+        if (my_start >= (int32_t) ne0) {
+            my_start = 0;
+            my_end   = 0;
+        }
+
+        unsigned long saved_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+        // Phase 1: partial sum of squares
+        __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+        for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+            __asm__ volatile(
+                "flw.ps f11, %[x_vec]\n"
+                "fmadd.ps f10, f11, f11, f10\n"
+                :
+                : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                : "f10", "f11");
+        }
+
+        float partial_sum;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(partial_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+        // Phase 2: L2SCP exchange
+        volatile float * my_slot = (volatile float *) et_shire_l2scp_local((uint64_t) shire_tid * 64);
+        *my_slot                 = partial_sum;
+        FENCE;
+        evict_to_l2((const void *) my_slot, 1, 64);
+        WAIT_CACHEOPS;
+
+        et_barrier(ET_BARRIER_SHIRE);
+
+        // Phase 3: all threads reduce + apply scale to own chunk
+        int workers = threads_per_row < total_cls ? threads_per_row : total_cls;
+
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            evict_to_l2((const void *) slot, 1, 64);
+        }
+        WAIT_CACHEOPS;
+
+        float total_sum_sq = 0.0f;
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            total_sum_sq += *slot;
+        }
+
+        float l2_norm = et_powf(total_sum_sq, 0.5f);
+        if (l2_norm < eps) {
+            l2_norm = eps;
+        }
+        const float scale = et_fdiv(1.0f, l2_norm);
+
+        if (my_start < my_end) {
+            uint32_t scale_bits;
+            __asm__ volatile("fmv.x.s %0, %1" : "=r"(scale_bits) : "f"(scale));
+            __asm__ volatile("fbcx.ps f13, %[sb]\n" : : [sb] "r"(scale_bits) : "f13");
+
+            for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+                __asm__ volatile(
+                    "flw.ps f12, %[x_vec]\n"
+                    "fmul.ps f14, f12, f13\n"
+                    "fsw.ps f14, %[result]\n"
+                    : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                    : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                    : "f12", "f14");
+            }
+        }
+
+        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/linker.ld b/ggml/src/ggml-et/et-kernels/src/linker.ld
new file mode 100644 (file)
index 0000000..b7d3485
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/linker.ld
@@ -0,0 +1,85 @@
+/*-------------------------------------------------------------------------
+ * Independent Linker Script for GGML Bare Metal Kernels
+ *-------------------------------------------------------------------------
+ */
+
+/* Define maximum number of harts (threads) - simplified for bare metal */
+MAX_HARTS = 2112;
+
+SECTIONS
+{
+  /* Start at the base address passed by -Wl,--defsym=BASE_ADDRESS=... */
+  . = BASE_ADDRESS;
+
+  /* Export entry point symbol for runtime compatibility */
+  KERNEL_UMODE_ENTRY = BASE_ADDRESS;
+
+  /* Initialization section - must come first */
+  .text.init :
+  {
+     *(.text.init)
+  }
+
+  /* Align to cache line boundary */
+  . = ALIGN(64);
+
+  /* Main text section for code */
+  .text : {
+    *(.text)
+    *(.text.*)
+  }
+  . = ALIGN(64);
+
+  /* Data section with global pointer setup */
+  .data :
+  {
+    _data_start = .;
+    . = ALIGN(64);
+
+    /* Small data section and global pointer */
+    *(.sdata .sdata.*)
+    PROVIDE( __global_pointer$ = . + 0x800 );
+
+    /* Regular data */
+    *(.data .data.*)
+    . = ALIGN(64);
+    _data_end = .;
+  }
+  . = ALIGN(64);
+
+  /* BSS section for uninitialized data */
+  .bss(NOLOAD) :
+  {
+    _bss_start = .;
+    *(.sbss*);
+    *(.bss*);
+    . = ALIGN(64);
+    _bss_end = .;
+  }
+
+  /* Thread Local Storage (TLS) sections */
+  . = ALIGN(64);
+  .tdata :
+  {
+     *(.tdata*)
+     . = ALIGN(64);
+  }
+  __tdata_start = ADDR(.tdata);
+
+  .tbss : {
+      __tbss_start = .;
+      *(.tbss*)
+  }
+  . = . + SIZEOF(.tbss);
+  . = ALIGN(64);
+  __tbss_end = .;
+
+  /* TLS allocation area for all harts */
+  .tls-alloc ALIGN(64) (NOLOAD) : {
+     __tls_alloc_start = .;
+     . = . + (ABSOLUTE(__tbss_end) - ABSOLUTE(__tdata_start)) * MAX_HARTS;
+  }
+
+  /* End of kernel image */
+  _end = .;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/math_fp.h b/ggml/src/ggml-et/et-kernels/src/math_fp.h
new file mode 100644 (file)
index 0000000..552ee8d
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/math_fp.h
@@ -0,0 +1,299 @@
+//******************************************************************************
+// ET Floating Point Math Library
+// Provides ET hardware-specific math functions, FP16 conversion, and trig functions
+// for bare metal kernels
+//******************************************************************************
+
+#ifndef MATH_FP_H
+#define MATH_FP_H
+
+#include <stdint.h>
+
+//******************************************************************************
+// ET Hardware Math Functions
+//******************************************************************************
+
+// ET hardware division function (uses FRCP.PS instruction)
+static inline float et_fdiv(float a, float b) {
+    float         d;
+    unsigned long temp;
+
+    __asm__ volatile(
+        "mova.x.m  %[temp]              \n\t"
+        "mov.m.x   m0, x0, 1            \n\t"
+        "frcp.ps   %[d], %[b]           \n\t"
+        "fmul.s    %[d], %[d], %[a]     \n\t"
+        "mova.m.x  %[temp]              \n\t"
+        : [temp] "=&r"(temp), [d] "=&f"(d)
+        : [a] "f"(a), [b] "f"(b));
+
+    return d;
+}
+
+// Power function using ET hardware vector instructions
+// Implements pow(base, exp) = exp(exp * ln(base)) using FLOG.PS and FEXP.PS
+static inline float et_powf(float base, float exp) {
+    // Handle special cases
+    if (base <= 0.0f) {
+        if (base == 0.0f) {
+            if (exp > 0.0f) {
+                return 0.0f;
+            }
+
+            // For exp <= 0, return +infinity (IEEE 754: sign=0, exp=0xFF, mantissa=0)
+            union {
+                float    f;
+                uint32_t i;
+            } inf = { .i = 0x7F800000 };
+
+            return inf.f;
+        }
+
+        // For negative base, return NaN (IEEE 754: exp=0xFF, mantissa!=0)
+        union {
+            float    f;
+            uint32_t i;
+        } nan = { .i = 0x7FC00000 };
+
+        return nan.f;
+    }
+    if (base == 1.0f) {
+        return 1.0f;
+    }
+    if (exp == 0.0f) {
+        return 1.0f;
+    }
+    if (exp == 1.0f) {
+        return base;
+    }
+
+    // Use ET hardware instructions following DNN library pattern:
+    // pow(base, exp) = exp(exp * ln(base))
+    float         result;
+    unsigned long temp;
+
+    __asm__ volatile(
+        "mova.x.m  %[temp]              \n\t"      // Save current mask state
+        "mov.m.x   m0, x0, 1            \n\t"      // Set mask register m0 to enable element 0
+        "flog.ps %[result], %[base]     \n\t"      // result = ln(base)
+        "fmul.s %[result], %[result], %[exp]\n\t"  // result = ln(base) * exp
+        "fexp.ps %[result], %[result]   \n\t"      // result = exp(ln(base) * exp) = base^exp
+        "mova.m.x  %[temp]              \n\t"      // Restore mask state
+        : [temp] "=&r"(temp), [result] "=&f"(result)
+        : [base] "f"(base), [exp] "f"(exp));
+
+    return result;
+}
+
+// Natural logarithm.
+static inline float et_logf(float x) {
+    // Handle special cases
+    if (x < 0.0f) {
+        // Return NaN for negative input
+        union {
+            float    f;
+            uint32_t i;
+        } nan = { .i = 0x7FC00000 };
+
+        return nan.f;
+    }
+    if (x == 0.0f) {
+        // Return -infinity for log(0)
+        union {
+            float    f;
+            uint32_t i;
+        } inf = { .i = 0xFF800000 };
+
+        return inf.f;
+    }
+    if (x == 1.0f) {
+        return 0.0f;
+    }
+
+    float         log2_result;
+    unsigned long temp;
+
+    __asm__ volatile(
+        "mova.x.m  %[temp]              \n\t"  // Save current mask state
+        "mov.m.x   m0, x0, 1            \n\t"  // Set mask register m0 to enable element 0
+        "flog.ps %[result], %[x]        \n\t"  // result = log2(x)
+        "mova.m.x  %[temp]              \n\t"  // Restore mask state
+        : [temp] "=&r"(temp), [result] "=&f"(log2_result)
+        : [x] "f"(x));
+
+    // Convert log2 to natural log: ln(x) = log2(x) * ln(2)
+    const float ln2 = 0.69314718055994530942f;
+    return log2_result * ln2;
+}
+
+// Square root function implemented as et_powf(x, 0.5)
+static inline float et_sqrtf(float x) {
+    // Handle special cases
+    if (x < 0.0f) {
+        // Return NaN for negative input (IEEE 754: exp=0xFF, mantissa!=0)
+        union {
+            float    f;
+            uint32_t i;
+        } nan = { .i = 0x7FC00000 };
+
+        return nan.f;
+    }
+    if (x == 0.0f) {
+        return 0.0f;
+    }
+
+    return et_powf(x, 0.5f);
+}
+
+// Base-2 exponential: returns 2^x using the ET hardware FEXP.PS instruction.
+// No base conversion, no special-case clamping — this is the raw hardware op
+// with just the mask save/restore wrapper.  Caller is responsible for ensuring
+// x is in a range that produces a useful result (roughly [-126, 128] for fp32).
+static inline float __attribute__((always_inline)) et_exp2f(float x) {
+    unsigned long old_mask;
+    float         out;
+    __asm__ volatile(
+        "mova.x.m  %[ms]             \n\t"
+        "mov.m.x   m0, x0, 1         \n\t"
+        "fexp.ps   %[out], %[x]      \n\t"
+        "mova.m.x  %[ms]             \n\t"
+        : [ms] "=&r"(old_mask), [out] "=&f"(out)
+        : [x] "f"(x));
+    return out;
+}
+
+// Exponential function using ET hardware FEXP.PS instruction
+// Note: FEXP.PS computes 2^x, so we need to convert: exp(x) = 2^(x * log2(e))
+static inline float et_expf(float x) {
+    // Handle special cases
+    if (x > 88.0f) {
+        // For x > 88, exp(x) would overflow, return +infinity
+        union {
+            float    f;
+            uint32_t i;
+        } inf = { .i = 0x7F800000 };
+
+        return inf.f;
+    }
+    if (x < -87.0f) {
+        // For x < -87, exp(x) is essentially 0
+        return 0.0f;
+    }
+
+    // Convert to base-2 exponent: x * log2(e)
+    const float log2e   = 1.4426950408889634f;  // log2(e)
+    float       x_log2e = x * log2e;
+
+    // Use ET hardware instruction: fexp.ps computes 2^x
+    float         result;
+    unsigned long temp;
+
+    __asm__ volatile(
+        "mova.x.m  %[temp]              \n\t"  // Save current mask state
+        "mov.m.x   m0, x0, 1            \n\t"  // Set mask register m0 to enable element 0
+        "fexp.ps %[result], %[x_log2e]  \n\t"  // result = 2^(x * log2(e)) = exp(x)
+        "mova.m.x  %[temp]              \n\t"  // Restore mask state
+        : [temp] "=&r"(temp), [result] "=&f"(result)
+        : [x_log2e] "f"(x_log2e));
+
+    return result;
+}
+
+//******************************************************************************
+// Trigonometric Functions
+//******************************************************************************
+
+// FSIN.PS
+
+// Sine function using Taylor series
+static inline float et_sinf(float x) {
+    const float pi        = 3.14159265358979323846f;
+    const float two_pi    = 6.28318530717958647693f;
+    const float pi_over_2 = 1.57079632679489661923f;
+
+    if (x > pi || x < -pi) {
+        float cycles = x * et_fdiv(1.0f, two_pi);
+        int   n      = (int) cycles;
+        if (x < 0.0f) {
+            n--;  // Floor for negative
+        }
+        x = x - (float) n * two_pi;
+    }
+
+    // sin(x) = sin(π - x) for x in [π/2, π]
+    // sin(x) = -sin(-π - x) for x in [-π, -π/2]
+    int negate = 0;
+    if (x > pi_over_2) {
+        x = pi - x;
+    } else if (x < -pi_over_2) {
+        x      = -pi - x;
+        negate = 1;
+    }
+
+    // sin(x) ≈ x - x^3/3! + x^5/5! - x^7/7! + x^9/9! - x^11/11!
+    const float x2  = x * x;
+    const float x3  = x2 * x;
+    const float x5  = x3 * x2;
+    const float x7  = x5 * x2;
+    const float x9  = x7 * x2;
+    const float x11 = x9 * x2;
+
+    float result = x - x3 * et_fdiv(1.0f, 6.0f)         // x^3/3!
+                   + x5 * et_fdiv(1.0f, 120.0f)         // x^5/5!
+                   - x7 * et_fdiv(1.0f, 5040.0f)        // x^7/7!
+                   + x9 * et_fdiv(1.0f, 362880.0f)      // x^9/9!
+                   - x11 * et_fdiv(1.0f, 39916800.0f);  // x^11/11!
+
+    return negate ? -result : result;
+}
+
+// Cosine function using identity cos(x) = sin(x + π/2)
+static inline float et_cosf(float x) {
+    const float pi_over_2 = 1.57079632679489661923f;
+    return et_sinf(x + pi_over_2);
+}
+
+//******************************************************************************
+// FP16 <-> FP32 Conversion Functions
+//******************************************************************************
+
+// Convert FP16 (IEEE 754 half precision) to FP32 (single precision)
+// Uses ET hardware FCVT.PS.F16 instruction for accurate conversion
+static inline float fp16_to_fp32(uint16_t h) {
+    float         result;
+    unsigned long temp;
+    uint32_t      raw = (uint32_t) h;
+
+    __asm__ volatile(
+        "mova.x.m  %[temp]              \n\t"    // Save current mask state
+        "mov.m.x   m0, x0, 1            \n\t"    // Set mask register m0 to enable element 0
+        "fbcx.ps   %[result], %[raw]    \n\t"    // Broadcast raw FP16 bits into vector register
+        "fcvt.ps.f16 %[result], %[result] \n\t"  // Convert FP16 to FP32
+        "mova.m.x  %[temp]              \n\t"    // Restore mask state
+        : [temp] "=&r"(temp), [result] "=&f"(result)
+        : [raw] "r"(raw));
+
+    return result;
+}
+
+// Convert FP32 (single precision) to FP16 (IEEE 754 half precision)
+// Uses ET hardware FCVT.F16.PS instruction for accurate conversion
+static inline uint16_t fp32_to_fp16(float f) {
+    float         result_f;
+    unsigned long temp;
+
+    __asm__ volatile(
+        "mova.x.m  %[temp]              \n\t"  // Save current mask state
+        "mov.m.x   m0, x0, 1            \n\t"  // Set mask register m0 to enable element 0
+        "fcvt.f16.ps %[result], %[f]    \n\t"  // Convert FP32 to FP16 (result in lower 16 bits)
+        "mova.m.x  %[temp]              \n\t"  // Restore mask state
+        : [temp] "=&r"(temp), [result] "=&f"(result_f)
+        : [f] "f"(f));
+
+    // Extract lower 16 bits containing the FP16 value
+    // The instruction zero-extends to 32 bits, so upper 16 bits are 0
+    uint32_t result_bits = *(uint32_t *) &result_f;
+    return (uint16_t) result_bits;
+}
+
+#endif  // MATH_FP_H

diff --git a/ggml/src/ggml-et/et-kernels/src/mean_f32.c b/ggml/src/ggml-et/et-kernels/src/mean_f32.c
new file mode 100644 (file)
index 0000000..cbb0064
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mean_f32.c
@@ -0,0 +1,220 @@
+//******************************************************************************
+// MEAN F32 Kernel
+// Row-wise mean reduction: dst[0, i1, i2, i3] = mean(src0[0..ne00-1, i1, i2, i3])
+//
+// Modes:
+//   - total_rows >= shire_threads: row-parallel, each thread handles whole rows.
+//   - total_rows <  shire_threads: intra-row reduction within a shire. Threads
+//     within a shire cooperate via shire-local L2 SCP slots. All shires
+//     duplicate the work because L2 SCP is per-shire (no cross-shire coherency).
+//
+// ne00 may be any positive size and rows may have any 4-byte alignment. We
+// take the 8-wide vector path only when the row pointer is 32B-aligned and
+// fall back to scalar for the leftover tail (or for the entire row when the
+// row start is not 32B-aligned).
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_mean_params {
+    struct ggml_tensor src0;  // F32 input  [ne00, ne01, ne02, ne03]
+    struct ggml_tensor dst;   // F32 output [1,    ne01, ne02, ne03]
+};
+
+// Sum a contiguous F32 slice [base+i_lo, base+i_hi). Uses the 8-wide vector
+// path only when `base + i_lo` is 32B-aligned; the tail (and the whole slice
+// when misaligned) is summed with scalar fadd.s.
+static inline float partial_sum_slice(const float * base, int32_t i_lo, int32_t i_hi) {
+    if (i_lo >= i_hi) {
+        return 0.0f;
+    }
+
+    const float * p   = base + i_lo;
+    int32_t       n   = i_hi - i_lo;
+    float         acc = 0.0f;
+    int32_t       i   = 0;
+
+    if (n >= 8 && (((uintptr_t) p) & 31) == 0) {
+        float zero = 0.0f;
+        __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+        for (; i + 8 <= n; i += 8) {
+            __asm__ volatile(
+                "flw.ps  f11, %[x]\n"
+                "fadd.ps f10, f10, f11\n"
+                :
+                : [x] "m"(*(const float (*)[8]) & p[i])
+                : "f10", "f11");
+        }
+
+        float vec_sum;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(vec_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+        acc = vec_sum;
+    }
+
+    for (; i < n; i++) {
+        acc += p[i];
+    }
+    return acc;
+}
+
+int entry_point(struct ggml_et_mean_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne00 = src0->ne[0];
+    const int64_t ne01 = src0->ne[1];
+    const int64_t ne02 = src0->ne[2];
+    const int64_t ne03 = src0->ne[3];
+
+    const size_t nb01 = src0->nb[1];
+    const size_t nb02 = src0->nb[2];
+    const size_t nb03 = src0->nb[3];
+
+    const size_t nb1 = dst->nb[1];
+    const size_t nb2 = dst->nb[2];
+    const size_t nb3 = dst->nb[3];
+
+    if (ne00 <= 0) {
+        return 0;
+    }
+
+    const int32_t total_rows    = (int32_t) (ne01 * ne02 * ne03);
+    const int     shire_threads = SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+    const float   inv_ne00      = et_fdiv(1.0f, (float) (int32_t) ne00);
+
+    // Row-parallel: each thread owns whole rows.
+    if (total_rows >= shire_threads) {
+        for (int64_t ir = thread_id; ir < total_rows; ir += num_threads) {
+            const int64_t i03 = ir / (ne02 * ne01);
+            const int64_t i02 = (ir - i03 * ne02 * ne01) / ne01;
+            const int64_t i01 = ir - i03 * ne02 * ne01 - i02 * ne01;
+
+            const float * src_row = (const float *) ((const char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03);
+            float *       dst_ptr = (float *) ((char *) dst_data + i01 * nb1 + i02 * nb2 + i03 * nb3);
+
+            float row_sum = partial_sum_slice(src_row, 0, (int32_t) ne00);
+            atomic_store_f32(dst_ptr, row_sum * inv_ne00);
+        }
+        // Shire co-work
+    } else {
+        int shire_tid       = thread_id % shire_threads;
+        int threads_per_row = shire_threads / total_rows;
+        int my_row          = shire_tid / threads_per_row;
+        int local_tid       = shire_tid % threads_per_row;
+        int group_base      = my_row * threads_per_row;
+
+        if (my_row >= total_rows) {
+            FENCE;
+            et_barrier(ET_BARRIER_SHIRE);
+            return 0;
+        }
+
+        int64_t i1 = my_row % ne01;
+        int64_t i2 = (my_row / ne01) % ne02;
+        int64_t i3 = my_row / (ne01 * ne02);
+
+        const float * src_ptr = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+        float *       dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+        // Chunk size in elements, rounded up to a multiple of 8 so that every
+        // thread's slice start stays 32B-aligned relative to src_ptr (which
+        // matters for the vector path inside partial_sum_slice).
+        int32_t chunk = ((int32_t) ne00 + threads_per_row - 1) / threads_per_row;
+        chunk         = (chunk + 7) & ~7;
+        if (chunk < 8) {
+            chunk = 8;
+        }
+
+        int32_t my_start = local_tid * chunk;
+        int32_t my_end   = my_start + chunk;
+        if (my_end > (int32_t) ne00) {
+            my_end = (int32_t) ne00;
+        }
+        if (my_start > (int32_t) ne00) {
+            my_start = my_end = (int32_t) ne00;
+        }
+
+        int workers = ((int32_t) ne00 + chunk - 1) / chunk;
+        if (workers > threads_per_row) {
+            workers = threads_per_row;
+        }
+
+        unsigned long saved_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+        float partial_sum = partial_sum_slice(src_ptr, my_start, my_end);
+
+        // Publish partial to shire-local L2 SCP slot (64B per slot, one per
+        // hart). evict_to_l2 is required on the WRITER because scalar stores
+        // land in L1D first; readers must also evict before reading.
+        volatile float * my_slot = (volatile float *) et_shire_l2scp_local((uint64_t) shire_tid * 64);
+        *my_slot                 = partial_sum;
+        FENCE;
+        evict_to_l2((const void *) my_slot, 1, 64);
+        WAIT_CACHEOPS;
+
+        et_barrier(ET_BARRIER_SHIRE);
+
+        if (local_tid == 0) {
+            // Reader-side evictions for every contributing peer slot.
+            for (int t = 0; t < workers; t++) {
+                volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+                evict_to_l2((const void *) slot, 1, 64);
+            }
+            WAIT_CACHEOPS;
+
+            float total_sum = 0.0f;
+            for (int t = 0; t < workers; t++) {
+                volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+                total_sum += *slot;
+            }
+            atomic_store_f32(dst_ptr, total_sum * inv_ne00);
+        }
+
+        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/memops.c b/ggml/src/ggml-et/et-kernels/src/memops.c
new file mode 100644 (file)
index 0000000..b2163a4
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/memops.c
@@ -0,0 +1,181 @@
+//******************************************************************************
+// Memory Operations Kernel — tensor_store based memset
+//
+// Uses the tensor engine's store path (bypasses L1+L2 caches) to achieve hiher
+// performance. Unrolled vector writes can write at ~25GB/s and tensor writes
+// can so ~71 GB/s. Only even harts (hart 0 per minion) participate, as due to
+// hardware design (only thye have matrix engine access and co-op stores seems
+// slower)
+//******************************************************************************
+
+#include "platform.h"
+#include "tensor.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+
+// Operation identifiers for memops kernel
+enum ggml_et_memop_type {
+    GGML_ET_MEMOP_MEMSET = 0,
+};
+
+// Memset operation parameters (must match host-side struct in ggml-et-memops.cpp)
+struct memset_params {
+    uint32_t op_type;
+    uint32_t value;
+    void *   dst_ptr;
+    size_t   size;
+};
+
+// Fill all 32 f-regs with a replicated byte pattern
+static inline void __attribute__((always_inline)) fill_fregs(uint32_t fill32) {
+    register uint64_t val __asm__("a2") = fill32;
+    __asm__ __volatile__(
+        "fbcx.ps f0, %[v]\n\t"
+        "fbcx.ps f1, %[v]\n\t"
+        "fbcx.ps f2, %[v]\n\t"
+        "fbcx.ps f3, %[v]\n\t"
+        "fbcx.ps f4, %[v]\n\t"
+        "fbcx.ps f5, %[v]\n\t"
+        "fbcx.ps f6, %[v]\n\t"
+        "fbcx.ps f7, %[v]\n\t"
+        "fbcx.ps f8, %[v]\n\t"
+        "fbcx.ps f9, %[v]\n\t"
+        "fbcx.ps f10, %[v]\n\t"
+        "fbcx.ps f11, %[v]\n\t"
+        "fbcx.ps f12, %[v]\n\t"
+        "fbcx.ps f13, %[v]\n\t"
+        "fbcx.ps f14, %[v]\n\t"
+        "fbcx.ps f15, %[v]\n\t"
+        "fbcx.ps f16, %[v]\n\t"
+        "fbcx.ps f17, %[v]\n\t"
+        "fbcx.ps f18, %[v]\n\t"
+        "fbcx.ps f19, %[v]\n\t"
+        "fbcx.ps f20, %[v]\n\t"
+        "fbcx.ps f21, %[v]\n\t"
+        "fbcx.ps f22, %[v]\n\t"
+        "fbcx.ps f23, %[v]\n\t"
+        "fbcx.ps f24, %[v]\n\t"
+        "fbcx.ps f25, %[v]\n\t"
+        "fbcx.ps f26, %[v]\n\t"
+        "fbcx.ps f27, %[v]\n\t"
+        "fbcx.ps f28, %[v]\n\t"
+        "fbcx.ps f29, %[v]\n\t"
+        "fbcx.ps f30, %[v]\n\t"
+        "fbcx.ps f31, %[v]\n\t" ::[v] "r"(val)
+        : "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16",
+          "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+}
+
+// Fill a partial region [start, end) using tensor_store for 16-byte-aligned
+// chunks and byte stores for any remainder < 16 bytes.
+// Assumes f-regs are already loaded with the fill pattern.
+static void memset_tail(uint8_t * start, uint8_t * end, uint8_t val) {
+    uint8_t * cur = start;
+
+    // Full 64-byte rows via tensor_store (up to 16 at a time = 1KB)
+    while (cur + 64 <= end) {
+        size_t rows = (end - cur) / 64;
+        if (rows > 16) {
+            rows = 16;
+        }
+        tensor_store(0, 0, 3, rows - 1, (uintptr_t) cur, 0, 64);
+        cur += rows * 64;
+    }
+
+    // Remaining 16-byte aligned chunk (16, 32, or 48 bytes)
+    if (cur + 16 <= end) {
+        size_t cols = (end - cur) / 16;
+        tensor_store(0, 0, cols - 1, 0, (uintptr_t) cur, 0, 64);
+        cur += cols * 16;
+    }
+
+    tensor_wait(TENSOR_STORE_WAIT);
+
+    // Final < 16 bytes with byte stores
+    while (cur < end) {
+        *(volatile uint8_t *) cur = val;
+        cur++;
+    }
+}
+
+#define ALIGN_UP(ptr, align) ((uint8_t *) (((uintptr_t) (ptr) + (align) - 1) & ~((uintptr_t) (align) - 1)))
+
+int entry_point(struct memset_params * params, kernel_environment_t * env) {
+    uint64_t hart_id = get_hart_id();
+
+    // Only even harts have tensor engine access
+    if (hart_id & 1) {
+        return 0;
+    }
+
+    if (!params || ((uintptr_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    if (params->op_type != GGML_ET_MEMOP_MEMSET) {
+        return -1;
+    }
+
+    uint8_t * dst  = (uint8_t *) params->dst_ptr;
+    size_t    size = params->size;
+
+    if (!dst || size == 0) {
+        return -1;
+    }
+
+    // Dynamic hart count from shire_mask
+    int num_even_harts = manual_popcountll(env->shire_mask) * SOC_MINIONS_PER_SHIRE;
+
+    // global_id: shire * 32 + minion (for even harts)
+    uint64_t global_id = ((hart_id >> 6) << 5) + ((hart_id >> 1) & 0x1F);
+
+    uint8_t  val    = params->value & 0xFF;
+    uint32_t fill32 = val | ((uint32_t) val << 8) | ((uint32_t) val << 16) | ((uint32_t) val << 24);
+
+    uint8_t * end = dst + size;
+
+    setup_cache_scp();
+    CLEAR_TENSOR_ERROR;
+    fill_fregs(fill32);
+
+    // Align to 16 bytes (tensor_store minimum alignment)
+    uint8_t * base = ALIGN_UP(dst, 16);
+    if (base > end) {
+        base = end;
+    }
+
+    // Hart 0 handles head bytes before alignment
+    if (global_id == 0) {
+        volatile uint8_t * p = dst;
+        while (p < (volatile uint8_t *) base) {
+            *p++ = val;
+        }
+    }
+
+    // Bulk: 1KB blocks distributed across all harts (base is already 16-byte aligned)
+    size_t aligned_size = end - base;
+    size_t total_blocks = aligned_size / 1024;
+
+    if (total_blocks > 0) {
+        size_t blocks_per_hart = total_blocks / num_even_harts;
+        size_t extra           = total_blocks % num_even_harts;
+        size_t my_start        = blocks_per_hart * global_id + (global_id < extra ? global_id : extra);
+        size_t my_count        = blocks_per_hart + (global_id < extra ? 1 : 0);
+
+        uint8_t * addr = base + my_start * 1024;
+        for (size_t b = 0; b < my_count; b++) {
+            tensor_store(0, 0, 3, 15, (uintptr_t) addr, 0, 64);
+            addr += 1024;
+        }
+        tensor_wait(TENSOR_STORE_WAIT);
+    }
+
+    // Hart 0 handles the tail after the last full 1KB block
+    if (global_id == 0) {
+        memset_tail(base + total_blocks * 1024, end, val);
+    }
+
+    FENCE;
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_Q4_0.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_Q4_0.c
new file mode 100644 (file)
index 0000000..d128a99
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_Q4_0.c
@@ -0,0 +1,358 @@
+//******************************************************************************
+// MUL_MAT Kernel
+// Matrix multiplication: C[M,N] = A[M,K] * B[K,N]
+//******************************************************************************
+
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <stdint.h>
+
+#define STRIDE_M                   2048 /* 32 shires x 32 minions x 2 harts */
+#define STRIDE_M_KSPLIT            1024 /* 32 shires x 32 minions (both harts share rows) */
+#define KSPLIT_MIN_K_BLOCKS        256  /* K >= 8192 elements */
+#define KSPLIT_SMALL_ROWS_K_BLOCKS 64   /* K >= 2048 elements for very small M */
+#define KSPLIT_MAX_ROWS            8    /* max rows per minion for K-split */
+#define TILE_KB                    256  /* K-tile size in Q4_0 blocks (8192 elems, 32KB B data) */
+#define KSPLIT_GROUP_ROWS          4
+#define SIMPLE_X2_ROWS             2
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    uint64_t hart_id = get_hart_id();
+
+    // Matrix dimensions
+    const int64_t K    = params->src0.ne[0];
+    const int64_t M    = params->src0.ne[1];
+    const int64_t N    = params->src1.ne[1];
+    const int64_t ne02 = params->src0.ne[2];
+    const int64_t ne03 = params->src0.ne[3];
+    const int64_t ne12 = params->src1.ne[2];
+    const int64_t ne13 = params->src1.ne[3];
+
+    // Strides (in bytes)
+    const size_t nb01 = params->src0.nb[1];
+    const size_t nb02 = params->src0.nb[2];
+    const size_t nb03 = params->src0.nb[3];
+
+    const size_t nb11 = params->src1.nb[1];
+    const size_t nb12 = params->src1.nb[2];
+    const size_t nb13 = params->src1.nb[3];
+
+    const size_t nbd1 = params->dst.nb[1];
+    const size_t nbd2 = params->dst.nb[2];
+    const size_t nbd3 = params->dst.nb[3];
+
+    // Q4_0 block size is 32
+    const int64_t K_blocks      = K / 32;
+    const int     use_simple_x2 = ((nb01 & 31) == 0);
+
+    // Broadcasting ratios
+    const int64_t r2 = ne12 / ne02;
+    const int64_t r3 = ne13 / ne03;
+
+    // K-split decision
+    const int64_t minion_id             = hart_id >> 1;          /* 0..1023 global */
+    const int64_t local_minion          = (hart_id >> 1) & 0x1F; /* 0..31 within shire */
+    const int     is_hart1              = hart_id & 1;
+    const int64_t rows_per_minion       = (M + STRIDE_M_KSPLIT - 1) / STRIDE_M_KSPLIT;
+    const int64_t k_half                = K_blocks / 2;
+    const int     use_ksplit_small_rows = (rows_per_minion <= 2) && (K_blocks >= KSPLIT_SMALL_ROWS_K_BLOCKS);
+    /*
+     * K-split when K is large enough to benefit, and either:
+     *   - few rows (≤4): always safe, proven working
+     *   - more rows (5-8): only if each hart's half fits in one tile,
+     *     otherwise L1 thrashing from 2 harts × 8 rows kills performance
+     *
+     * Also allow K-split earlier for the low-M regime (≤2 rows/minion). In
+     * that case the simple row-striped path leaves half the machine idle, so
+     * using both harts on each row pays off even for moderate K.
+     */
+    const int     use_ksplit            = ((K_blocks >= KSPLIT_MIN_K_BLOCKS) && (rows_per_minion <= KSPLIT_MAX_ROWS) &&
+                                           (rows_per_minion <= 4 || k_half <= TILE_KB)) ||
+                                          use_ksplit_small_rows;
+    const int     use_ksplit_group      = !use_ksplit && (K_blocks >= KSPLIT_MIN_K_BLOCKS) && (rows_per_minion > 4) &&
+                                          (rows_per_minion <= KSPLIT_MAX_ROWS);
+
+    if (use_ksplit) {
+        /* Each hart processes half the K dimension */
+        const int64_t k_start = is_hart1 ? k_half : 0;
+        const int64_t k_len   = is_hart1 ? (K_blocks - k_half) : k_half;
+
+        /* One cache-line-aligned L2SCP slot per minion for exchange */
+        volatile float * l2scp_slot = (volatile float *) et_shire_l2scp_local(local_minion * 64);
+
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+
+                    for (int64_t m = minion_id; m < M; m += STRIDE_M_KSPLIT) {
+                        const block_q4_0 * q_row = (const block_q4_0 *) (src0_ptr2 + m * nb01);
+
+                        float partial = compute_row_dot_q4_0(q_row + k_start, b_col_base + k_start * 32, k_len);
+
+                        if (is_hart1) {
+                            *l2scp_slot = partial;
+                            FENCE;
+                            flush_to_l2((const void *) l2scp_slot, 1, 64);
+                            WAIT_CACHEOPS;
+                            et_sem_post(ET_BARRIER_MINION);
+                            et_sem_wait(ET_BARRIER_MINION);
+                        } else {
+                            et_sem_wait(ET_BARRIER_MINION);
+                            float other = *l2scp_slot;
+                            et_sem_post(ET_BARRIER_MINION);
+
+                            float * dst_entry = (float *) (dst_ptr2 + n * nbd1 + m * sizeof(float));
+                            atomic_store_f32((volatile float *) dst_entry, partial + other);
+                        }
+                    }
+                }
+            }
+        }
+    } else if (use_ksplit_group) {
+        /*
+         * Grouped K-split for the 5-8 rows/minion regime.
+         *
+         * Both harts process the same 4-row group, each on half of K, and
+         * exchange 4 partial sums once per group instead of once per row.
+         * This keeps the K-split bandwidth benefit while cutting semaphore
+         * traffic by 4x relative to the old per-row exchange.
+         */
+        const int64_t    k_start    = is_hart1 ? k_half : 0;
+        const int64_t    k_len      = is_hart1 ? (K_blocks - k_half) : k_half;
+        volatile float * l2scp_slot = (volatile float *) et_shire_l2scp_local(local_minion * 64);
+
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+
+                    for (int64_t m_base = minion_id; m_base < M; m_base += STRIDE_M_KSPLIT * KSPLIT_GROUP_ROWS) {
+                        const int64_t m0 = m_base;
+                        const int64_t m1 = m0 + STRIDE_M_KSPLIT;
+                        const int64_t m2 = m1 + STRIDE_M_KSPLIT;
+                        const int64_t m3 = m2 + STRIDE_M_KSPLIT;
+
+                        float s0 = 0.0f, s1 = 0.0f, s2 = 0.0f, s3 = 0.0f;
+
+                        for (int64_t kb = 0; kb < K_blocks; kb += TILE_KB) {
+                            int64_t tile_len = k_len - kb;
+                            if (tile_len > TILE_KB) {
+                                tile_len = TILE_KB;
+                            }
+                            if (tile_len <= 0) {
+                                break;
+                            }
+                            const float * b_tile = b_col_base + (k_start + kb) * 32;
+                            const int64_t row_kb = k_start + kb;
+
+                            if (m0 < M) {
+                                s0 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m0 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                            if (m1 < M) {
+                                s1 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m1 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                            if (m2 < M) {
+                                s2 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m2 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                            if (m3 < M) {
+                                s3 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m3 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                        }
+
+                        if (is_hart1) {
+                            l2scp_slot[0] = s0;
+                            l2scp_slot[1] = s1;
+                            l2scp_slot[2] = s2;
+                            l2scp_slot[3] = s3;
+                            FENCE;
+                            flush_to_l2((const void *) l2scp_slot, 1, 64);
+                            WAIT_CACHEOPS;
+                            et_sem_post(ET_BARRIER_MINION);
+                            et_sem_wait(ET_BARRIER_MINION);
+                        } else {
+                            et_sem_wait(ET_BARRIER_MINION);
+                            const float p0 = l2scp_slot[0];
+                            const float p1 = l2scp_slot[1];
+                            const float p2 = l2scp_slot[2];
+                            const float p3 = l2scp_slot[3];
+                            et_sem_post(ET_BARRIER_MINION);
+
+                            float * c_base = (float *) (dst_ptr2 + n * nbd1);
+                            if (m0 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m0), s0 + p0);
+                            }
+                            if (m1 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m1), s1 + p1);
+                            }
+                            if (m2 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m2), s2 + p2);
+                            }
+                            if (m3 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m3), s3 + p3);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    } else if (K_blocks > TILE_KB) {
+        /*
+         * Tile-outer with scalar row groups: process up to 4 rows per
+         * hart sharing each B tile before advancing to the next tile.
+         * Uses scalar float variables (not an array) to accumulate across
+         * tiles — avoids the flw/fadd.s/fsw stack ops that corrupt vector
+         * register state on ET-SoC-1's MMX-style shared FP file.
+         */
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+
+                    for (int64_t m0 = hart_id; m0 < M; m0 += STRIDE_M * 4) {
+                        const int64_t m1 = m0 + STRIDE_M;
+                        const int64_t m2 = m0 + STRIDE_M * 2;
+                        const int64_t m3 = m0 + STRIDE_M * 3;
+
+                        float s0 = 0.0f, s1 = 0.0f, s2 = 0.0f, s3 = 0.0f;
+
+                        for (int64_t kb = 0; kb < K_blocks; kb += TILE_KB) {
+                            int64_t tile_len = K_blocks - kb;
+                            if (tile_len > TILE_KB) {
+                                tile_len = TILE_KB;
+                            }
+                            const float * b_tile = b_col_base + kb * 32;
+
+                            s0 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m0 * nb01) + kb, b_tile,
+                                                       tile_len);
+                            if (m1 < M) {
+                                s1 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m1 * nb01) + kb, b_tile,
+                                                           tile_len);
+                            }
+                            if (m2 < M) {
+                                s2 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m2 * nb01) + kb, b_tile,
+                                                           tile_len);
+                            }
+                            if (m3 < M) {
+                                s3 += compute_row_dot_q4_0((const block_q4_0 *) (src0_ptr2 + m3 * nb01) + kb, b_tile,
+                                                           tile_len);
+                            }
+                        }
+
+                        float * dst_base = (float *) (dst_ptr2 + n * nbd1);
+                        atomic_store_f32((volatile float *) (dst_base + m0), s0);
+                        if (m1 < M) {
+                            atomic_store_f32((volatile float *) (dst_base + m1), s1);
+                        }
+                        if (m2 < M) {
+                            atomic_store_f32((volatile float *) (dst_base + m2), s2);
+                        }
+                        if (m3 < M) {
+                            atomic_store_f32((volatile float *) (dst_base + m3), s3);
+                        }
+                    }
+                }
+            }
+        }
+    } else {
+        /*
+         * Simple path for small K.
+         *
+         * When `nb01` is 32-byte aligned, every row has the same block-alignment
+         * pattern. That lets us compute two rows together and reuse each loaded
+         * B chunk across both rows instead of reloading it in a second dot call.
+         */
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+                    q4_dot_state  q4_state;
+                    q4_dot_begin(&q4_state);
+
+                    if (use_simple_x2) {
+                        for (int64_t m0 = hart_id; m0 < M; m0 += STRIDE_M * SIMPLE_X2_ROWS) {
+                            const int64_t      m1     = m0 + STRIDE_M;
+                            const block_q4_0 * q_row0 = (const block_q4_0 *) (src0_ptr2 + m0 * nb01);
+
+                            if (m1 < M) {
+                                const block_q4_0 * q_row1 = (const block_q4_0 *) (src0_ptr2 + m1 * nb01);
+                                float              s0, s1;
+                                q4_dot_compute_x2_aligned(q_row0, q_row1, b_col_base, K_blocks, &s0, &s1);
+
+                                float * dst0 = (float *) (dst_ptr2 + n * nbd1 + m0 * sizeof(float));
+                                float * dst1 = (float *) (dst_ptr2 + n * nbd1 + m1 * sizeof(float));
+                                atomic_store_f32((volatile float *) dst0, s0);
+                                atomic_store_f32((volatile float *) dst1, s1);
+                            } else {
+                                float   sum = q4_dot_compute(q_row0, b_col_base, K_blocks);
+                                float * dst = (float *) (dst_ptr2 + n * nbd1 + m0 * sizeof(float));
+                                atomic_store_f32((volatile float *) dst, sum);
+                            }
+                        }
+                    } else {
+                        for (int64_t m = hart_id; m < M; m += STRIDE_M) {
+                            const block_q4_0 * q_row = (const block_q4_0 *) (src0_ptr2 + m * nb01);
+
+                            float sum = q4_dot_compute(q_row, b_col_base, K_blocks);
+
+                            float * dst_entry = (float *) (dst_ptr2 + n * nbd1 + m * sizeof(float));
+                            atomic_store_f32((volatile float *) dst_entry, sum);
+                        }
+                    }
+
+                    q4_dot_end(&q4_state);
+                }
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_Q4_0_matrix_engine.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_Q4_0_matrix_engine.c
new file mode 100644 (file)
index 0000000..28a1030
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_Q4_0_matrix_engine.c
@@ -0,0 +1,368 @@
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+#include "tensor.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+
+// Q4_0 x F32 -> F32 MUL_MAT on the tensor (matrix) engine, TensorFMA32.
+// Hart 1: dequantize Q4_0 weights to FP32 into double-buffered L2 SCP.
+// Hart 0: tensor engine compute (FMA, reduce, store).
+
+#define NUM_COMPUTE_SHIRES 32
+#define MINIONS_PER_SHIRE  32
+
+#define TILE_M  16
+#define TILE_N  16
+#define BLOCK_K QK4_0  // 32 elements per Q4_0 block
+#define FMA_K   16     // tensor FMA k-width for FP32 (a_num_cols = FMA_K-1)
+
+#define CACHEOP_MAX 0
+#define REP_RATE    0
+
+#define A_L1_START 0   // L1 SCP lines  0..15 for A (activations)
+#define B_L1_START 16  // L1 SCP lines 16..31 for B (dequantized weights)
+
+// L2 SCP layout per minion (double-buffered dequant panel + sync counters).
+// panel = BLOCK_K k-lines x TILE_M m (FP32) = 32 * 64 = 2048 bytes, in TenB
+// [k][m] order: panel[k*TILE_M + m].
+#define SCP_PANEL_SIZE   (BLOCK_K * TILE_M * (uint64_t) sizeof(float))  // 2048
+#define SCP_READY_OFF    (2 * SCP_PANEL_SIZE)                           // 4096
+#define SCP_CONSUMED_OFF (SCP_READY_OFF + 64)                           // 4160
+#define SCP_PER_MINION   (SCP_CONSUMED_OFF + 64)                        // 4224
+
+// Signal a counter value to the other hart via L2 SCP.
+static inline void __attribute__((always_inline)) scp_signal(volatile uint32_t * flag, uint32_t value) {
+    *flag = value;
+    FENCE;
+    evict_to_l2((const void *) flag, 1, 64);
+    WAIT_CACHEOPS;
+}
+
+// Wait for a counter in L2 SCP to reach the expected value.
+static inline void __attribute__((always_inline)) scp_wait(volatile uint32_t * flag, uint32_t expected) {
+    while (1) {
+        evict_to_l2((const void *) flag, 1, 64);
+        WAIT_CACHEOPS;
+        if (*flag >= expected) {
+            return;
+        }
+    }
+}
+
+// Dequantize one 32-element Q4_0 block of TILE_M weight rows into the FP32
+// panel, written directly in TenB [k][m] order: panel[k*TILE_M + m].
+//   Low  nibble of byte i -> k = i
+//   High nibble of byte i -> k = i + 16
+//   value = d * (nibble - 8)
+//
+// Vectorized: for each weight row m we gather 8 packed bytes at a time, expand
+// the low/high nibbles to FP32 (nibble-8), scale by the block's fp16 d, and
+// fscw.ps-scatter the 8 values down 8 panel lines (stride 64B) at column m.
+// 4 groups of 8 cover the 32 k-values (low 0..15, high 16..31).
+static inline void __attribute__((always_inline)) dequant_q4_0_panel(float *      panel,
+                                                                     const char * src0_batch,
+                                                                     int64_t      mb,
+                                                                     int64_t      kb_block,
+                                                                     int64_t      nb1_0) {
+    static const int32_t __attribute__((aligned(32))) scatter_idx[8] = {
+        0, 64, 128, 192, 256, 320, 384, 448  // byte offsets: 8 lines apart
+    };
+    static const int32_t __attribute__((aligned(32))) gather_idx[8] = {
+        0, 1, 2, 3, 4, 5, 6, 7  // 8 consecutive bytes
+    };
+
+    unsigned long old_mask;
+    __asm__ volatile(
+        "mova.x.m  %[ms]            \n\t"
+        "mov.m.x   m0, x0, 0xFF     \n\t"  // all 8 lanes active
+        "flw.ps    f1, (%[sidx])    \n\t"  // f1 = scatter offsets
+        "flw.ps    f2, (%[gidx])    \n\t"  // f2 = gather offsets
+        : [ms] "=&r"(old_mask)
+        : [sidx] "r"(scatter_idx), [gidx] "r"(gather_idx)
+        : "f1", "f2");
+
+    char * pbase = (char *) panel;
+    for (int j = 0; j < TILE_M; ++j) {
+        const block_q4_0 * blk       = (const block_q4_0 *) (src0_batch + (mb + j) * nb1_0) + kb_block;
+        uint32_t           scale_raw = (uint32_t) blk->d;
+        const uint8_t *    qs        = blk->qs;
+        char *             col       = pbase + j * 4;  // column m=j of the panel
+
+        __asm__ volatile(
+            "fbcx.ps     f3, %[sb]      \n\t"  // broadcast fp16 scale bits
+            "fcvt.ps.f16 f3, f3         \n\t"  // -> d in all 8 lanes (fp32)
+
+            "fgb.ps      f4, f2(%[qs0]) \n\t"  // gather qs[0..7]
+            "fandi.pi    f5, f4, 15     \n\t"  // low nibble
+            "faddi.pi    f5, f5, -8     \n\t"
+            "fcvt.ps.pw  f5, f5, rne    \n\t"
+            "fmul.ps     f5, f5, f3     \n\t"
+            "fscw.ps     f5, f1(%[c0])  \n\t"  // k=0..7   -> lines 0..7
+            "fsrli.pi    f6, f4, 4      \n\t"  // high nibble
+            "fandi.pi    f6, f6, 15     \n\t"
+            "faddi.pi    f6, f6, -8     \n\t"
+            "fcvt.ps.pw  f6, f6, rne    \n\t"
+            "fmul.ps     f6, f6, f3     \n\t"
+            "fscw.ps     f6, f1(%[c16]) \n\t"  // k=16..23 -> lines 16..23
+
+            "fgb.ps      f4, f2(%[qs8]) \n\t"  // gather qs[8..15]
+            "fandi.pi    f5, f4, 15     \n\t"
+            "faddi.pi    f5, f5, -8     \n\t"
+            "fcvt.ps.pw  f5, f5, rne    \n\t"
+            "fmul.ps     f5, f5, f3     \n\t"
+            "fscw.ps     f5, f1(%[c8])  \n\t"  // k=8..15  -> lines 8..15
+            "fsrli.pi    f6, f4, 4      \n\t"
+            "fandi.pi    f6, f6, 15     \n\t"
+            "faddi.pi    f6, f6, -8     \n\t"
+            "fcvt.ps.pw  f6, f6, rne    \n\t"
+            "fmul.ps     f6, f6, f3     \n\t"
+            "fscw.ps     f6, f1(%[c24]) \n\t"  // k=24..31 -> lines 24..31
+            :
+            : [sb] "r"(scale_raw), [qs0] "r"(qs), [qs8] "r"(qs + 8), [c0] "r"(col), [c8] "r"(col + 8 * 64),
+              [c16] "r"(col + 16 * 64), [c24] "r"(col + 24 * 64)
+            : "f3", "f4", "f5", "f6", "memory");
+    }
+
+    __asm__ volatile("mova.m.x %0" ::"r"(old_mask));
+}
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    (void) env;
+
+    uint64_t hart_id  = get_hart_id();
+    uint64_t shire_id = get_shire_id();
+
+    if (shire_id >= NUM_COMPUTE_SHIRES) {
+        return 0;
+    }
+
+    const int is_hart1     = hart_id & 1;
+    uint64_t  local_minion = (hart_id >> 1) & 0x1F;
+
+    // Dimensions (both harts need these for tile assignment)
+    const int64_t K = params->src0.ne[0];
+    const int64_t M = params->src0.ne[1];
+    const int64_t N = params->src1.ne[1];
+
+    if ((M % TILE_M) != 0) {
+        return 0;
+    }
+    if ((K % BLOCK_K) != 0) {
+        return 0;
+    }
+
+    const int64_t ne2_0 = params->src0.ne[2], ne3_0 = params->src0.ne[3];
+    const int64_t ne2_1 = params->src1.ne[2], ne3_1 = params->src1.ne[3];
+
+    const int64_t nb1_0 = params->src0.nb[1];
+    const int64_t nb2_0 = params->src0.nb[2], nb3_0 = params->src0.nb[3];
+
+    const int64_t nb1_1 = params->src1.nb[1];
+    const int64_t nb2_1 = params->src1.nb[2], nb3_1 = params->src1.nb[3];
+
+    const int64_t nb1_d = params->dst.nb[1];
+    const int64_t nb2_d = params->dst.nb[2], nb3_d = params->dst.nb[3];
+
+    const char * src0_base = (const char *) params->src0.data;
+    const char * src1_base = (const char *) params->src1.data;
+    char *       dst_base  = (char *) params->dst.data;
+
+    const int64_t m_tiles     = M / TILE_M;
+    const int64_t n_tiles     = (N + TILE_N - 1) / TILE_N;
+    const int64_t batch_count = ne2_1 * ne3_1;
+    const int64_t base_tiles  = m_tiles * n_tiles * batch_count;
+
+    const int64_t r2 = ne2_1 / ne2_0;
+    const int64_t r3 = ne3_1 / ne3_0;
+
+    const int64_t k_steps = K / BLOCK_K;  // number of Q4_0 blocks
+
+    // Force a single K-split.
+    const int64_t k_splits = 1;
+
+    const int64_t tiles_per_shire = MINIONS_PER_SHIRE / k_splits;
+    const int64_t k_split         = local_minion % k_splits;
+    const int64_t local_tile_idx  = local_minion / k_splits;
+    const int64_t tiles_stride    = (int64_t) NUM_COMPUTE_SHIRES * tiles_per_shire;
+
+    const int64_t k_steps_per_split = k_steps / k_splits;
+    const int64_t kb_start          = k_split * k_steps_per_split;   // first block
+    const int64_t kb_end            = kb_start + k_steps_per_split;  // one past last
+
+    // L2 SCP pointers for this minion's double-buffered panels + sync.
+    uint64_t scp_base     = local_minion * SCP_PER_MINION;
+    float *  scp_panel[2] = {
+        (float *) et_shire_l2scp_local(scp_base),
+        (float *) et_shire_l2scp_local(scp_base + SCP_PANEL_SIZE),
+    };
+    volatile uint32_t * ready_ctr    = (volatile uint32_t *) et_shire_l2scp_local(scp_base + SCP_READY_OFF);
+    volatile uint32_t * consumed_ctr = (volatile uint32_t *) et_shire_l2scp_local(scp_base + SCP_CONSUMED_OFF);
+
+    // ================================================================
+    // Hart 1: Q4_0 weight dequant producer
+    // ================================================================
+    if (is_hart1) {
+        scp_signal(ready_ctr, 0);
+        scp_signal(consumed_ctr, 0);
+
+        uint32_t chunk_id = 0;
+
+        for (int64_t tile = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES; tile < base_tiles;
+             tile += tiles_stride) {
+            const int64_t tiles_per_batch = m_tiles * n_tiles;
+            const int64_t batch_idx       = tile / tiles_per_batch;
+            const int64_t tile_in_batch   = tile % tiles_per_batch;
+
+            const int64_t mb_idx = tile_in_batch % m_tiles;
+
+            const int64_t i3   = batch_idx / ne2_1;
+            const int64_t i2   = batch_idx % ne2_1;
+            const int64_t i2_0 = i2 / r2;
+            const int64_t i3_0 = i3 / r3;
+
+            const char *  src0_batch = src0_base + i3_0 * nb3_0 + i2_0 * nb2_0;
+            const int64_t mb         = mb_idx * TILE_M;
+
+            for (int64_t kb = kb_start; kb < kb_end; ++kb) {
+                int buf = chunk_id & 1;
+
+                // Back-pressure: wait for hart 0 to finish with this buffer.
+                if (chunk_id >= 2) {
+                    scp_wait(consumed_ctr, chunk_id - 1);
+                }
+
+                dequant_q4_0_panel(scp_panel[buf], src0_batch, mb, kb, nb1_0);
+
+                FENCE;
+                flush_to_l2(scp_panel[buf], BLOCK_K, 64);
+                WAIT_CACHEOPS;
+
+                chunk_id++;
+                scp_signal(ready_ctr, chunk_id);
+            }
+        }
+
+        FENCE;
+        return 0;
+    }
+
+    // ================================================================
+    // Hart 0: tensor engine compute
+    // ================================================================
+    uint64_t       my_minion_id      = get_minion_id();
+    const uint64_t group_base_global = my_minion_id - k_split;
+
+    setup_cache_scp();
+#if CACHEOP_MAX > 0 || REP_RATE > 0
+    ucache_control(1, REP_RATE, CACHEOP_MAX);
+#endif
+    CLEAR_TENSOR_ERROR;
+
+    evict_to_l2((const void *) ready_ctr, 1, 64);
+    WAIT_CACHEOPS;
+    evict_to_l2((const void *) consumed_ctr, 1, 64);
+    WAIT_CACHEOPS;
+
+    uint32_t chunk_id = 0;
+
+    for (int64_t tile = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES; tile < base_tiles;
+         tile += tiles_stride) {
+        const int64_t tiles_per_batch = m_tiles * n_tiles;
+        const int64_t batch_idx       = tile / tiles_per_batch;
+        const int64_t tile_in_batch   = tile % tiles_per_batch;
+
+        const int64_t nb_idx = tile_in_batch / m_tiles;
+        const int64_t mb_idx = tile_in_batch % m_tiles;
+
+        const int64_t i3 = batch_idx / ne2_1;
+        const int64_t i2 = batch_idx % ne2_1;
+
+        const char * src1_batch = src1_base + i3 * nb3_1 + i2 * nb2_1;
+        char *       dst_batch  = dst_base + i3 * nb3_d + i2 * nb2_d;
+
+        const int64_t mb    = mb_idx * TILE_M;
+        const int64_t nb    = nb_idx * TILE_N;
+        const int64_t n_cur = (nb + TILE_N <= N) ? TILE_N : (N - nb);
+
+        // Partial-N tiles run TensorFMA32 with a_num_rows = n_cur-1.
+        // Errata Type D workaround for n_cur == 4 (AROWS==3): pad A to AROWS==4.
+        const int64_t arows_fma = (n_cur == 4) ? 4 : (n_cur - 1);
+
+        if (n_cur == 4) {
+            // Zero the padded 5th A row (line A_L1_START+4) once; the per-pass A
+            // load only writes lines A_L1_START..+3, so this persists.
+            static const float __attribute__((aligned(64))) zero_line[16] = { 0 };
+            tensor_load(false, false, A_L1_START + 4, TENSOR_LOAD_PLAIN, 0, (uint64_t) zero_line, 0,
+                        0,  // 1 line
+                        64, 0);
+            tensor_wait(TENSOR_LOAD_WAIT_0);
+        }
+
+        int first = 1;  // first_pass=1 only for the very first FMA of the tile
+
+        for (int64_t kb = kb_start; kb < kb_end; ++kb) {
+            int buf = chunk_id & 1;
+
+            // Wait for hart 1 to finish dequantizing this block.
+            chunk_id++;
+            scp_wait(ready_ctr, chunk_id);
+
+            // Two FMA passes over the 32-wide block (16 K-cols each).
+            for (int half = 0; half < 2; ++half) {
+                const int64_t k_elem = kb * BLOCK_K + half * FMA_K;
+
+                // Load A (activations) for this 16-K sub-tile, PLAIN.
+                tensor_load(false, false, A_L1_START, TENSOR_LOAD_PLAIN, 0,
+                            (uint64_t) (src1_batch + nb * nb1_1 + k_elem * (int64_t) sizeof(float)), 0, n_cur - 1,
+                            (uint64_t) nb1_1, 0);
+
+                // Load B (dequantized weights) half from L2 SCP panel, PLAIN.
+                tensor_load(false, false, B_L1_START, TENSOR_LOAD_PLAIN, 0,
+                            (uint64_t) (scp_panel[buf] + (int64_t) half * FMA_K * TILE_M), 0, FMA_K - 1, 64, 1);
+
+                tensor_wait(TENSOR_LOAD_WAIT_0);
+                tensor_wait(TENSOR_LOAD_WAIT_1);
+
+                tensor_fma(false,
+                           3,          // b_num_col: (16/4)-1
+                           arows_fma,  // a_num_rows (n_cur-1, or 4 for the n_cur==4 errata pad)
+                           FMA_K - 1,  // a_num_cols
+                           0, false, false, false, false, B_L1_START, A_L1_START, TENSOR_FMA_OP_FP32, first);
+
+                tensor_wait(TENSOR_FMA_WAIT);
+                first = 0;
+            }
+
+            // Signal that this buffer is free for hart 1 to reuse.
+            scp_signal(consumed_ctr, chunk_id);
+        }
+
+        // K-split ring reduce.
+        if (k_splits > 1) {
+            const uint64_t num_regs = (uint64_t) n_cur * 2;
+
+            if (k_split > 0) {
+                tensor_reduce_recv(0, TENSOR_REDUCE_OP_FADD, num_regs, group_base_global + k_split - 1);
+                tensor_wait(TENSOR_REDUCE_WAIT);
+            }
+
+            if (k_split < k_splits - 1) {
+                tensor_reduce_send(0, num_regs, group_base_global + k_split + 1);
+                tensor_wait(TENSOR_REDUCE_WAIT);
+            }
+        }
+
+        // Store FP32 result tile (only the last k-split owns the final sum).
+        if (k_split == k_splits - 1) {
+            tensor_store(0, 0, 3, n_cur - 1, (uint64_t) (dst_batch + nb * nb1_d + mb * (int64_t) sizeof(float)), 0,
+                         (uint64_t) nb1_d);
+            tensor_wait(TENSOR_STORE_WAIT);
+        }
+    }
+
+    FENCE;
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_Q8_0.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_Q8_0.c
new file mode 100644 (file)
index 0000000..ad21a3e
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_Q8_0.c
@@ -0,0 +1,413 @@
+//******************************************************************************
+// MUL_MAT Kernel
+// Matrix multiplication: C[M,N] = A[M,K] * B[K,N]
+//******************************************************************************
+
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <stdint.h>
+
+#define STRIDE_M                   2048 /* 32 shires x 32 minions x 2 harts */
+#define STRIDE_M_KSPLIT            1024 /* 32 shires x 32 minions (both harts share rows) */
+#define KSPLIT_MIN_K_BLOCKS        256  /* K >= 8192 elements */
+#define KSPLIT_SMALL_ROWS_K_BLOCKS 64   /* K >= 2048 elements for very small M */
+#define KSPLIT_MAX_ROWS            8    /* max rows per minion for K-split */
+#define TILE_KB                    256  /* K-tile size in Q8_0 blocks (8192 elems, 32KB B data) */
+#define KSPLIT_GROUP_ROWS          4
+#define SIMPLE_X2_ROWS             2
+
+static inline size_t tensor_bytes(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+int entry_point(struct ggml_et_mm_q8_params * params, void * env) {
+    uint64_t hart_id = get_hart_id();
+
+    // Matrix dimensions
+    const int64_t K    = params->src0.ne[0];
+    const int64_t M    = params->src0.ne[1];
+    const int64_t N    = params->src1.ne[1];
+    const int64_t ne02 = params->src0.ne[2];
+    const int64_t ne03 = params->src0.ne[3];
+    const int64_t ne12 = params->src1.ne[2];
+    const int64_t ne13 = params->src1.ne[3];
+
+    // Strides (in bytes)
+    const size_t nb01 = params->src0.nb[1];
+    const size_t nb02 = params->src0.nb[2];
+    const size_t nb03 = params->src0.nb[3];
+
+    const size_t nb11 = params->src1.nb[1];
+    const size_t nb12 = params->src1.nb[2];
+    const size_t nb13 = params->src1.nb[3];
+
+    const size_t nbd1 = params->dst.nb[1];
+    const size_t nbd2 = params->dst.nb[2];
+    const size_t nbd3 = params->dst.nb[3];
+
+    // Optional residual bias
+    const char * bias_base = (const char *) params->bias.data;
+    const size_t nbb1      = params->bias.nb[1];
+    const size_t nbb2      = params->bias.nb[2];
+    const size_t nbb3      = params->bias.nb[3];
+
+    // Q8_0 block size is 32
+    const int64_t K_blocks      = K / 32;
+    const int     use_simple_x2 = ((nb01 & 31) == 0);
+
+    // Broadcasting ratios
+    const int64_t r2 = ne12 / ne02;
+    const int64_t r3 = ne13 / ne03;
+
+    // K-split decision
+    const int64_t minion_id             = hart_id >> 1;          /* 0..1023 global */
+    const int64_t local_minion          = (hart_id >> 1) & 0x1F; /* 0..31 within shire */
+    const int     is_hart1              = hart_id & 1;
+    const int64_t rows_per_minion       = (M + STRIDE_M_KSPLIT - 1) / STRIDE_M_KSPLIT;
+    const int64_t k_half                = K_blocks / 2;
+    const int     use_ksplit_small_rows = (rows_per_minion <= 2) && (K_blocks >= KSPLIT_SMALL_ROWS_K_BLOCKS);
+    /*
+     * K-split when K is large enough to benefit, and either:
+     *   - few rows (≤4): always safe, proven working
+     *   - more rows (5-8): only if each hart's half fits in one tile,
+     *     otherwise L1 thrashing from 2 harts × 8 rows kills performance
+     *
+     * Also allow K-split earlier for the low-M regime (≤2 rows/minion). In
+     * that case the simple row-striped path leaves half the machine idle, so
+     * using both harts on each row pays off even for moderate K.
+     */
+    const int     use_ksplit            = ((K_blocks >= KSPLIT_MIN_K_BLOCKS) && (rows_per_minion <= KSPLIT_MAX_ROWS) &&
+                                           (rows_per_minion <= 4 || k_half <= TILE_KB)) ||
+                                          use_ksplit_small_rows;
+    const int     use_ksplit_group      = !use_ksplit && (K_blocks >= KSPLIT_MIN_K_BLOCKS) && (rows_per_minion > 4) &&
+                                          (rows_per_minion <= KSPLIT_MAX_ROWS);
+
+    evict_region_past_l2(params->src1.data, tensor_bytes(&params->src1));
+    if (params->bias.data) {
+        evict_region_past_l2(params->bias.data, tensor_bytes(&params->bias));
+    }
+
+    if (use_ksplit) {
+        /* Each hart processes half the K dimension */
+        const int64_t k_start = is_hart1 ? k_half : 0;
+        const int64_t k_len   = is_hart1 ? (K_blocks - k_half) : k_half;
+
+        /* One cache-line-aligned L2SCP slot per minion for exchange */
+        volatile float * l2scp_slot = (volatile float *) et_shire_l2scp_local(local_minion * 64);
+
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+            const char *  bias_ptr3 = bias_base ? bias_base + i3 * nbb3 : (const char *) 0;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+                const char *  bias_ptr2 = bias_ptr3 ? bias_ptr3 + i2 * nbb2 : (const char *) 0;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+                    const float * bias_n     = bias_ptr2 ? (const float *) (bias_ptr2 + n * nbb1) : (const float *) 0;
+
+                    for (int64_t m = minion_id; m < M; m += STRIDE_M_KSPLIT) {
+                        const block_q8_0 * q_row = (const block_q8_0 *) (src0_ptr2 + m * nb01);
+
+                        float partial = compute_row_dot_q8_0(q_row + k_start, b_col_base + k_start * 32, k_len);
+
+                        if (is_hart1) {
+                            *l2scp_slot = partial;
+                            FENCE;
+                            flush_to_l2((const void *) l2scp_slot, 1, 64);
+                            WAIT_CACHEOPS;
+                            et_sem_post(ET_BARRIER_MINION);
+                            et_sem_wait(ET_BARRIER_MINION);
+                        } else {
+                            et_sem_wait(ET_BARRIER_MINION);
+                            float other = *l2scp_slot;
+                            et_sem_post(ET_BARRIER_MINION);
+
+                            float * dst_entry = (float *) (dst_ptr2 + n * nbd1 + m * sizeof(float));
+                            float   sum       = partial + other;
+                            if (bias_n) {
+                                sum += bias_n[m];
+                            }
+                            atomic_store_f32((volatile float *) dst_entry, sum);
+                        }
+                    }
+                }
+            }
+        }
+    } else if (use_ksplit_group) {
+        /*
+         * Grouped K-split for the 5-8 rows/minion regime.
+         *
+         * Both harts process the same 4-row group, each on half of K, and
+         * exchange 4 partial sums once per group instead of once per row.
+         * This keeps the K-split bandwidth benefit while cutting semaphore
+         * traffic by 4x relative to the old per-row exchange.
+         */
+        const int64_t    k_start    = is_hart1 ? k_half : 0;
+        const int64_t    k_len      = is_hart1 ? (K_blocks - k_half) : k_half;
+        volatile float * l2scp_slot = (volatile float *) et_shire_l2scp_local(local_minion * 64);
+
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+            const char *  bias_ptr3 = bias_base ? bias_base + i3 * nbb3 : (const char *) 0;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+                const char *  bias_ptr2 = bias_ptr3 ? bias_ptr3 + i2 * nbb2 : (const char *) 0;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+                    const float * bias_n     = bias_ptr2 ? (const float *) (bias_ptr2 + n * nbb1) : (const float *) 0;
+
+                    for (int64_t m_base = minion_id; m_base < M; m_base += STRIDE_M_KSPLIT * KSPLIT_GROUP_ROWS) {
+                        const int64_t m0 = m_base;
+                        const int64_t m1 = m0 + STRIDE_M_KSPLIT;
+                        const int64_t m2 = m1 + STRIDE_M_KSPLIT;
+                        const int64_t m3 = m2 + STRIDE_M_KSPLIT;
+
+                        float s0 = 0.0f, s1 = 0.0f, s2 = 0.0f, s3 = 0.0f;
+
+                        for (int64_t kb = 0; kb < K_blocks; kb += TILE_KB) {
+                            int64_t tile_len = k_len - kb;
+                            if (tile_len > TILE_KB) {
+                                tile_len = TILE_KB;
+                            }
+                            if (tile_len <= 0) {
+                                break;
+                            }
+                            const float * b_tile = b_col_base + (k_start + kb) * 32;
+                            const int64_t row_kb = k_start + kb;
+
+                            if (m0 < M) {
+                                s0 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m0 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                            if (m1 < M) {
+                                s1 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m1 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                            if (m2 < M) {
+                                s2 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m2 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                            if (m3 < M) {
+                                s3 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m3 * nb01) + row_kb,
+                                                           b_tile, tile_len);
+                            }
+                        }
+
+                        if (is_hart1) {
+                            l2scp_slot[0] = s0;
+                            l2scp_slot[1] = s1;
+                            l2scp_slot[2] = s2;
+                            l2scp_slot[3] = s3;
+                            FENCE;
+                            flush_to_l2((const void *) l2scp_slot, 1, 64);
+                            WAIT_CACHEOPS;
+                            et_sem_post(ET_BARRIER_MINION);
+                            et_sem_wait(ET_BARRIER_MINION);
+                        } else {
+                            et_sem_wait(ET_BARRIER_MINION);
+                            const float p0 = l2scp_slot[0];
+                            const float p1 = l2scp_slot[1];
+                            const float p2 = l2scp_slot[2];
+                            const float p3 = l2scp_slot[3];
+                            et_sem_post(ET_BARRIER_MINION);
+
+                            float *     c_base = (float *) (dst_ptr2 + n * nbd1);
+                            const float b0     = bias_n ? bias_n[m0] : 0.0f;
+                            const float b1     = (bias_n && m1 < M) ? bias_n[m1] : 0.0f;
+                            const float b2     = (bias_n && m2 < M) ? bias_n[m2] : 0.0f;
+                            const float b3     = (bias_n && m3 < M) ? bias_n[m3] : 0.0f;
+                            if (m0 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m0), s0 + p0 + b0);
+                            }
+                            if (m1 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m1), s1 + p1 + b1);
+                            }
+                            if (m2 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m2), s2 + p2 + b2);
+                            }
+                            if (m3 < M) {
+                                atomic_store_f32((volatile float *) (c_base + m3), s3 + p3 + b3);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    } else if (K_blocks > TILE_KB) {
+        /*
+         * Tile-outer with scalar row groups: process up to 4 rows per
+         * hart sharing each B tile before advancing to the next tile.
+         * Uses scalar float variables (not an array) to accumulate across
+         * tiles — avoids the flw/fadd.s/fsw stack ops that corrupt vector
+         * register state on ET-SoC-1's MMX-style shared FP file.
+         */
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+            const char *  bias_ptr3 = bias_base ? bias_base + i3 * nbb3 : (const char *) 0;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+                const char *  bias_ptr2 = bias_ptr3 ? bias_ptr3 + i2 * nbb2 : (const char *) 0;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+                    const float * bias_n     = bias_ptr2 ? (const float *) (bias_ptr2 + n * nbb1) : (const float *) 0;
+
+                    for (int64_t m0 = hart_id; m0 < M; m0 += STRIDE_M * 4) {
+                        const int64_t m1 = m0 + STRIDE_M;
+                        const int64_t m2 = m0 + STRIDE_M * 2;
+                        const int64_t m3 = m0 + STRIDE_M * 3;
+
+                        float s0 = 0.0f, s1 = 0.0f, s2 = 0.0f, s3 = 0.0f;
+
+                        for (int64_t kb = 0; kb < K_blocks; kb += TILE_KB) {
+                            int64_t tile_len = K_blocks - kb;
+                            if (tile_len > TILE_KB) {
+                                tile_len = TILE_KB;
+                            }
+                            const float * b_tile = b_col_base + kb * 32;
+
+                            s0 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m0 * nb01) + kb, b_tile,
+                                                       tile_len);
+                            if (m1 < M) {
+                                s1 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m1 * nb01) + kb, b_tile,
+                                                           tile_len);
+                            }
+                            if (m2 < M) {
+                                s2 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m2 * nb01) + kb, b_tile,
+                                                           tile_len);
+                            }
+                            if (m3 < M) {
+                                s3 += compute_row_dot_q8_0((const block_q8_0 *) (src0_ptr2 + m3 * nb01) + kb, b_tile,
+                                                           tile_len);
+                            }
+                        }
+
+                        float *     dst_base = (float *) (dst_ptr2 + n * nbd1);
+                        const float b0       = bias_n ? bias_n[m0] : 0.0f;
+                        const float b1       = (bias_n && m1 < M) ? bias_n[m1] : 0.0f;
+                        const float b2       = (bias_n && m2 < M) ? bias_n[m2] : 0.0f;
+                        const float b3       = (bias_n && m3 < M) ? bias_n[m3] : 0.0f;
+                        atomic_store_f32((volatile float *) (dst_base + m0), s0 + b0);
+                        if (m1 < M) {
+                            atomic_store_f32((volatile float *) (dst_base + m1), s1 + b1);
+                        }
+                        if (m2 < M) {
+                            atomic_store_f32((volatile float *) (dst_base + m2), s2 + b2);
+                        }
+                        if (m3 < M) {
+                            atomic_store_f32((volatile float *) (dst_base + m3), s3 + b3);
+                        }
+                    }
+                }
+            }
+        }
+    } else {
+        /*
+         * Simple path for small K.
+         *
+         * When `nb01` is 32-byte aligned, every row has the same block-alignment
+         * pattern. That lets us compute two rows together and reuse each loaded
+         * B chunk across both rows instead of reloading it in a second dot call.
+         */
+        for (int64_t i3 = 0; i3 < ne13; i3++) {
+            const int64_t i03       = i3 / r3;
+            const char *  src0_ptr3 = (const char *) params->src0.data + i03 * nb03;
+            const char *  src1_ptr3 = (const char *) params->src1.data + i3 * nb13;
+            char *        dst_ptr3  = (char *) params->dst.data + i3 * nbd3;
+            const char *  bias_ptr3 = bias_base ? bias_base + i3 * nbb3 : (const char *) 0;
+
+            for (int64_t i2 = 0; i2 < ne12; i2++) {
+                const int64_t i02       = i2 / r2;
+                const char *  src0_ptr2 = src0_ptr3 + i02 * nb02;
+                const char *  src1_ptr2 = src1_ptr3 + i2 * nb12;
+                char *        dst_ptr2  = dst_ptr3 + i2 * nbd2;
+                const char *  bias_ptr2 = bias_ptr3 ? bias_ptr3 + i2 * nbb2 : (const char *) 0;
+
+                for (int64_t n = 0; n < N; n++) {
+                    const float * b_col_base = (const float *) (src1_ptr2 + n * nb11);
+                    const float * bias_n     = bias_ptr2 ? (const float *) (bias_ptr2 + n * nbb1) : (const float *) 0;
+                    q8_dot_state  q8_state;
+                    q8_dot_begin(&q8_state);
+
+                    if (use_simple_x2) {
+                        for (int64_t m0 = hart_id; m0 < M; m0 += STRIDE_M * SIMPLE_X2_ROWS) {
+                            const int64_t      m1     = m0 + STRIDE_M;
+                            const block_q8_0 * q_row0 = (const block_q8_0 *) (src0_ptr2 + m0 * nb01);
+
+                            if (m1 < M) {
+                                const block_q8_0 * q_row1 = (const block_q8_0 *) (src0_ptr2 + m1 * nb01);
+                                float              s0, s1;
+                                q8_dot_compute_x2_aligned(q_row0, q_row1, b_col_base, K_blocks, &s0, &s1);
+
+                                float * dst0 = (float *) (dst_ptr2 + n * nbd1 + m0 * sizeof(float));
+                                float * dst1 = (float *) (dst_ptr2 + n * nbd1 + m1 * sizeof(float));
+                                if (bias_n) {
+                                    s0 += bias_n[m0];
+                                    s1 += bias_n[m1];
+                                }
+                                atomic_store_f32((volatile float *) dst0, s0);
+                                atomic_store_f32((volatile float *) dst1, s1);
+                            } else {
+                                float   sum = q8_dot_compute(q_row0, b_col_base, K_blocks);
+                                float * dst = (float *) (dst_ptr2 + n * nbd1 + m0 * sizeof(float));
+                                if (bias_n) {
+                                    sum += bias_n[m0];
+                                }
+                                atomic_store_f32((volatile float *) dst, sum);
+                            }
+                        }
+                    } else {
+                        for (int64_t m = hart_id; m < M; m += STRIDE_M) {
+                            const block_q8_0 * q_row = (const block_q8_0 *) (src0_ptr2 + m * nb01);
+
+                            float sum = q8_dot_compute(q_row, b_col_base, K_blocks);
+
+                            float * dst_entry = (float *) (dst_ptr2 + n * nbd1 + m * sizeof(float));
+                            if (bias_n) {
+                                sum += bias_n[m];
+                            }
+                            atomic_store_f32((volatile float *) dst_entry, sum);
+                        }
+                    }
+
+                    q8_dot_end(&q8_state);
+                }
+            }
+        }
+    }
+
+#ifdef ET_UBERKERNEL
+    FENCE;
+    evict_region_past_l2(params->dst.data, tensor_bytes(&params->dst));
+    WAIT_CACHEOPS;
+    FENCE;
+#endif
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_f16.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_f16.c
new file mode 100644 (file)
index 0000000..3f1fcd5
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_f16.c
@@ -0,0 +1,142 @@
+//******************************************************************************
+// MUL_MAT Kernel
+// Matrix multiplication: C[M,N] = A[M,K] * B[K,N]
+//******************************************************************************
+
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <stdint.h>
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env || params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    // Thread coordination
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0 || (thread_id & 1)) {
+        return 0;  // Skip odd threads to avoid resource contention
+    }
+
+    int effective_thread_id   = thread_id / 2;
+    int effective_num_threads = (num_threads + 1) / 2;
+
+    // Extract tensor references
+    struct ggml_tensor * src0 = &params->src0;  // Weight matrix A (F16)
+    struct ggml_tensor * src1 = &params->src1;  // Activation matrix B (F16/F32)
+    struct ggml_tensor * dst  = &params->dst;   // Output matrix C (F32)
+
+    // Generic non-matrix-engine path: F16 x (F16/F32) -> F32
+    if (src0->type != GGML_TYPE_F16 || (src1->type != GGML_TYPE_F16 && src1->type != GGML_TYPE_F32) ||
+        dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const uint16_t * src0_data = (const uint16_t *) src0->data;
+    float *          dst_data  = (float *) dst->data;
+
+    // Dimensions and Strides
+    const int64_t K = src0->ne[0];
+    const int64_t M = src0->ne[1];
+    const int64_t N = src1->ne[1];
+
+    const int64_t ne02 = src0->ne[2], ne03 = src0->ne[3];
+    const int64_t ne12 = src1->ne[2], ne13 = src1->ne[3];
+    const int64_t ne2 = dst->ne[2], ne3 = dst->ne[3];
+
+    const size_t nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    const size_t nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3];
+    const size_t nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+
+    // F16 specific block size (Usually QK_F16)
+    const int     block_size  = QK_F16;
+    const int64_t K_blocks    = K / block_size;
+    const int64_t K_remainder = K % block_size;
+
+    // Threading distribution
+    const uint64_t total_elements = M * N * ne2 * ne3;
+    const uint64_t per_thread     = 16;
+    const uint64_t threads_stride = per_thread * effective_num_threads;
+
+    if (effective_thread_id * per_thread >= total_elements) {
+        return 0;
+    }
+
+    // Broadcasting support
+    const int64_t r2 = ne12 / ne02;
+    const int64_t r3 = ne13 / ne03;
+
+    for (uint64_t base_idx = effective_thread_id * per_thread; base_idx < total_elements; base_idx += threads_stride) {
+        for (uint64_t j = 0; j < per_thread; j++) {
+            const uint64_t idx = base_idx + j;
+            if (idx >= total_elements) {
+                break;
+            }
+
+            // Index decoding
+            const int64_t i3   = idx / (M * N * ne2);
+            const int64_t rem3 = idx % (M * N * ne2);
+            const int64_t i2   = rem3 / (M * N);
+            const int64_t rem2 = rem3 % (M * N);
+            const int64_t n    = rem2 / M;
+            const int64_t m    = rem2 % M;
+
+            const int64_t i03 = i3 / r3, i02 = i2 / r2;
+            const int64_t i13 = (ne13 > 1) ? i3 : 0, i12 = (ne12 > 1) ? i2 : 0;
+
+            float            sum = 0.0f;
+            const uint16_t * f16_row =
+                (const uint16_t *) ((const char *) src0_data + m * nb01 + i02 * nb02 + i03 * nb03);
+
+            if (src1->type == GGML_TYPE_F32) {
+                const float * src1_data = (const float *) src1->data;
+
+                for (int64_t kb = 0; kb < K_blocks; kb++) {
+                    const float * b_col_ptr =
+                        (const float *) ((const char *) src1_data + (kb * block_size) * sizeof(float) + n * nb11 +
+                                         i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f16_naive(&f16_row[kb * block_size], b_col_ptr);
+                }
+
+                if (K_remainder > 0) {
+                    const int64_t offset    = K_blocks * block_size;
+                    const float * b_col_ptr = (const float *) ((const char *) src1_data + offset * sizeof(float) +
+                                                               n * nb11 + i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f16_partial(&f16_row[offset], b_col_ptr, K_remainder);
+                }
+            } else {
+                const uint16_t * src1_data = (const uint16_t *) src1->data;
+
+                for (int64_t kb = 0; kb < K_blocks; kb++) {
+                    const uint16_t * b_col_ptr =
+                        (const uint16_t *) ((const char *) src1_data + (kb * block_size) * sizeof(uint16_t) + n * nb11 +
+                                            i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f16_f16_partial(&f16_row[kb * block_size], b_col_ptr, block_size);
+                }
+
+                if (K_remainder > 0) {
+                    const int64_t    offset = K_blocks * block_size;
+                    const uint16_t * b_col_ptr =
+                        (const uint16_t *) ((const char *) src1_data + offset * sizeof(uint16_t) + n * nb11 +
+                                            i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f16_f16_partial(&f16_row[offset], b_col_ptr, K_remainder);
+                }
+            }
+
+            // Atomic store for output
+            volatile float * c_element =
+                (volatile float *) ((char *) dst_data + m * dst->nb[0] + n * nb1 + i2 * nb2 + i3 * nb3);
+            atomic_store_f32(c_element, sum);
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_f16_matrix_engine.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_f16_matrix_engine.c
new file mode 100644 (file)
index 0000000..2aab87a
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_f16_matrix_engine.c
@@ -0,0 +1,329 @@
+#include "ggml_tensor.h"
+#include "platform.h"
+#include "tensor.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+
+// FP16 x FP16 -> FP32 MUL_MAT with hart 1 B-panel packing
+//
+// Hart 0: tensor engine (load A, load B from SCP, FMA, reduce, store)
+// Hart 1: pack B into double-buffered L2 SCP panels, flush for tensor_load
+//
+// Sync: monotonic counters in L2 SCP with evict-based coherency.
+// Double-buffered bpanel allows pack/FMA overlap.
+//
+#define NUM_COMPUTE_SHIRES 32
+#define MINIONS_PER_SHIRE  32
+
+#define TILE_M 16
+#define TILE_N 16
+#define TILE_K 32
+
+#define CACHEOP_MAX 0
+#define REP_RATE    0
+
+#define A_L1_START 0   // SCP lines  0..15 for A
+#define B_L1_START 16  // SCP lines 16..31 for B
+
+typedef uint16_t et_fp16_t;
+
+// L2 SCP layout per minion (double-buffered bpanel + sync counters)
+//   [0..1023]    bpanel buffer 0 (16 lines x 64 bytes)
+//   [1024..2047] bpanel buffer 1
+//   [2048..2111] ready counter   (hart1 -> hart0, own cache line)
+//   [2112..2175] consumed counter (hart0 -> hart1, own cache line)
+#define SCP_BPANEL_SIZE  (16 * 32 * sizeof(et_fp16_t))  // 1024 bytes
+#define SCP_READY_OFF    (2 * SCP_BPANEL_SIZE)          // 2048
+#define SCP_CONSUMED_OFF (SCP_READY_OFF + 64)           // 2112
+#define SCP_PER_MINION   (SCP_CONSUMED_OFF + 64)        // 2176
+
+// Signal a counter value to the other hart via L2 SCP.
+static inline void __attribute__((always_inline)) scp_signal(volatile uint32_t * flag, uint32_t value) {
+    *flag = value;
+    FENCE;
+    evict_to_l2((const void *) flag, 1, 64);
+    WAIT_CACHEOPS;
+}
+
+// Wait for a counter in L2 SCP to reach the expected value.
+static inline void __attribute__((always_inline)) scp_wait(volatile uint32_t * flag, uint32_t expected) {
+    while (1) {
+        evict_to_l2((const void *) flag, 1, 64);
+        WAIT_CACHEOPS;
+        if (*flag >= expected) {
+            return;
+        }
+    }
+}
+
+/**
+ * Build the interleaved B panel that TensorFMA16A32 expects (vectorized).
+ *
+ * Output: 16 lines x 32 fp16 = 1024 bytes, 64-byte aligned.
+ *   out[l][j*2+0] = src0[mb + j][kb + 2*l]
+ *   out[l][j*2+1] = src0[mb + j][kb + 2*l + 1]
+ *
+ * Uses fsch.ps scatter store: load 8 pairs per row, scatter to 8 output lines.
+ */
+static inline void __attribute__((always_inline)) pack_b_interleaved(et_fp16_t *  out,
+                                                                     const char * src0_batch,
+                                                                     int64_t      mb,
+                                                                     int64_t      kb,
+                                                                     int64_t      nb1_0) {
+    static const int32_t __attribute__((aligned(32))) scatter_idx[8] = { 0, 64, 128, 192, 256, 320, 384, 448 };
+
+    unsigned long old_mask;
+    __asm__ volatile(
+        "mova.x.m  %[ms]            \n\t"
+        "mov.m.x   m0, x0, 0xFF     \n\t"
+        "flw.ps    f1, 0(%[idx])    \n\t"
+        : [ms] "=&r"(old_mask)
+        : [idx] "r"(scatter_idx)
+        : "f1");
+
+    for (int j = 0; j < TILE_M; ++j) {
+        const et_fp16_t * row = (const et_fp16_t *) (src0_batch + (mb + j) * nb1_0) + kb;
+        char *            dst = (char *) out + j * 4;
+
+        __asm__ volatile(
+            "flw.ps    f2, 0(%[src])    \n\t"
+            "flw.ps    f3, 32(%[src])   \n\t"
+            "fscw.ps   f2, f1(%[d0])    \n\t"
+            "fscw.ps   f3, f1(%[d1])    \n\t"
+            :
+            : [src] "r"(row), [d0] "r"(dst), [d1] "r"(dst + 512)
+            : "f2", "f3", "memory");
+    }
+
+    __asm__ volatile("mova.m.x  %[ms]            \n\t" : : [ms] "r"(old_mask));
+}
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    (void) env;
+
+    uint64_t hart_id  = get_hart_id();
+    uint64_t shire_id = get_shire_id();
+
+    if (shire_id >= NUM_COMPUTE_SHIRES) {
+        return 0;
+    }
+
+    const int is_hart1     = hart_id & 1;
+    uint64_t  local_minion = (hart_id >> 1) & 0x1F;
+
+    // Dimensions (both harts need these for tile assignment)
+    const int64_t K = params->src0.ne[0];
+    const int64_t M = params->src0.ne[1];
+    const int64_t N = params->src1.ne[1];
+
+    const int64_t ne2_0 = params->src0.ne[2], ne3_0 = params->src0.ne[3];
+    const int64_t ne2_1 = params->src1.ne[2], ne3_1 = params->src1.ne[3];
+
+    const int64_t nb1_0 = params->src0.nb[1];
+    const int64_t nb2_0 = params->src0.nb[2], nb3_0 = params->src0.nb[3];
+
+    const int64_t nb1_1 = params->src1.nb[1];
+    const int64_t nb2_1 = params->src1.nb[2], nb3_1 = params->src1.nb[3];
+
+    const int64_t nb1_d = params->dst.nb[1];
+    const int64_t nb2_d = params->dst.nb[2], nb3_d = params->dst.nb[3];
+
+    const char * src0_base = (const char *) params->src0.data;
+    const char * src1_base = (const char *) params->src1.data;
+    char *       dst_base  = (char *) params->dst.data;
+
+    if ((M % TILE_M) != 0) {
+        return 0;
+    }
+    if ((K % TILE_K) != 0) {
+        return 0;
+    }
+
+    const int64_t m_tiles     = M / TILE_M;
+    const int64_t n_tiles     = (N + TILE_N - 1) / TILE_N;
+    const int64_t batch_count = ne2_1 * ne3_1;
+    const int64_t base_tiles  = m_tiles * n_tiles * batch_count;
+
+    const int64_t r2 = ne2_1 / ne2_0;
+    const int64_t r3 = ne3_1 / ne3_0;
+
+    const int64_t total_harts = NUM_COMPUTE_SHIRES * MINIONS_PER_SHIRE;
+    const int64_t k_steps     = K / TILE_K;
+
+    int64_t k_splits = 1;
+    if (base_tiles < total_harts) {
+        k_splits   = (total_harts + base_tiles - 1) / base_tiles;
+        int64_t ks = 1;
+        while (ks * 2 <= k_splits && ks * 2 <= 32 && k_steps % (ks * 2) == 0) {
+            ks *= 2;
+        }
+        k_splits = ks;
+    }
+
+    const int64_t tiles_per_shire = MINIONS_PER_SHIRE / k_splits;
+    const int64_t k_split         = local_minion % k_splits;
+    const int64_t local_tile_idx  = local_minion / k_splits;
+    const int64_t tiles_stride    = (int64_t) NUM_COMPUTE_SHIRES * tiles_per_shire;
+
+    const int64_t k_steps_per_split = k_steps / k_splits;
+    const int64_t k_start           = k_split * k_steps_per_split * TILE_K;
+    const int64_t k_end             = k_start + k_steps_per_split * TILE_K;
+
+    // L2 SCP pointers for this minion's double-buffered panels + sync
+    uint64_t    scp_base  = local_minion * SCP_PER_MINION;
+    et_fp16_t * scp_bp[2] = {
+        (et_fp16_t *) et_shire_l2scp_local(scp_base),
+        (et_fp16_t *) et_shire_l2scp_local(scp_base + SCP_BPANEL_SIZE),
+    };
+    volatile uint32_t * ready_ctr    = (volatile uint32_t *) et_shire_l2scp_local(scp_base + SCP_READY_OFF);
+    volatile uint32_t * consumed_ctr = (volatile uint32_t *) et_shire_l2scp_local(scp_base + SCP_CONSUMED_OFF);
+
+    // ================================================================
+    // Hart 1: B-panel packer
+    // ================================================================
+    if (is_hart1) {
+        // Initialize sync counters
+        scp_signal(ready_ctr, 0);
+        scp_signal(consumed_ctr, 0);
+
+        uint32_t chunk_id = 0;
+
+        for (int64_t tile = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES; tile < base_tiles;
+             tile += tiles_stride) {
+            const int64_t tiles_per_batch = m_tiles * n_tiles;
+            const int64_t batch_idx       = tile / tiles_per_batch;
+            const int64_t tile_in_batch   = tile % tiles_per_batch;
+
+            const int64_t mb_idx = tile_in_batch % m_tiles;
+
+            const int64_t i3   = batch_idx / ne2_1;
+            const int64_t i2   = batch_idx % ne2_1;
+            const int64_t i2_0 = i2 / r2;
+            const int64_t i3_0 = i3 / r3;
+
+            const char *  src0_batch = src0_base + i3_0 * nb3_0 + i2_0 * nb2_0;
+            const int64_t mb         = mb_idx * TILE_M;
+
+            for (int64_t kb = k_start; kb < k_end; kb += TILE_K) {
+                int buf = chunk_id & 1;
+
+                // Back-pressure: wait for hart 0 to finish with this buffer
+                if (chunk_id >= 2) {
+                    scp_wait(consumed_ctr, chunk_id - 1);
+                }
+
+                pack_b_interleaved(scp_bp[buf], src0_batch, mb, kb, nb1_0);
+
+                FENCE;
+                flush_to_l2(scp_bp[buf], 16, 64);
+                WAIT_CACHEOPS;
+
+                chunk_id++;
+                scp_signal(ready_ctr, chunk_id);
+            }
+        }
+
+        FENCE;
+        return 0;
+    }
+
+    // ================================================================
+    // Hart 0: tensor engine compute
+    // ================================================================
+    uint64_t       my_minion_id      = get_minion_id();
+    const uint64_t group_base_global = my_minion_id - k_split;
+
+    setup_cache_scp();
+#if CACHEOP_MAX > 0 || REP_RATE > 0
+    ucache_control(1, REP_RATE, CACHEOP_MAX);
+#endif
+    CLEAR_TENSOR_ERROR;
+
+    // Evict any stale L1D copies of sync counters
+    evict_to_l2((const void *) ready_ctr, 1, 64);
+    WAIT_CACHEOPS;
+    evict_to_l2((const void *) consumed_ctr, 1, 64);
+    WAIT_CACHEOPS;
+
+    uint32_t chunk_id = 0;
+
+    for (int64_t tile = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES; tile < base_tiles;
+         tile += tiles_stride) {
+        const int64_t tiles_per_batch = m_tiles * n_tiles;
+        const int64_t batch_idx       = tile / tiles_per_batch;
+        const int64_t tile_in_batch   = tile % tiles_per_batch;
+
+        const int64_t nb_idx = tile_in_batch / m_tiles;
+        const int64_t mb_idx = tile_in_batch % m_tiles;
+
+        const int64_t i3 = batch_idx / ne2_1;
+        const int64_t i2 = batch_idx % ne2_1;
+
+        const char * src1_batch = src1_base + i3 * nb3_1 + i2 * nb2_1;
+        char *       dst_batch  = dst_base + i3 * nb3_d + i2 * nb2_d;
+
+        const int64_t mb    = mb_idx * TILE_M;
+        const int64_t nb    = nb_idx * TILE_N;
+        const int64_t n_cur = (nb + TILE_N <= N) ? TILE_N : (N - nb);
+
+        // Set tensor_mask for partial N tiles
+        if (n_cur < TILE_N) {
+            uint64_t mask = (1ULL << n_cur) - 1;
+            __asm__ __volatile__("csrw 0x805, %0" : : "r"(mask));
+        }
+
+        for (int64_t kb = k_start; kb < k_end; kb += TILE_K) {
+            int buf = chunk_id & 1;
+
+            // Start loading A from DRAM (overlaps with waiting for hart 1)
+            tensor_load((n_cur < TILE_N), false, A_L1_START, TENSOR_LOAD_PLAIN, 0,
+                        (uint64_t) (src1_batch + nb * nb1_1 + kb * (int64_t) sizeof(et_fp16_t)), 0, n_cur - 1,
+                        (uint64_t) nb1_1, 0);
+
+            // Wait for hart 1 to finish packing this chunk
+            chunk_id++;
+            scp_wait(ready_ctr, chunk_id);
+
+            // Load B from L2 SCP (hart 1 already flushed it)
+            tensor_load(false, false, B_L1_START, TENSOR_LOAD_PLAIN, 0, (uint64_t) scp_bp[buf], 0, 15, 64, 1);
+
+            tensor_wait(TENSOR_LOAD_WAIT_0);
+            tensor_wait(TENSOR_LOAD_WAIT_1);
+
+            // TensorFMA16A32
+            tensor_fma((n_cur < TILE_N), 3, n_cur - 1, 15, 0, false, false, false, false, B_L1_START, A_L1_START,
+                       TENSOR_FMA_OP_FP16, (kb == k_start));
+
+            tensor_wait(TENSOR_FMA_WAIT);
+
+            // Signal that this buffer is free for hart 1 to reuse
+            scp_signal(consumed_ctr, chunk_id);
+        }
+
+        // K-split ring reduce
+        if (k_splits > 1) {
+            const uint64_t num_regs = (uint64_t) n_cur * 2;
+
+            if (k_split > 0) {
+                tensor_reduce_recv(0, TENSOR_REDUCE_OP_FADD, num_regs, group_base_global + k_split - 1);
+                tensor_wait(TENSOR_REDUCE_WAIT);
+            }
+
+            if (k_split < k_splits - 1) {
+                tensor_reduce_send(0, num_regs, group_base_global + k_split + 1);
+                tensor_wait(TENSOR_REDUCE_WAIT);
+            }
+        }
+
+        // Store FP32 result tile
+        if (k_split == k_splits - 1) {
+            tensor_store(0, 0, 3, n_cur - 1, (uint64_t) (dst_batch + nb * nb1_d + mb * (int64_t) sizeof(float)), 0,
+                         (uint64_t) nb1_d);
+            tensor_wait(TENSOR_STORE_WAIT);
+        }
+    }
+
+    FENCE;
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_f32.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_f32.c
new file mode 100644 (file)
index 0000000..107bc50
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_f32.c
@@ -0,0 +1,137 @@
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+#include <stdio.h>
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env || params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    // Thread coordination
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0 || (thread_id & 1)) {
+        return 0;  // Skip odd threads to avoid resource contention
+    }
+
+    int effective_thread_id   = thread_id / 2;
+    int effective_num_threads = (num_threads + 1) / 2;
+
+    // Extract tensor references
+    struct ggml_tensor * src0 = &params->src0;  // Weight matrix A (F32)
+    struct ggml_tensor * src1 = &params->src1;  // Activation matrix B (F16/F32)
+    struct ggml_tensor * dst  = &params->dst;   // Output matrix C (F32)
+
+    // Generic non-matrix-engine path: F32 x (F16/F32) -> F32
+    if (src0->type != GGML_TYPE_F32 || (src1->type != GGML_TYPE_F16 && src1->type != GGML_TYPE_F32) ||
+        dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float * src0_data = (const float *) src0->data;
+    float *       dst_data  = (float *) dst->data;
+
+    // Dimensions and Strides
+    const int64_t K = src0->ne[0];
+    const int64_t M = src0->ne[1];
+    const int64_t N = src1->ne[1];
+
+    const int64_t ne02 = src0->ne[2], ne03 = src0->ne[3];
+    const int64_t ne12 = src1->ne[2], ne13 = src1->ne[3];
+    const int64_t ne2 = dst->ne[2], ne3 = dst->ne[3];
+
+    const size_t nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    const size_t nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3];
+    const size_t nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+
+    // F32 specific block size and counts
+    const int     block_size  = QK_F32;
+    const int64_t K_blocks    = K / block_size;
+    const int64_t K_remainder = K % block_size;
+
+    // Threading distribution
+    const uint64_t total_elements = M * N * ne2 * ne3;
+    const uint64_t per_thread     = 16;
+    const uint64_t threads_stride = per_thread * effective_num_threads;
+
+    if (effective_thread_id * per_thread >= total_elements) {
+        return 0;
+    }
+
+    // Broadcasting support
+    const int64_t r2 = ne12 / ne02;
+    const int64_t r3 = ne13 / ne03;
+
+    for (uint64_t base_idx = effective_thread_id * per_thread; base_idx < total_elements; base_idx += threads_stride) {
+        for (uint64_t j = 0; j < per_thread; j++) {
+            const uint64_t idx = base_idx + j;
+            if (idx >= total_elements) {
+                break;
+            }
+
+            // Index decoding
+            const int64_t i3   = idx / (M * N * ne2);
+            const int64_t rem3 = idx % (M * N * ne2);
+            const int64_t i2   = rem3 / (M * N);
+            const int64_t rem2 = rem3 % (M * N);
+            const int64_t n    = rem2 / M;
+            const int64_t m    = rem2 % M;
+
+            const int64_t i03 = i3 / r3, i02 = i2 / r2;
+            const int64_t i13 = (ne13 > 1) ? i3 : 0, i12 = (ne12 > 1) ? i2 : 0;
+
+            float         sum     = 0.0f;
+            const float * f32_row = (const float *) ((const char *) src0_data + m * nb01 + i02 * nb02 + i03 * nb03);
+
+            if (src1->type == GGML_TYPE_F32) {
+                const float * src1_data = (const float *) src1->data;
+
+                for (int64_t kb = 0; kb < K_blocks; kb++) {
+                    const float * b_col_ptr =
+                        (const float *) ((const char *) src1_data + (kb * block_size) * sizeof(float) + n * nb11 +
+                                         i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f32(&f32_row[kb * block_size], b_col_ptr);
+                }
+
+                if (K_remainder > 0) {
+                    const int64_t offset    = K_blocks * block_size;
+                    const float * b_col_ptr = (const float *) ((const char *) src1_data + offset * sizeof(float) +
+                                                               n * nb11 + i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f32_partial(&f32_row[offset], b_col_ptr, K_remainder);
+                }
+            } else {
+                const uint16_t * src1_data = (const uint16_t *) src1->data;
+
+                for (int64_t kb = 0; kb < K_blocks; kb++) {
+                    const uint16_t * b_col_ptr =
+                        (const uint16_t *) ((const char *) src1_data + (kb * block_size) * sizeof(uint16_t) + n * nb11 +
+                                            i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f32_f16_partial(&f32_row[kb * block_size], b_col_ptr, block_size);
+                }
+
+                if (K_remainder > 0) {
+                    const int64_t    offset = K_blocks * block_size;
+                    const uint16_t * b_col_ptr =
+                        (const uint16_t *) ((const char *) src1_data + offset * sizeof(uint16_t) + n * nb11 +
+                                            i12 * nb12 + i13 * nb13);
+                    sum += compute_block_dot_product_f32_f16_partial(&f32_row[offset], b_col_ptr, K_remainder);
+                }
+            }
+
+            // Atomic store for output
+            volatile float * c_element =
+                (volatile float *) ((char *) dst_data + m * dst->nb[0] + n * nb1 + i2 * nb2 + i3 * nb3);
+            atomic_store_f32(c_element, sum);
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_f32_matrix_engine.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_f32_matrix_engine.c
new file mode 100644 (file)
index 0000000..b2b61d5
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_f32_matrix_engine.c
@@ -0,0 +1,155 @@
+#include "ggml_tensor.h"
+#include "platform.h"
+#include "tensor.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+
+/*
+ * F32 Matrix Multiply for ET-SoC-1 — TensorFMA32.
+ *
+ * K-parallel + interleaved tiles + ring reduce.
+ * No batched-K yet (needs investigation on hang).
+ * This is the last known working version.
+ */
+
+#define NUM_COMPUTE_SHIRES 32
+#define MINIONS_PER_SHIRE  32
+#define TILE_K             16
+#define TILE_M             16
+
+/* ── Tuning knobs ───────────────────────────────────────────────────── */
+#define TILE_N      16
+#define CACHEOP_MAX 0
+#define REP_RATE    0
+
+/* ─────────────────────────────────────────────────────────────────── */
+
+int entry_point(struct ggml_et_binary_params * params, void * env) {
+    uint64_t hart_id  = get_hart_id();
+    uint64_t shire_id = get_shire_id();
+
+    if (shire_id >= NUM_COMPUTE_SHIRES) {
+        return 0;
+    }
+    if (hart_id & 1) {
+        return 0;
+    }
+
+    uint64_t local_minion = (hart_id >> 1) & 0x1F;
+    uint64_t my_minion_id = get_minion_id();
+
+    const int64_t K = params->src0.ne[0];
+    const int64_t M = params->src0.ne[1];
+    const int64_t N = params->src1.ne[1];
+
+    const int64_t ne2_0 = params->src0.ne[2], ne3_0 = params->src0.ne[3];
+    const int64_t ne2_1 = params->src1.ne[2], ne3_1 = params->src1.ne[3];
+
+    const int64_t nb1_0 = params->src0.nb[1];
+    const int64_t nb2_0 = params->src0.nb[2], nb3_0 = params->src0.nb[3];
+    const int64_t nb1_1 = params->src1.nb[1];
+    const int64_t nb2_1 = params->src1.nb[2], nb3_1 = params->src1.nb[3];
+    const int64_t nb1_d = params->dst.nb[1];
+    const int64_t nb2_d = params->dst.nb[2], nb3_d = params->dst.nb[3];
+
+    const char * src0_base = (const char *) params->src0.data;
+    const char * src1_base = (const char *) params->src1.data;
+    char *       dst_base  = (char *) params->dst.data;
+
+    setup_cache_scp();
+#if CACHEOP_MAX > 0 || REP_RATE > 0
+    ucache_control(1, REP_RATE, CACHEOP_MAX);
+#endif
+    CLEAR_TENSOR_ERROR;
+
+    const int64_t m_tiles     = M / TILE_M;
+    const int64_t n_tiles     = (N + TILE_N - 1) / TILE_N;
+    const int64_t batch_count = ne2_1 * ne3_1;
+    const int64_t base_tiles  = m_tiles * n_tiles * batch_count;
+
+    const int64_t r2 = ne2_1 / ne2_0;
+    const int64_t r3 = ne3_1 / ne3_0;
+
+    const int64_t total_harts = NUM_COMPUTE_SHIRES * MINIONS_PER_SHIRE;
+    const int64_t k_steps     = K / TILE_K;
+    int64_t       k_splits    = 1;
+    if (base_tiles < total_harts) {
+        k_splits   = (total_harts + base_tiles - 1) / base_tiles;
+        int64_t ks = 1;
+        while (ks * 2 <= k_splits && ks * 2 <= 32 && k_steps % (ks * 2) == 0) {
+            ks *= 2;
+        }
+        k_splits = ks;
+    }
+
+    const int64_t tiles_per_shire = MINIONS_PER_SHIRE / k_splits;
+    const int64_t k_split         = local_minion % k_splits;
+    const int64_t local_tile_idx  = local_minion / k_splits;
+    const int64_t tiles_stride    = (int64_t) NUM_COMPUTE_SHIRES * tiles_per_shire;
+
+    const int64_t k_steps_per_split = k_steps / k_splits;
+    const int64_t k_start           = k_split * k_steps_per_split * TILE_K;
+    const int64_t k_end             = k_start + k_steps_per_split * TILE_K;
+
+    const uint64_t group_base_global = my_minion_id - k_split;
+
+    for (int64_t tile = (int64_t) shire_id + local_tile_idx * NUM_COMPUTE_SHIRES; tile < base_tiles;
+         tile += tiles_stride) {
+        const int64_t tiles_per_batch = m_tiles * n_tiles;
+        const int64_t batch_idx       = tile / tiles_per_batch;
+        const int64_t tile_in_batch   = tile % tiles_per_batch;
+        const int64_t nb_idx          = tile_in_batch / m_tiles;
+        const int64_t mb_idx          = tile_in_batch % m_tiles;
+
+        const int64_t i3   = batch_idx / ne2_1;
+        const int64_t i2   = batch_idx % ne2_1;
+        const int64_t i2_0 = i2 / r2;
+        const int64_t i3_0 = i3 / r3;
+
+        const char * src0_batch = src0_base + i3_0 * nb3_0 + i2_0 * nb2_0;
+        const char * src1_batch = src1_base + i3 * nb3_1 + i2 * nb2_1;
+        char *       dst_batch  = dst_base + i3 * nb3_d + i2 * nb2_d;
+
+        const int64_t mb    = mb_idx * TILE_M;
+        const int64_t nb    = nb_idx * TILE_N;
+        const int64_t n_cur = (nb + TILE_N <= N) ? TILE_N : (N - nb);
+
+        for (int64_t kb = k_start; kb < k_end; kb += TILE_K) {
+            tensor_load(false, false, 0, 0, 0, (uint64_t) (src1_batch + nb * nb1_1 + kb * sizeof(float)), 0, n_cur - 1,
+                        (uint64_t) nb1_1, 0);
+
+            tensor_load(false, false, TILE_K, 7, 0, (uint64_t) (src0_batch + mb * nb1_0 + kb * sizeof(float)), 0,
+                        TILE_K - 1, (uint64_t) nb1_0, 1);
+
+            tensor_wait(TENSOR_LOAD_WAIT_0);
+            tensor_wait(TENSOR_LOAD_WAIT_1);
+
+            tensor_fma(false, 3, n_cur - 1, TILE_K - 1, 0, false, false, false, false, TILE_K, 0, 0, (kb == k_start));
+
+            tensor_wait(TENSOR_FMA_WAIT);
+        }
+
+        if (k_splits > 1) {
+            const uint64_t num_regs = (uint64_t) n_cur * 2;
+
+            if (k_split > 0) {
+                tensor_reduce_recv(0, TENSOR_REDUCE_OP_FADD, num_regs, group_base_global + k_split - 1);
+                tensor_wait(TENSOR_REDUCE_WAIT);
+            }
+            if (k_split < k_splits - 1) {
+                tensor_reduce_send(0, num_regs, group_base_global + k_split + 1);
+                tensor_wait(TENSOR_REDUCE_WAIT);
+            }
+        }
+
+        if (k_split == k_splits - 1) {
+            tensor_store(0, 0, 3, n_cur - 1, (uint64_t) (dst_batch + nb * nb1_d + mb * sizeof(float)), 0,
+                         (uint64_t) nb1_d);
+            tensor_wait(TENSOR_STORE_WAIT);
+        }
+    }
+
+    FENCE;
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_id_Q4_0.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_id_Q4_0.c
new file mode 100644 (file)
index 0000000..3685c25
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_id_Q4_0.c
@@ -0,0 +1,169 @@
+//******************************************************************************
+// MUL_MAT_ID kernel specialized for Q4_0 weights (Mixture of Experts).
+//
+// C[m, s, b] = Sum(k=0..K-1) A[k, m, ids[s,b]] * B[k, s % ne11, b]
+//   A: Q4_0  [K, M, n_expert]   weights
+//   B: F32   [K, n_cols, batch] activations
+//   ids: I32 [n_expert_used, batch]
+//   C: F32   [M, n_expert_used, batch]
+//
+// Strategy: All harts active. Flat m-major output partition allows amortized
+// expert lookups and 2-row x2 dot products.
+//******************************************************************************
+
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <stdint.h>
+
+int entry_point(struct ggml_et_mul_mat_id_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+    if (!kernel_env || !params) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * src2 = &params->src2;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_Q4_0 || src1->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_I32 ||
+        dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const void *    src0_data = src0->data;
+    const float *   src1_data = (const float *) src1->data;
+    const int32_t * src2_data = (const int32_t *) src2->data;
+    float *         dst_data  = (float *) dst->data;
+    if (!src0_data || !src1_data || !src2_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t K             = src0->ne[0];
+    const int64_t M             = src0->ne[1];
+    const int64_t n_expert      = src0->ne[2];
+    const int64_t n_expert_used = src2->ne[0];
+    const int64_t batch         = src2->ne[1];
+    const int64_t ne11          = src1->ne[1];
+
+    if (K % QK4_0 != 0) {
+        return -1;
+    }
+
+    const size_t nb01 = src0->nb[1];  // Q4_0 row stride
+    const size_t nb02 = src0->nb[2];  // expert stride
+    const size_t nb11 = src1->nb[1];  // activation column stride
+    const size_t nb12 = src1->nb[2];  // activation batch stride
+    const size_t nb20 = src2->nb[0];
+    const size_t nb21 = src2->nb[1];
+    const size_t nbd0 = dst->nb[0];
+    const size_t nbd1 = dst->nb[1];
+    const size_t nbd2 = dst->nb[2];
+
+    if (src0->nb[0] != sizeof(block_q4_0) || src1->nb[0] != sizeof(float) || src2->nb[0] != sizeof(int32_t) ||
+        nbd0 != sizeof(float)) {
+        return -1;
+    }
+
+    const int64_t K_blocks = K / QK4_0;
+    const int     use_x2   = ((nb01 & 31) == 0);
+
+    const uint64_t total_outputs = (uint64_t) M * (uint64_t) n_expert_used * (uint64_t) batch;
+    if (total_outputs == 0) {
+        return 0;
+    }
+
+    // Even partition: hart h owns outputs [h*chunk, (h+1)*chunk).
+    const uint64_t chunk    = (total_outputs + (uint64_t) num_threads - 1) / (uint64_t) num_threads;
+    const uint64_t my_start = (uint64_t) thread_id * chunk;
+    if (my_start >= total_outputs) {
+        return 0;
+    }
+    uint64_t my_end = my_start + chunk;
+    if (my_end > total_outputs) {
+        my_end = total_outputs;
+    }
+
+    // Save mask register once; full lanes for vector dot.
+    q4_dot_state q4_state;
+    q4_dot_begin(&q4_state);
+
+    const uint64_t per_batch = (uint64_t) M * (uint64_t) n_expert_used;
+
+    uint64_t idx = my_start;
+    while (idx < my_end) {
+        // Decode (m, slot, batch) from the m-major linear index.
+        const int64_t  batch_idx = (int64_t) (idx / per_batch);
+        const uint64_t rem       = idx - (uint64_t) batch_idx * per_batch;
+        const int64_t  slot_idx  = (int64_t) (rem / (uint64_t) M);
+        const int64_t  m0        = (int64_t) (rem - (uint64_t) slot_idx * (uint64_t) M);
+
+        // How many outputs left in this (slot, batch) run AND in my range.
+        const uint64_t run_end_global =
+            (uint64_t) batch_idx * per_batch + (uint64_t) slot_idx * (uint64_t) M + (uint64_t) M;
+        const uint64_t end_in_my = (run_end_global < my_end) ? run_end_global : my_end;
+        int64_t        run_len   = (int64_t) (end_in_my - idx);
+
+        // Resolve expert + B column + dst slot for this run.
+        const int32_t expert_id =
+            *(const int32_t *) ((const char *) src2_data + slot_idx * (int64_t) nb20 + batch_idx * (int64_t) nb21);
+
+        char * dst_slot = (char *) dst_data + slot_idx * (int64_t) nbd1 + batch_idx * (int64_t) nbd2;
+
+        if (expert_id < 0 || expert_id >= n_expert) {
+            // Invalid expert id — zero out this run's outputs.
+            int64_t m = m0;
+            for (int64_t i = 0; i < run_len; i++, m++) {
+                atomic_store_f32((volatile float *) (dst_slot + m * (int64_t) nbd0), 0.0f);
+            }
+            idx += (uint64_t) run_len;
+            continue;
+        }
+
+        const int64_t col_idx = slot_idx % ne11;
+        const float * b_col_base =
+            (const float *) ((const char *) src1_data + col_idx * (int64_t) nb11 + batch_idx * (int64_t) nb12);
+        const char * expert_base = (const char *) src0_data + expert_id * (int64_t) nb02;
+
+        int64_t m    = m0;
+        int64_t left = run_len;
+
+        // Paired-row dots: halves B bandwidth for runs >= 2.
+        if (use_x2) {
+            while (left >= 2) {
+                const block_q4_0 * row0 = (const block_q4_0 *) (expert_base + m * (int64_t) nb01);
+                const block_q4_0 * row1 = (const block_q4_0 *) (expert_base + (m + 1) * (int64_t) nb01);
+                float              s0, s1;
+                q4_dot_compute_x2_aligned(row0, row1, b_col_base, K_blocks, &s0, &s1);
+                atomic_store_f32((volatile float *) (dst_slot + m * (int64_t) nbd0), s0);
+                atomic_store_f32((volatile float *) (dst_slot + (m + 1) * (int64_t) nbd0), s1);
+                m += 2;
+                left -= 2;
+            }
+        }
+
+        // Tail / non-aligned fallback: single-row dots.
+        while (left > 0) {
+            const block_q4_0 * row = (const block_q4_0 *) (expert_base + m * (int64_t) nb01);
+            float              s   = q4_dot_compute(row, b_col_base, K_blocks);
+            atomic_store_f32((volatile float *) (dst_slot + m * (int64_t) nbd0), s);
+            m++;
+            left--;
+        }
+
+        idx += (uint64_t) run_len;
+    }
+
+    q4_dot_end(&q4_state);
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_id_Q8_0.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_id_Q8_0.c
new file mode 100644 (file)
index 0000000..d077a00
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_id_Q8_0.c
@@ -0,0 +1,160 @@
+//******************************************************************************
+// MUL_MAT_ID kernel specialized for Q8_0 weights (Mixture of Experts).
+//
+// C[m, s, b] = Sum(k=0..K-1) A[k, m, ids[s,b]] * B[k, s % ne11, b]
+//   A: Q8_0  [K, M, n_expert]   weights
+//   B: F32   [K, n_cols, batch] activations
+//   ids: I32 [n_expert_used, batch]
+//   C: F32   [M, n_expert_used, batch]
+//
+// Strategy mirrors mul_mat_id_Q4_0.c.
+//******************************************************************************
+
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <stdint.h>
+
+int entry_point(struct ggml_et_mul_mat_id_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+    if (!kernel_env || !params) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * src2 = &params->src2;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_Q8_0 || src1->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_I32 ||
+        dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const void *    src0_data = src0->data;
+    const float *   src1_data = (const float *) src1->data;
+    const int32_t * src2_data = (const int32_t *) src2->data;
+    float *         dst_data  = (float *) dst->data;
+    if (!src0_data || !src1_data || !src2_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t K             = src0->ne[0];
+    const int64_t M             = src0->ne[1];
+    const int64_t n_expert      = src0->ne[2];
+    const int64_t n_expert_used = src2->ne[0];
+    const int64_t batch         = src2->ne[1];
+    const int64_t ne11          = src1->ne[1];
+
+    if (K % QK8_0 != 0) {
+        return -1;
+    }
+
+    const size_t nb01 = src0->nb[1];
+    const size_t nb02 = src0->nb[2];
+    const size_t nb11 = src1->nb[1];
+    const size_t nb12 = src1->nb[2];
+    const size_t nb20 = src2->nb[0];
+    const size_t nb21 = src2->nb[1];
+    const size_t nbd0 = dst->nb[0];
+    const size_t nbd1 = dst->nb[1];
+    const size_t nbd2 = dst->nb[2];
+
+    if (src0->nb[0] != sizeof(block_q8_0) || src1->nb[0] != sizeof(float) || src2->nb[0] != sizeof(int32_t) ||
+        nbd0 != sizeof(float)) {
+        return -1;
+    }
+
+    const int64_t K_blocks = K / QK8_0;
+    const int     use_x2   = ((nb01 & 31) == 0);
+
+    const uint64_t total_outputs = (uint64_t) M * (uint64_t) n_expert_used * (uint64_t) batch;
+    if (total_outputs == 0) {
+        return 0;
+    }
+
+    const uint64_t chunk    = (total_outputs + (uint64_t) num_threads - 1) / (uint64_t) num_threads;
+    const uint64_t my_start = (uint64_t) thread_id * chunk;
+    if (my_start >= total_outputs) {
+        return 0;
+    }
+    uint64_t my_end = my_start + chunk;
+    if (my_end > total_outputs) {
+        my_end = total_outputs;
+    }
+
+    q8_dot_state q8_state;
+    q8_dot_begin(&q8_state);
+
+    const uint64_t per_batch = (uint64_t) M * (uint64_t) n_expert_used;
+
+    uint64_t idx = my_start;
+    while (idx < my_end) {
+        const int64_t  batch_idx = (int64_t) (idx / per_batch);
+        const uint64_t rem       = idx - (uint64_t) batch_idx * per_batch;
+        const int64_t  slot_idx  = (int64_t) (rem / (uint64_t) M);
+        const int64_t  m0        = (int64_t) (rem - (uint64_t) slot_idx * (uint64_t) M);
+
+        const uint64_t run_end_global =
+            (uint64_t) batch_idx * per_batch + (uint64_t) slot_idx * (uint64_t) M + (uint64_t) M;
+        const uint64_t end_in_my = (run_end_global < my_end) ? run_end_global : my_end;
+        int64_t        run_len   = (int64_t) (end_in_my - idx);
+
+        const int32_t expert_id =
+            *(const int32_t *) ((const char *) src2_data + slot_idx * (int64_t) nb20 + batch_idx * (int64_t) nb21);
+
+        char * dst_slot = (char *) dst_data + slot_idx * (int64_t) nbd1 + batch_idx * (int64_t) nbd2;
+
+        if (expert_id < 0 || expert_id >= n_expert) {
+            int64_t m = m0;
+            for (int64_t i = 0; i < run_len; i++, m++) {
+                atomic_store_f32((volatile float *) (dst_slot + m * (int64_t) nbd0), 0.0f);
+            }
+            idx += (uint64_t) run_len;
+            continue;
+        }
+
+        const int64_t col_idx = slot_idx % ne11;
+        const float * b_col_base =
+            (const float *) ((const char *) src1_data + col_idx * (int64_t) nb11 + batch_idx * (int64_t) nb12);
+        const char * expert_base = (const char *) src0_data + expert_id * (int64_t) nb02;
+
+        int64_t m    = m0;
+        int64_t left = run_len;
+
+        if (use_x2) {
+            while (left >= 2) {
+                const block_q8_0 * row0 = (const block_q8_0 *) (expert_base + m * (int64_t) nb01);
+                const block_q8_0 * row1 = (const block_q8_0 *) (expert_base + (m + 1) * (int64_t) nb01);
+                float              s0, s1;
+                q8_dot_compute_x2_aligned(row0, row1, b_col_base, K_blocks, &s0, &s1);
+                atomic_store_f32((volatile float *) (dst_slot + m * (int64_t) nbd0), s0);
+                atomic_store_f32((volatile float *) (dst_slot + (m + 1) * (int64_t) nbd0), s1);
+                m += 2;
+                left -= 2;
+            }
+        }
+
+        while (left > 0) {
+            const block_q8_0 * row = (const block_q8_0 *) (expert_base + m * (int64_t) nb01);
+            float              s   = q8_dot_compute(row, b_col_base, K_blocks);
+            atomic_store_f32((volatile float *) (dst_slot + m * (int64_t) nbd0), s);
+            m++;
+            left--;
+        }
+
+        idx += (uint64_t) run_len;
+    }
+
+    q8_dot_end(&q8_state);
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/mul_mat_id_f32.c b/ggml/src/ggml-et/et-kernels/src/mul_mat_id_f32.c
new file mode 100644 (file)
index 0000000..900aa0c
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/mul_mat_id_f32.c
@@ -0,0 +1,288 @@
+//******************************************************************************
+// Bare Metal MUL_MAT_ID Kernel (Mixture of Experts)
+//
+// ALGORITHM:
+// MUL_MAT_ID performs batched matrix multiplication with expert routing.
+// Each output element selects which expert matrix to use based on an index tensor.
+//
+// INPUTS:
+//   src0 (as):  Expert weight matrices [K, M, n_expert]
+//               - Stack of n_expert matrices, each of size [K, M]
+//   src1 (b):   Activation vectors [K, n_cols, batch]
+//               - n_cols can be 1 (broadcast) or n_expert_used (per-expert inputs)
+//   src2 (ids): Expert selection indices [n_expert_used, batch] (int32)
+//               - For each (slot, batch), specifies which expert from src0 to use
+//
+// OUTPUT:
+//   dst:        Result [M, n_expert_used, batch, 1]
+//
+// COMPUTATION:
+//   For each output position (m, slot, batch):
+//     expert_id = ids[slot, batch]           // Which expert to use (0..n_expert-1)
+//     col_idx = slot % src1.ne[1]            // Which column in src1 (handles broadcasting)
+//     dst[m, slot, batch] = dot_product(
+//       src0[0:K, m, expert_id],             // Row m from selected expert matrix
+//       src1[0:K, col_idx, batch]            // Column from activations (may broadcast)
+//     )
+//
+// BROADCASTING:
+//   - When src1.ne[1] == 1: All expert slots use the same activation column
+//   - When src1.ne[1] == n_expert_used: Each slot has its own activation column
+//   - General case: col_idx = slot % src1.ne[1] (modulo handles both cases)
+//
+// MATH NOTATION:
+//   C[m, s, b] = Sum(k=0 to K-1) A[k, m, ids[s,b]] x B[k, s % ne11, b]
+//   where:
+//     m: [0, M)               - output feature index
+//     s: [0, n_expert_used)   - expert slot index
+//     b: [0, batch)           - batch index
+//     k: [0, K)               - hidden dimension
+//     ne11 = src1->ne[1]       - number of columns in src1
+//******************************************************************************
+
+#include "block_ops.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+#include "quants.h"
+
+#include <stdint.h>
+
+// Main entry point for MUL_MAT_ID kernel (Mixture of Experts)
+int entry_point(struct ggml_et_mul_mat_id_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    // Get thread coordination info
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return -1;
+    }
+
+    // Use even threads only to avoid resource contention
+    // Each minion has 2 threads sharing instruction/data cache, NOC to RAM, and FPU
+    // Odd threads return immediately to avoid fighting for shared resources
+    if (thread_id & 1) {
+        return 0;  // Odd thread - skip work
+    }
+
+    // Adjust thread count and ID for even-only threading
+    int effective_thread_id   = thread_id / 2;
+    int effective_num_threads = (num_threads + 1) / 2;  // Ceiling division
+
+    // Validate params
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    // Extract tensor references
+    struct ggml_tensor * src0 = &params->src0;  // Expert weight matrices [K, M, n_expert]
+    struct ggml_tensor * src1 = &params->src1;  // Activations [K, n_expert_used, batch]
+    struct ggml_tensor * src2 = &params->src2;  // Expert indices [n_expert_used, batch] (I32)
+    struct ggml_tensor * dst  = &params->dst;   // Output [M, n_expert_used, batch, 1]
+
+    // Validate tensor types
+    if (src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_I32) {
+        return -1;
+    }
+
+    // Get data pointers
+    const void *    src0_data = src0->data;                    // Expert matrices (Q8_0/F16/F32)
+    const float *   src1_data = (const float *) src1->data;    // Activations (F32)
+    const int32_t * src2_data = (const int32_t *) src2->data;  // Expert IDs (I32)
+    float *         dst_data  = (float *) dst->data;           // Output (F32)
+
+    if (!src0_data || !src1_data || !src2_data || !dst_data) {
+        return -1;
+    }
+
+    // Determine block size based on src0 type
+    int block_size;
+    switch (src0->type) {
+        case GGML_TYPE_Q8_0:
+            block_size = QK8_0;
+            break;
+        case GGML_TYPE_Q4_0:
+            block_size = QK4_0;
+            break;
+        case GGML_TYPE_F16:
+            block_size = QK_F16;
+            break;
+        case GGML_TYPE_F32:
+            block_size = QK_F32;
+            break;
+        default:
+            return -1;
+    }
+
+    // Get dimensions
+    // src0: [K, M, n_expert] - expert weight matrices
+    // src1: [K, n_expert_used, batch] - activations
+    // src2: [n_expert_used, batch] - expert indices
+    // dst:  [M, n_expert_used, batch, 1] - output
+    const int64_t K             = src0->ne[0];  // Hidden dimension
+    const int64_t M             = src0->ne[1];  // Output features
+    const int64_t n_expert      = src0->ne[2];  // Number of experts
+    const int64_t n_expert_used = src2->ne[0];  // Experts used per token
+    const int64_t batch         = src2->ne[1];  // Batch size
+
+    // Strides (in bytes)
+    const size_t nb01 = src0->nb[1];  // src0 row stride
+    const size_t nb02 = src0->nb[2];  // src0 expert stride
+    const size_t nb11 = src1->nb[1];  // src1 column stride
+    const size_t nb12 = src1->nb[2];  // src1 batch stride
+    const size_t nb20 = src2->nb[0];  // src2 element stride
+    const size_t nb21 = src2->nb[1];  // src2 batch stride
+    const size_t nb1  = dst->nb[1];   // dst column stride
+    const size_t nb2  = dst->nb[2];   // dst batch stride
+
+    // Verify K dimension alignment for quantization
+    // Q8_0 requires strict alignment (quantized data must be block-aligned)
+    // F32 and F16 can handle partial blocks with scalar remainders
+    if ((src0->type == GGML_TYPE_Q8_0 || src0->type == GGML_TYPE_Q4_0) && K % block_size != 0) {
+        return -1;  // Q8_0 requires K to be multiple of block_size
+    }
+
+    // Verify first dimension is contiguous
+    size_t expected_element_size_src0;
+    if (src0->type == GGML_TYPE_Q8_0) {
+        expected_element_size_src0 = sizeof(block_q8_0);
+    } else if (src0->type == GGML_TYPE_Q4_0) {
+        expected_element_size_src0 = sizeof(block_q4_0);
+    } else if (src0->type == GGML_TYPE_F16) {
+        expected_element_size_src0 = sizeof(uint16_t);
+    } else if (src0->type == GGML_TYPE_F32) {
+        expected_element_size_src0 = sizeof(float);
+    } else {
+        return -1;
+    }
+
+    if (src0->nb[0] != expected_element_size_src0 || src1->nb[0] != sizeof(float) || src2->nb[0] != sizeof(int32_t) ||
+        dst->nb[0] != sizeof(float)) {
+        return -1;
+    }
+
+    const int64_t K_blocks = K / block_size;
+
+    // Threading: distribute output elements across threads
+    // Total output elements = M * n_expert_used * batch
+    const uint64_t total_elements = M * n_expert_used * batch;
+
+    const uint64_t per_thread     = 16;
+    const uint64_t threads_stride = per_thread * effective_num_threads;
+
+    if (effective_thread_id * per_thread >= total_elements) {
+        return 0;
+    }
+
+    // Process elements assigned to this thread
+    for (uint64_t base_idx = effective_thread_id * per_thread; base_idx < total_elements; base_idx += threads_stride) {
+        for (uint64_t j = 0; j < per_thread; j++) {
+            const uint64_t idx = base_idx + j;
+
+            if (idx >= total_elements) {
+                break;
+            }
+
+            // Decode linear index to (m, n_idx, batch_idx)
+            // Layout: m + M * (n_idx + n_expert_used * batch_idx)
+            const int64_t batch_idx = idx / (M * n_expert_used);
+            const int64_t rem       = idx % (M * n_expert_used);
+            const int64_t n_idx     = rem / M;
+            const int64_t m         = rem % M;
+
+            // Get expert ID from src2[n_idx, batch_idx]
+            const int32_t expert_id = *(const int32_t *) ((const char *) src2_data + n_idx * nb20 + batch_idx * nb21);
+
+            // Validate expert ID
+            if (expert_id < 0 || expert_id >= n_expert) {
+                // Invalid expert ID - write zero and continue
+                volatile float * dst_element =
+                    (volatile float *) ((char *) dst_data + m * dst->nb[0] + n_idx * nb1 + batch_idx * nb2);
+                atomic_store_f32(dst_element, 0.0f);
+                continue;
+            }
+
+            // Compute dot product: expert_matrix[m, :] x activations[:, col_idx, batch_idx]
+            // Use modulo to handle broadcasting: when src1 has fewer columns than expert slots,
+            // multiple slots share the same activation column (col_idx = n_idx % src1->ne[1])
+            const int64_t col_idx = n_idx % src1->ne[1];
+            float         sum     = 0.0f;
+
+            // Type switch hoisted outside block loop: one branch per element, not per block
+            const char * expert_row_base = (const char *) src0_data + m * nb01 + expert_id * nb02;
+
+            switch (src0->type) {
+                case GGML_TYPE_Q8_0:
+                    {
+                        const block_q8_0 * q8_row = (const block_q8_0 *) expert_row_base;
+                        const float *      b_col_base =
+                            (const float *) ((const char *) src1_data + col_idx * nb11 + batch_idx * nb12);
+                        sum += compute_row_dot_q8_0(q8_row, b_col_base, K_blocks);
+                        break;
+                    }
+                case GGML_TYPE_Q4_0:
+                    {
+                        const block_q4_0 * q4_row = (const block_q4_0 *) expert_row_base;
+                        const float *      b_col_base =
+                            (const float *) ((const char *) src1_data + col_idx * nb11 + batch_idx * nb12);
+                        sum += compute_row_dot_q4_0(q4_row, b_col_base, K_blocks);
+                        break;
+                    }
+                case GGML_TYPE_F16:
+                    {
+                        const uint16_t * f16_row     = (const uint16_t *) expert_row_base;
+                        const int64_t    K_remainder = K % block_size;
+                        for (int64_t kb = 0; kb < K_blocks; kb++) {
+                            const float * b_col_ptr =
+                                (const float *) ((const char *) src1_data + (kb * block_size) * sizeof(float) +
+                                                 col_idx * nb11 + batch_idx * nb12);
+                            sum += compute_block_dot_product_f16_naive(&f16_row[kb * block_size], b_col_ptr);
+                        }
+                        if (K_remainder > 0) {
+                            const int64_t offset = K_blocks * block_size;
+                            const float * b_col_ptr =
+                                (const float *) ((const char *) src1_data + offset * sizeof(float) + col_idx * nb11 +
+                                                 batch_idx * nb12);
+                            sum += compute_block_dot_product_f16_partial(&f16_row[offset], b_col_ptr, K_remainder);
+                        }
+                        break;
+                    }
+                case GGML_TYPE_F32:
+                    {
+                        const float * f32_row     = (const float *) expert_row_base;
+                        const int64_t K_remainder = K % block_size;
+                        for (int64_t kb = 0; kb < K_blocks; kb++) {
+                            const float * b_col_ptr =
+                                (const float *) ((const char *) src1_data + (kb * block_size) * sizeof(float) +
+                                                 col_idx * nb11 + batch_idx * nb12);
+                            sum += compute_block_dot_product_f32(&f32_row[kb * block_size], b_col_ptr);
+                        }
+                        if (K_remainder > 0) {
+                            const int64_t offset = K_blocks * block_size;
+                            const float * b_col_ptr =
+                                (const float *) ((const char *) src1_data + offset * sizeof(float) + col_idx * nb11 +
+                                                 batch_idx * nb12);
+                            sum += compute_block_dot_product_f32_partial(&f32_row[offset], b_col_ptr, K_remainder);
+                        }
+                        break;
+                    }
+                default:
+                    return -1;
+            }
+
+            // Store result using atomic store to avoid cache coherency issues
+            // when multiple threads write to the same cache line (64 bytes = 16 floats)
+            volatile float * dst_element =
+                (volatile float *) ((char *) dst_data + m * dst->nb[0] + n_idx * nb1 + batch_idx * nb2);
+            atomic_store_f32(dst_element, sum);
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/norm_f32.c b/ggml/src/ggml-et/et-kernels/src/norm_f32.c
new file mode 100644 (file)
index 0000000..f172b6d
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/norm_f32.c
@@ -0,0 +1,328 @@
+//******************************************************************************
+// Norm F32 Kernel (Layer Normalization)
+// y[i] = (x[i] - mean) / sqrt(variance + eps)
+// where mean = sum(x) / N, variance = sum((x - mean)^2) / N
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+// Norm kernel parameters structure
+struct ggml_et_norm_params {
+    struct ggml_tensor src0;  // F32 input tensor
+    struct ggml_tensor dst;   // F32 output tensor
+    float              eps;   // Epsilon parameter for numerical stability
+};
+
+int entry_point(struct ggml_et_norm_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+    float                eps  = params->eps;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+
+    if (eps < 0.0f) {
+        return -1;  // Invalid epsilon
+    }
+
+    const int64_t ne0 = dst->ne[0];
+    const int64_t ne1 = dst->ne[1];
+    const int64_t ne2 = dst->ne[2];
+    const int64_t ne3 = dst->ne[3];
+
+    const size_t nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+    const size_t nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+
+    if (src0->ne[0] != ne0 || src0->ne[1] != ne1 || src0->ne[2] != ne2 || src0->ne[3] != ne3) {
+        return -1;  // Shape mismatch
+    }
+
+    const int32_t total_rows    = (int32_t) (ne1 * ne2 * ne3);
+    const int     shire_threads = SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+
+    if (total_rows >= shire_threads) {
+        // Row-parallel: each thread processes whole rows
+        for (int64_t i3 = 0; i3 < ne3; i3++) {
+            for (int64_t i2 = 0; i2 < ne2; i2++) {
+                for (int64_t i1 = thread_id; i1 < ne1; i1 += num_threads) {
+                    const float * src_ptr =
+                        (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                    float * dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+                    // Step 1: sum for mean
+                    float zero = 0.0f;
+                    __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[x_vec]\n"
+                            "fadd.ps f10, f10, f11\n"
+                            :
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                            : "f10", "f11");
+                    }
+
+                    float sum;
+                    __asm__ __volatile__(
+                        "fswizz.ps f1, f10, 0xB1 \n\t"
+                        "fadd.ps   f2, f10, f1, rne \n\t"
+                        "fswizz.ps f3, f2, 0x4E \n\t"
+                        "fadd.ps   f4, f2, f3, rne \n\t"
+                        "fmvz.x.ps t0, f4, 4 \n\t"
+                        "fbcx.ps   f5, t0 \n\t"
+                        "fadd.ps   %[vout], f4, f5, rne \n\t"
+                        : [vout] "=f"(sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+                    const float mean = et_fdiv(sum, (float) (int32_t) ne0);
+
+                    // Step 2: compute (x - mean) → dst, accumulate variance
+                    __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[x_vec]\n"
+                            "fbc.ps f12, %[mean_ptr]\n"
+                            "fsub.ps f13, f11, f12\n"
+                            "fsw.ps f13, %[result]\n"
+                            "fmadd.ps f10, f13, f13, f10\n"
+                            : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0]), [mean_ptr] "m"(mean)
+                            : "f10", "f11", "f12", "f13");
+                    }
+
+                    float var_sum;
+                    __asm__ __volatile__(
+                        "fswizz.ps f1, f10, 0xB1 \n\t"
+                        "fadd.ps   f2, f10, f1, rne \n\t"
+                        "fswizz.ps f3, f2, 0x4E \n\t"
+                        "fadd.ps   f4, f2, f3, rne \n\t"
+                        "fmvz.x.ps t0, f4, 4 \n\t"
+                        "fbcx.ps   f5, t0 \n\t"
+                        "fadd.ps   %[vout], f4, f5, rne \n\t"
+                        : [vout] "=f"(var_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+                    const float variance = et_fdiv(var_sum, (float) (int32_t) ne0);
+                    const float scale    = et_powf(variance + eps, -0.5f);
+
+                    if (!(scale > 0.0f)) {
+                        return -1;
+                    }
+
+                    // Step 3: apply scale to centered values in dst
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f12, %[y_vec]\n"
+                            "fbc.ps f13, %[scale_ptr]\n"
+                            "fmul.ps f14, f12, f13\n"
+                            "fsw.ps f14, %[result]\n"
+                            : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                            : [y_vec] "m"(*(const float (*)[8]) & dst_ptr[i0]), [scale_ptr] "m"(scale)
+                            : "f12", "f13", "f14");
+                    }
+                }
+            }
+        }
+    } else {
+        // Intra-row: threads within each shire cooperate via L2 SCP.
+        // Two reductions needed: sum (for mean), then variance sum.
+        int shire_tid       = thread_id % shire_threads;
+        int threads_per_row = shire_threads / total_rows;
+        int my_row          = shire_tid / threads_per_row;
+        int local_tid       = shire_tid % threads_per_row;
+        int group_base      = my_row * threads_per_row;
+
+        if (my_row >= total_rows) {
+            FENCE;
+            et_barrier(ET_BARRIER_SHIRE);
+            // Second barrier for variance exchange
+            FENCE;
+            et_barrier(ET_BARRIER_SHIRE);
+            return 0;
+        }
+
+        int64_t i1 = my_row % ne1;
+        int64_t i2 = (my_row / ne1) % ne2;
+        int64_t i3 = my_row / (ne1 * ne2);
+
+        const float * src_ptr = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+        float *       dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+        const int32_t elems_per_cl   = 16;
+        int32_t       total_cls      = ((int32_t) ne0 + elems_per_cl - 1) / elems_per_cl;
+        int32_t       cls_per_thread = (total_cls + threads_per_row - 1) / threads_per_row;
+        int32_t       my_start       = local_tid * cls_per_thread * elems_per_cl;
+        int32_t       my_end         = my_start + cls_per_thread * elems_per_cl;
+        if (my_end > (int32_t) ne0) {
+            my_end = (int32_t) ne0;
+        }
+        if (my_start >= (int32_t) ne0) {
+            my_start = 0;
+            my_end   = 0;
+        }
+
+        int workers = threads_per_row < total_cls ? threads_per_row : total_cls;
+
+        unsigned long saved_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+        // ---- Reduction 1: partial sum for mean ----
+        __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+        for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+            __asm__ volatile(
+                "flw.ps f11, %[x_vec]\n"
+                "fadd.ps f10, f10, f11\n"
+                :
+                : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                : "f10", "f11");
+        }
+
+        float partial_sum;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(partial_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+        // L2SCP exchange for sum
+        volatile float * my_slot = (volatile float *) et_shire_l2scp_local((uint64_t) shire_tid * 64);
+        *my_slot                 = partial_sum;
+        FENCE;
+        evict_to_l2((const void *) my_slot, 1, 64);
+        WAIT_CACHEOPS;
+
+        et_barrier(ET_BARRIER_SHIRE);
+
+        // All threads read sum, compute mean
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            evict_to_l2((const void *) slot, 1, 64);
+        }
+        WAIT_CACHEOPS;
+
+        float total_sum = 0.0f;
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            total_sum += *slot;
+        }
+
+        const float mean = et_fdiv(total_sum, (float) (int32_t) ne0);
+
+        // ---- Reduction 2: compute (x - mean) → dst chunk, partial variance ----
+        __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+
+        if (my_start < my_end) {
+            uint32_t mean_bits;
+            __asm__ volatile("fmv.x.s %0, %1" : "=r"(mean_bits) : "f"(mean));
+            __asm__ volatile("fbcx.ps f15, %[mb]\n" : : [mb] "r"(mean_bits) : "f15");
+
+            for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+                __asm__ volatile(
+                    "flw.ps f11, %[x_vec]\n"
+                    "fsub.ps f13, f11, f15\n"
+                    "fsw.ps f13, %[result]\n"
+                    "fmadd.ps f10, f13, f13, f10\n"
+                    : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                    : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                    : "f10", "f11", "f13");
+            }
+        }
+
+        float partial_var;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(partial_var)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+        // L2SCP exchange for variance (reuse same slots)
+        *my_slot = partial_var;
+        FENCE;
+        evict_to_l2((const void *) my_slot, 1, 64);
+        WAIT_CACHEOPS;
+
+        et_barrier(ET_BARRIER_SHIRE);
+
+        // All threads read variance, compute scale, apply to own chunk
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            evict_to_l2((const void *) slot, 1, 64);
+        }
+        WAIT_CACHEOPS;
+
+        float total_var = 0.0f;
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            total_var += *slot;
+        }
+
+        const float variance = et_fdiv(total_var, (float) (int32_t) ne0);
+        const float scale    = et_powf(variance + eps, -0.5f);
+
+        if (!(scale > 0.0f)) {
+            __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+            return -1;
+        }
+
+        // Apply scale to centered values (already in dst from reduction 2)
+        if (my_start < my_end) {
+            uint32_t scale_bits;
+            __asm__ volatile("fmv.x.s %0, %1" : "=r"(scale_bits) : "f"(scale));
+            __asm__ volatile("fbcx.ps f13, %[sb]\n" : : [sb] "r"(scale_bits) : "f13");
+
+            for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+                __asm__ volatile(
+                    "flw.ps f12, %[y_vec]\n"
+                    "fmul.ps f14, f12, f13\n"
+                    "fsw.ps f14, %[result]\n"
+                    : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                    : [y_vec] "m"(*(const float (*)[8]) & dst_ptr[i0])
+                    : "f12", "f14");
+            }
+        }
+
+        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/pad_f32.c b/ggml/src/ggml-et/et-kernels/src/pad_f32.c
new file mode 100644 (file)
index 0000000..085336f
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/pad_f32.c
@@ -0,0 +1,165 @@
+//******************************************************************************
+// Bare Metal PAD F32 Kernel
+// Zero-pads an F32 tensor along dimensions 1-3.
+//
+// Constraints:
+//   - No dim0 padding (lp[0]==0, rp[0]==0)
+//   - dst contiguous
+//   - src nb[0] == 4 (dim0 contiguous for vectorized reads)
+//   - Zero-pad only (no circular mode)
+//
+// Two paths:
+//   Aligned (ne0 % 16 == 0): rows distributed across harts, vectorized.
+//   Small   (16 % ne0 == 0): cache-line distributed, scalar per-element.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_pad_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+    int32_t            lp[4];
+    int32_t            rp[4];
+};
+
+// Vectorized copy with scalar tail
+static inline void vec_copy_f32(float * dst, const float * src, int32_t n) {
+    int32_t       i       = 0;
+    const int32_t vec_end = (n / 8) * 8;
+    for (; i < vec_end; i += 8) {
+        __asm__ volatile(
+            "flw.ps f10, %[s]\n"
+            "fsw.ps f10, %[d]\n"
+            : [d] "=m"(*(float (*)[8]) & dst[i])
+            : [s] "m"(*(const float (*)[8]) & src[i])
+            : "f10");
+    }
+    for (; i < n; i++) {
+        dst[i] = src[i];
+    }
+}
+
+int entry_point(struct ggml_et_pad_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float * src0_data = (const float *) src0->data;
+    float *       dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    // Dst dimensions
+    const int64_t ne0 = dst->ne[0];
+    const int64_t ne1 = dst->ne[1];
+    const int64_t ne2 = dst->ne[2];
+    const int64_t ne3 = dst->ne[3];
+
+    // Src strides (byte offsets)
+    const int64_t nb1_src = src0->nb[1];
+    const int64_t nb2_src = src0->nb[2];
+    const int64_t nb3_src = src0->nb[3];
+
+    // Padding values
+    const int32_t lp1 = params->lp[1];
+    const int32_t rp1 = params->rp[1];
+    const int32_t lp2 = params->lp[2];
+    const int32_t rp2 = params->rp[2];
+    const int32_t lp3 = params->lp[3];
+    const int32_t rp3 = params->rp[3];
+
+    const int64_t total_rows     = ne1 * ne2 * ne3;
+    const int64_t total_elements = ne0 * total_rows;
+
+    if (total_elements == 0) {
+        return 0;
+    }
+
+    // Broadcast 0.0f to SIMD register for vectorized zero-fill
+    float zero = 0.0f;
+    __asm__ volatile("fbc.ps f12, %[v]\n" : : [v] "m"(zero) : "f12");
+
+    // Aligned: ne0 % 16 == 0 -> row-based distribution, vectorized
+    if (ne0 % 16 == 0) {
+        for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+            const int64_t i3 = row / (ne1 * ne2);
+            const int64_t i2 = (row / ne1) % ne2;
+            const int64_t i1 = row % ne1;
+
+            float * dst_row = dst_data + row * ne0;
+
+            if (i1 >= lp1 && i1 < ne1 - rp1 && i2 >= lp2 && i2 < ne2 - rp2 && i3 >= lp3 && i3 < ne3 - rp3) {
+                const float * src_row = (const float *) ((const char *) src0_data + (i1 - lp1) * nb1_src +
+                                                         (i2 - lp2) * nb2_src + (i3 - lp3) * nb3_src);
+                vec_copy_f32(dst_row, src_row, (int32_t) ne0);
+            } else {
+                int64_t       i       = 0;
+                const int64_t vec_end = (ne0 / 8) * 8;
+                for (; i < vec_end; i += 8) {
+                    __asm__ volatile("fsw.ps f12, %[d]\n" : [d] "=m"(*(float (*)[8]) & dst_row[i])::"f12");
+                }
+            }
+        }
+        return 0;
+    }
+
+    // Small-ne0 path: 16 % ne0 == 0 -> cache-line distributed, scalar
+    const int64_t elems_per_cl = 16;
+    const int64_t total_cl     = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+    const int64_t ne1_data_end = ne1 - rp1;
+    const int64_t ne2_data_end = ne2 - rp2;
+    const int64_t ne3_data_end = ne3 - rp3;
+
+    for (int64_t cl = thread_id; cl < total_cl; cl += num_threads) {
+        const int64_t elem_start = cl * elems_per_cl;
+        int64_t       elem_end   = elem_start + elems_per_cl;
+        if (elem_end > total_elements) {
+            elem_end = total_elements;
+        }
+
+        for (int64_t idx = elem_start; idx < elem_end; idx++) {
+            const int64_t i0   = idx % ne0;
+            const int64_t rem  = idx / ne0;
+            const int64_t i1   = rem % ne1;
+            const int64_t rem2 = rem / ne1;
+            const int64_t i2   = rem2 % ne2;
+            const int64_t i3   = rem2 / ne2;
+
+            if (i1 >= lp1 && i1 < ne1_data_end && i2 >= lp2 && i2 < ne2_data_end && i3 >= lp3 && i3 < ne3_data_end) {
+                const float * sp = (const float *) ((const char *) src0_data + i0 * 4 + (i1 - lp1) * nb1_src +
+                                                    (i2 - lp2) * nb2_src + (i3 - lp3) * nb3_src);
+                dst_data[idx]    = *sp;
+            } else {
+                dst_data[idx] = 0.0f;
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/platform.h b/ggml/src/ggml-et/et-kernels/src/platform.h
new file mode 100644 (file)
index 0000000..cbec4c9
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/platform.h
@@ -0,0 +1,545 @@
+//******************************************************************************
+// ET Platform Hardware Abstraction Layer
+// Provides thread coordination, kernel infrastructure, and platform primitives
+// for bare metal ET kernels
+//******************************************************************************
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#include "etsoc/common/utils.h"
+#include "etsoc/isa/barriers.h"
+#include "etsoc/isa/cacheops-umode.h"
+#include "etsoc/isa/hart.h"
+
+#include <stdint.h>
+
+#define SOC_MINIONS_PER_SHIRE    32
+#define NUM_HARTS_PER_MINION     2
+#define ET_CACHE_LINE_SIZE_BYTES 64
+
+// Environment structure definition
+typedef struct {
+    uint32_t version;     // Version of the ABI (offset 0)
+    uint32_t padding1;    // Padding to align shire_mask to offset 8
+    uint64_t shire_mask;  // Bitmask of active compute shires (offset 8)
+    uint32_t frequency;   // Frequency of Minion cores in MHz (offset 16)
+    uint32_t padding2;    // Padding to maintain alignment
+} __attribute__((packed, aligned(64))) kernel_environment_t;
+
+// Manual implementation of count trailing zeros for bare metal environment
+// NOTE: This simple loop-based implementation is used for portability.
+// Production implementations (like libgcc's __ctzdi2) use optimized bit manipulation
+// algorithms with lookup tables and parallel bit operations for O(log n) performance.
+static inline int manual_ctzll(uint64_t x) {
+    if (x == 0) return 64;
+    int count = 0;
+    while ((x & 1) == 0) {
+        x >>= 1;
+        count++;
+    }
+    return count;
+}
+
+// Manual implementation of population count for bare metal environment
+// NOTE: This simple loop-based implementation is used for portability.
+// Production implementations (like libgcc's __popcountdi2) use optimized bit-parallel
+// algorithms with magic constants and bit manipulation tricks for O(1) performance.
+static inline int manual_popcountll(uint64_t x) {
+    int count = 0;
+    while (x) {
+        count += x & 1;
+        x >>= 1;
+    }
+    return count;
+}
+
+// Binary GCD (Stein's algorithm) — avoids expensive 64-bit division/remainder.
+// Uses only shifts, subtraction, and comparison (all single-cycle on ET cores).
+static inline int64_t et_gcd_i64(int64_t a, int64_t b) {
+    while (b) {
+        const int64_t t = b;
+        b               = a % b;
+        a               = t;
+    }
+    return a;
+}
+
+// Return the number of consecutive rows of width row_elems needed so the
+// combined write footprint spans an integer number of cache lines.
+static inline int64_t et_rows_per_cacheline_group(int64_t row_elems, int64_t elem_size_bytes) {
+    if (row_elems <= 0 || elem_size_bytes <= 0) {
+        return 1;
+    }
+
+    const int64_t row_bytes = row_elems * elem_size_bytes;
+    const int64_t gcd       = et_gcd_i64(ET_CACHE_LINE_SIZE_BYTES, row_bytes);
+    return ET_CACHE_LINE_SIZE_BYTES / gcd;
+}
+
+// Calculate relative thread ID from absolute hart ID using shire mask
+// Returns -1 if this hart is not active (not in shire mask)
+static inline int get_relative_thread_id(uint64_t shire_mask) {
+    int hart_id = (int) get_hart_id();
+
+    // Find starting hart offset from lowest active shire
+    int starting_hart = manual_ctzll(shire_mask) * SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+
+    // Return -1 if not an active thread
+    if (hart_id < starting_hart) {
+        return -1;
+    }
+
+    // Calculate relative thread ID
+    int thread_id = hart_id - starting_hart;
+    return thread_id;
+}
+
+// Calculate total number of threads from shire mask
+static inline int get_num_threads(uint64_t shire_mask) {
+    // Count active shires using popcount, multiply by minions per shire and harts per minion
+    return manual_popcountll(shire_mask) * SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+}
+
+//******************************************************************************
+// Synchronization Primitives
+//******************************************************************************
+
+#define NOP   __asm__ __volatile__("nop\n");
+#define FENCE __asm__ __volatile__("fence\n" ::: "memory");
+#define WFI   __asm__ __volatile__("wfi\n");
+
+//******************************************************************************
+// Atomic Operations
+//******************************************************************************
+
+// Global AMO primitives — ET custom 'g' suffix instructions that go through
+// the NoC coherence fabric for chip-wide atomicity.
+
+// Atomic swap (word), returns previous value.
+static inline uint32_t __attribute__((always_inline)) et_global_swap_w(volatile void * addr, uint32_t val) {
+    uint32_t ret;
+    __asm__ __volatile__("amoswapg.w %0, %1, (%2)" : "=r"(ret) : "r"(val), "r"(addr) : "memory");
+    return ret;
+}
+
+// Atomic add (word), returns previous value.
+static inline uint32_t __attribute__((always_inline)) et_global_add_w(volatile void * addr, uint32_t val) {
+    uint32_t ret;
+    __asm__ __volatile__("amoaddg.w %0, %1, (%2)" : "=r"(ret) : "r"(val), "r"(addr) : "memory");
+    return ret;
+}
+
+// Atomic store (halfword, global). Address must be 16-bit aligned.
+static inline void __attribute__((always_inline)) et_global_store_hw(volatile void * addr, uint16_t val) {
+    __asm__ __volatile__("shg %0, (%1)" : : "r"(val), "r"(addr) : "memory");
+}
+
+// Convenience wrappers — float types, fire-and-forget (old value discarded).
+static inline void atomic_store_f32(volatile float * addr, float value) {
+    et_global_swap_w(addr, *(uint32_t *) &value);
+}
+
+static inline void atomic_add_f32(volatile float * addr, float value) {
+    et_global_add_w(addr, *(uint32_t *) &value);
+}
+
+static inline void atomic_store_f16(volatile uint16_t * addr, uint16_t value) {
+    et_global_store_hw(addr, value);
+}
+
+//******************************************************************************
+// Barrier Primitives
+//
+// Hardware resources used (per shire):
+//   - 32 FLBs: 8-bit atomic counters, non-blocking (CSR 0x820)
+//   - 2 FCCs per hart: credit counters, hardware-stall on consume (CSR 0x821)
+//
+// Convention:
+//   MINION barriers: FLB = local_minion_id (0-31), FCC 0
+//   SHIRE  barriers: FLB 0,                        FCC 1
+//
+// MINION and SHIRE barriers MUST NOT be concurrent. All minion barriers
+// must complete before a shire barrier, and vice versa. FLB 0 is shared
+// between minion 0's barrier and the shire barrier — safe only because
+// the FLB counter auto-resets on match.
+//
+// FCC 0 is safe for all 32 concurrent minion barriers because each
+// barrier's fcc_send targets only its own minion (per-hart private
+// counters, scoped by CREDINC mask). FCC 1 is reserved for shire-wide
+// broadcast.
+//******************************************************************************
+
+#define ET_DEFAULT_SHIRE_MASK 0xFFFFFFFFULL
+
+typedef enum {
+    ET_BARRIER_MINION,  // sync both harts within each minion (FLB=minion_id, FCC 0)
+    ET_BARRIER_SHIRE,   // sync all harts across the shire   (FLB=0, FCC 1)
+    ET_BARRIER_GLOBAL,  // sync all harts across all active shires (FLB+global AMO+FCC)
+} et_barrier_scope_t;
+
+//******************************************************************************
+// Global Barrier (cross-shire)
+//
+// Synchronizes all harts across multiple shires on the chip.
+// Algorithm:
+//   1. FLB within each shire to elect one representative hart
+//   2. Elected hart does a global atomic increment on a shared counter
+//   3. The last shire to arrive resets the counter and sends FCC credits
+//      to all active shires to release them
+//   4. All harts wait on FCC to complete the barrier
+//
+// Uses FLB 0, FCC 1 (same as ET_BARRIER_SHIRE, these must not overlap).
+// The counter lives in a cache-line-aligned global to avoid coherency problems
+//******************************************************************************
+
+// Barrier counter cache-line aligned to avoid coherency problems
+// Must be zero-initialized (BSS).
+static uint32_t __attribute__((aligned(64))) et_global_barrier_count[64 / sizeof(uint32_t)] = { 0 };
+
+// Cross-shire barrier: all harts in num_active_shires shires synchronize.
+// Returns 1 if this hart was the globally-last to arrive, 0 otherwise.
+//
+//   num_active_shires - number of shires participating
+//                       (typically popcount(shire_mask) from kernel_environment_t)
+static inline uint64_t __attribute__((always_inline)) et_barrier_global(uint64_t num_active_shires) {
+    uint64_t last_global = 0;
+
+    // FLB within this shire. Elect one hart per shire.
+    // Master shire has only 16 minions (32 harts), others have 32 (64 harts).
+    uint64_t shire_id       = get_shire_id();
+    uint32_t harts_in_shire = (shire_id == SHIRE_MASTER) ? (SOC_MINIONS_PER_SHIRE / 2) * NUM_HARTS_PER_MINION :
+                                                           SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+    uint64_t last_in_shire  = flbarrier(0, harts_in_shire - 1);
+
+    if (last_in_shire) {
+        // Global atomic increment. Count arriving shires
+        uint32_t prev = et_global_add_w(et_global_barrier_count, 1);
+
+        if (prev == num_active_shires - 1) {
+            // Last shire. reset counter and fan out FCC to all shires
+            last_global = 1;
+            et_global_swap_w(et_global_barrier_count, 0);
+
+            for (uint64_t sid = 0; sid < 33; sid++) {
+                // Send FCC 1 credit to all harts (both threads) in each shire
+                fcc_send(sid, THREAD_0, FCC_1, 0xFFFFFFFF);
+                fcc_send(sid, THREAD_1, FCC_1, 0xFFFFFFFF);
+            }
+        }
+    }
+
+    // All harts wait for the FCC credit from the last shire
+    fcc_consume(FCC_1);
+    return last_global;
+}
+
+// Barrier with scope-derived parameters.
+// Returns 1 if this hart was the last to arrive, 0 otherwise.
+//
+// ET_BARRIER_GLOBAL uses ET_DEFAULT_SHIRE_MASK (32 shires). For a different
+// shire count, use et_barrier_global(n) directly.
+static inline uint64_t __attribute__((always_inline)) et_barrier(et_barrier_scope_t scope) {
+    if (scope == ET_BARRIER_MINION) {
+        uint32_t local_minion = (get_hart_id() >> 1) & 0x1F;
+        uint32_t mask         = 1u << local_minion;
+        return shire_barrier(local_minion, 0, 2, mask, mask);
+    } else if (scope == ET_BARRIER_SHIRE) {
+        uint64_t shire_id     = get_shire_id();
+        uint32_t thread_count = (shire_id == SHIRE_MASTER) ? 32 : 64;
+        uint32_t mask         = (shire_id == SHIRE_MASTER) ? 0xFFFF0000U : 0xFFFFFFFFU;
+        return shire_barrier(0, 1, thread_count, mask, mask);
+    } else { /* ET_BARRIER_GLOBAL */
+        return et_barrier_global(manual_popcountll(ET_DEFAULT_SHIRE_MASK));
+    }
+}
+
+// Raw barrier — caller manages FLB/FCC allocation.
+// Use when et_barrier() doesn't fit (custom thread counts, subgroups,
+// only even harts active, etc).
+//
+//   flb          - which FLB counter (0-31)
+//   fcc          - which FCC counter (0 or 1)
+//   thread_count - number of harts that will call this barrier
+//   mask_t0      - CREDINC bitmask: which minions' hart 0 gets a credit
+//   mask_t1      - CREDINC bitmask: which minions' hart 1 gets a credit
+static inline uint64_t __attribute__((always_inline)) et_barrier_raw(uint32_t flb,
+                                                                     uint32_t fcc,
+                                                                     uint32_t thread_count,
+                                                                     uint32_t mask_t0,
+                                                                     uint32_t mask_t1) {
+    return shire_barrier(flb, fcc, thread_count, mask_t0, mask_t1);
+}
+
+// One-way semaphore between harts (non-blocking post, blocking wait).
+//
+// et_sem_post(): increment the partner hart's semaphore. Non-blocking.
+//   the caller continues immediately. Multiple posts accumulate.
+//
+// et_sem_wait(): block until the semaphore is non-zero, then decrement it.
+//
+// Backed by hardware FCC (Flow Control Credit) counters. Uses FCC 0 for
+// ET_BARRIER_MINION scope. Counters are per-hart private, so both harts
+// can post/wait on the same scope independently.
+//
+// Must not be mixed with et_barrier() of the same scope in the
+// same kernel (shared FCC channel).
+static inline void __attribute__((always_inline)) et_sem_post(et_barrier_scope_t scope) {
+    if (scope == ET_BARRIER_MINION) {
+        uint64_t hart_id      = get_hart_id();
+        uint32_t local_minion = (hart_id >> 1) & 0x1F;
+        uint32_t mask         = 1u << local_minion;
+        uint64_t shire_id     = get_shire_id();
+
+        if (hart_id & 1) {
+            // Hart 1 → hart 0
+            fcc_send(shire_id, THREAD_0, FCC_0, mask);
+        } else {
+            // Hart 0 → hart 1
+            fcc_send(shire_id, THREAD_1, FCC_0, mask);
+        }
+    }
+}
+
+// Block until a post from et_sem_post() is available, then consume it.
+static inline void __attribute__((always_inline)) et_sem_wait(et_barrier_scope_t scope) {
+    if (scope == ET_BARRIER_MINION) {
+        fcc_consume(FCC_0);
+    }
+}
+
+//******************************************************************************
+// Tensor Engine Wait & Error Macros
+//
+// These write to CSR 0x830 (tensor_wait) to stall the hart until the specified
+// tensor unit completes its current operation.  The immediate encodes which
+// unit to wait on.
+//******************************************************************************
+
+#define WAIT_TENSOR_LOAD_0    __asm__ __volatile__("csrwi 0x830, 0\n" : :);
+#define WAIT_TENSOR_LOAD_1    __asm__ __volatile__("csrwi 0x830, 1\n" : :);
+#define WAIT_TENSOR_LOAD_L2_0 __asm__ __volatile__("csrwi 0x830, 2\n" : :);
+#define WAIT_TENSOR_LOAD_L2_1 __asm__ __volatile__("csrwi 0x830, 3\n" : :);
+#define WAIT_PREFETCH_0       __asm__ __volatile__("csrwi 0x830, 4\n" : :);
+#define WAIT_PREFETCH_1       __asm__ __volatile__("csrwi 0x830, 5\n" : :);
+#define WAIT_CACHEOPS         __asm__ __volatile__("csrwi 0x830, 6\n" : :);
+#define WAIT_TENSOR_FMA       __asm__ __volatile__("csrwi 0x830, 7\n" : :);
+#define WAIT_TENSOR_STORE     __asm__ __volatile__("csrwi 0x830, 8\n" : :);
+#define WAIT_TENSOR_REDUCE    __asm__ __volatile__("csrwi 0x830, 9\n" : :);
+#define WAIT_TENSOR_QUANT     __asm__ __volatile__("csrwi 0x830, 10\n" : :);
+#define STALL                 __asm__ __volatile__("csrw stall, x0\n" : :);
+
+// Write 0 to CSR 0x808 (tensor_error) to clear any latched tensor error bits.
+// Must be issued before the first tensor operation in a kernel to avoid stale
+// errors from a previous invocation causing spurious faults.
+#define CLEAR_TENSOR_ERROR __asm__ __volatile__("csrwi 0x808, 0" : :);
+
+//******************************************************************************
+// L1 Data Cache / Scratchpad (SCP) Configuration
+//
+// The ET-SoC-1 L1 data cache can be split so that half its ways operate as a
+// software-managed scratchpad (SCP).  Tensor load/store/FMA instructions
+// require SCP mode to be active.
+//
+// CSR 0x810 — ucache_control:
+//
+//   Bit(s)  Field         Description
+//   ──────  ────────────  ──────────────────────────────────────────────────
+//   [0]     D1Split       1 = L1 is split (half cache, half SCP).
+//                          Read-only from U-mode; set by M-mode firmware
+//                          before kernel launch.  Writing ScpEnable while
+//                          D1Split=0 is silently ignored.
+//   [1]     ScpEnable     1 = scratchpad is active and zeroed.
+//   [4:2]   RepRate       Cache-op replay rate (0 = no delay between ops).
+//   [10:6]  CacheOpMax    Max outstanding cache ops (0 = unlimited).
+//
+// Typical kernel prologue for tensor operations:
+//     setup_cache_scp();   // enables SCP, waits for zeroing
+//     CLEAR_TENSOR_ERROR;  // clear stale error bits
+//******************************************************************************
+
+// Write the ucache_control CSR (0x810).
+//
+//   scp_en       — 1 to enable SCP mode (requires D1Split already set)
+//   cacheop_rate — cache-op replay rate (0–7; 0 = no delay)
+//   cacheop_max  — max outstanding cache ops (0–31; 0 = unlimited)
+static inline void __attribute__((always_inline)) ucache_control(uint64_t scp_en,
+                                                                 uint64_t cacheop_rate,
+                                                                 uint64_t cacheop_max) {
+    uint64_t csr_enc = ((cacheop_max & 0x1F) << 6) | ((cacheop_rate & 0x7) << 2) | ((scp_en & 0x1) << 1);
+
+    __asm__ __volatile__("csrw 0x810, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) : "x31");
+}
+
+// Enable L1 scratchpad mode and wait for the transition to complete.
+// After this call the SCP lines are zeroed and ready for tensor operations.
+//
+// Prerequisites:
+//   - D1Split must already be 1 (set by M-mode firmware at boot).
+//   - Only even harts (hart 0 per minion) should call this, as only they
+//     can issue tensor instructions.
+static inline void setup_cache_scp(void) {
+    FENCE;                    // drain pending stores before reconfiguring cache
+    ucache_control(1, 0, 0);  // ScpEnable=1
+    WAIT_CACHEOPS;            // wait for SCP mode transition + zeroing
+}
+
+//******************************************************************************
+// L2 Scratchpad (L2 SCP) Address Computation
+//
+// Each shire has 4 MB of SRAM that can be split across L2 cache, L3 cache,
+// and scratchpad.  The scratchpad region occupies 0x00_8000_0000~0x00_FFFF_FFFF
+// and is accessible via regular load/store from any minion core.
+//
+// Two addressing formats (differentiated by address bit 30):
+//
+// Format 0 (bit[30]=0): Direct shire addressing
+//   [29:23] = shire ID (0–33, or 0x7F for local shire)
+//   [22:0]  = byte offset within shire's scratchpad
+//
+// Format 1 (bit[30]=1): Striped (round-robin) addressing
+//   [29:28] = shire ID[6:5]
+//   [27:11] = offset[22:6]   (cache-line-aligned upper bits)
+//   [10:6]  = shire ID[4:0]
+//   [5:0]   = offset[5:0]    (byte within cache line)
+//   Consecutive 64-byte cache lines cycle through different shires,
+//   distributing bandwidth across the mesh.
+//
+// Shire ID 0x7F always targets the local shire (instead of figureing out which
+// shire you are on).
+//******************************************************************************
+
+#define L2SCP_BASE        0x0080000000ULL
+#define L2SCP_SHIRE_LOCAL 0x7FULL
+
+// Format 0: direct address into a specific shire's L2 SCP.
+//   shire: 0–33 for explicit shire, L2SCP_SHIRE_LOCAL (0x7F) for local
+//   offset: byte offset within the shire's scratchpad
+static inline void * __attribute__((always_inline)) et_shire_l2scp(uint64_t shire, uint64_t offset) {
+    return (void *) (L2SCP_BASE | ((shire & 0x7F) << 23) | (offset & 0x7FFFFF));
+}
+
+// Format 0: local shire shorthand — no cross-shire traffic.
+static inline void * __attribute__((always_inline)) et_shire_l2scp_local(uint64_t offset) {
+    return (void *) (L2SCP_BASE | (L2SCP_SHIRE_LOCAL << 23) | (offset & 0x7FFFFF));
+}
+
+// Format 1: flat offset into a hardware-striped global address space.
+// Consecutive 64-byte cache lines automatically land on different shires,
+// distributing bandwidth across the mesh.  No shire parameter — the
+// hardware derives the target shire from the address bits.
+static inline void * __attribute__((always_inline)) et_global_l2scp(uint64_t offset) {
+    return (void *) (L2SCP_BASE | (1ULL << 30) | (offset & 0x3FFFFFFF));
+}
+
+//******************************************************************************
+// Cache Operatons
+//******************************************************************************
+
+// Prefetch nlines cache lines into L2 starting at addr, with stride bytes
+// between each line.  Uses PrefetchVA (CSR 0x81F) with dest=L2 (bits 59:58=01).
+//
+// The hardware fetches nlines consecutive cache-line-sized (64B) blocks from
+// DRAM/L3 into L2, starting at addr and advancing by stride bytes per line.
+// This is asynchronous — use WAIT_PREFETCH_0 or WAIT_PREFETCH_1 if the hart
+// must stall until the prefetch completes.
+//
+// NOTE: nlines is encoded in a 4-bit field (max 16). Passing nlines > 16
+// silently truncates. DO NOT pass nlines > 16.
+static inline void __attribute__((always_inline)) l2_prefetch(const void * addr, uint64_t nlines, uint64_t stride) {
+    uint64_t csr_val = (0x1ULL << 58) | ((uint64_t) addr & 0xFFFFFFFFFFC0ULL) | ((nlines - 1) & 0xF);
+
+    __asm__ __volatile__(
+        "mv    x31, %[stride]\n"
+        "csrw  0x81f, %[val]\n"
+        :
+        : [stride] "r"(stride & 0xFFFFFFFFFFC0ULL), [val] "r"(csr_val)
+        : "x31", "memory");
+}
+
+// Flush nlines cache lines at stride apart starting at addr from L1 to L2.
+// Uses FlushVA (CSR 0x8BF).  Caller must FENCE before (to drain stores to L1)
+// and WAIT_CACHEOPS after (to ensure flush completes before tensor loads).
+//
+// NOTE: nlines is encoded in a 4-bit field (max 16). Passing nlines > 16
+// silently truncates. DO NOT pass nlines > 16.
+static inline void __attribute__((always_inline)) flush_to_l2(const void * addr, uint64_t nlines, uint64_t stride) {
+    // dest=01 (L2) in bits 59:58, VA in bits 47:6, numlines-1 in bits 3:0
+    uint64_t csr_val = (0x1ULL << 58) | ((uint64_t) addr & 0xFFFFFFFFFFC0ULL) | ((nlines - 1) & 0xF);
+    uint64_t x31_val = stride & 0xFFFFFFFFFFC0ULL;
+
+    __asm__ __volatile__(
+        "mv x31, %[x31]\n"
+        "csrw 0x8BF, %[val]\n"
+        :
+        : [x31] "r"(x31_val), [val] "r"(csr_val)
+        : "x31", "memory");
+}
+
+// Evict nlines cache lines at stride apart starting at addr from L1 to L2.
+// Uses EvictVA (CSR 0x89F).  Unlike flush_to_l2, this guarantees the line is
+// NOT present in L1 after the operation - subsequent loads will miss and go
+// to L2/SCP. Caller must FENCE before and WAIT_CACHEOPS after.
+//
+// NOTE: nlines is encoded in a 4-bit field (max 16). DO NOT pass nlines > 16.
+static inline void __attribute__((always_inline)) evict_to_l2(const void * addr, uint64_t nlines, uint64_t stride) {
+    // dest=01 (L2) in bits 59:58, VA in bits 47:6, numlines-1 in bits 3:0
+    uint64_t csr_val = (0x1ULL << 58) | ((uint64_t) addr & 0xFFFFFFFFFFC0ULL) | ((nlines - 1) & 0xF);
+    uint64_t x31_val = stride & 0xFFFFFFFFFFC0ULL;
+
+    __asm__ __volatile__(
+        "mv x31, %[x31]\n"
+        "csrw 0x89F, %[val]\n"
+        :
+        : [x31] "r"(x31_val), [val] "r"(csr_val)
+        : "x31", "memory");
+}
+
+// Evict nlines cache lines at stride apart starting at addr from BOTH L1
+// and L2. Uses EvictVA (CSR 0x89F) with dest=10 (L3/DRAM). Guarantees the
+// line is NOT present in L1 or L2 after the operation — subsequent loads
+// will fetch from L3 or DRAM. Needed because both L1 and L2 are incoherent
+// on ET-SoC-1 (L2 is per-shire).
+// Caller must FENCE before and WAIT_CACHEOPS after.
+//
+// NOTE: nlines is encoded in a 4-bit field (max 16). DO NOT pass nlines > 16.
+static inline void __attribute__((always_inline)) evict_past_l2(const void * addr, uint64_t nlines, uint64_t stride) {
+    // dest=10 in bits 59:58, VA in bits 47:6, numlines-1 in bits 3:0
+    uint64_t csr_val = (0x2ULL << 58) | ((uint64_t) addr & 0xFFFFFFFFFFC0ULL) | ((nlines - 1) & 0xF);
+    uint64_t x31_val = stride & 0xFFFFFFFFFFC0ULL;
+
+    __asm__ __volatile__(
+        "mv x31, %[x31]\n"
+        "csrw 0x89F, %[val]\n"
+        :
+        : [x31] "r"(x31_val), [val] "r"(csr_val)
+        : "x31", "memory");
+}
+
+// Evict a contiguous region from both L1 and L2 so subsequent loads fetch
+// from L3/DRAM.  Both L1 and L2 are incoherent on ET-SoC-1 (L2 is per-shire),
+// so every op must evict its inputs before reading if a prior op in the same
+// uberkernel batch may have written to them via fsw.ps or tensor_store.
+//
+// Handles regions larger than the 16-line hardware limit by issuing multiple
+// evict_past_l2 calls.
+static void evict_region_past_l2(const void * addr, size_t bytes) {
+    if (!addr || bytes == 0) {
+        return;
+    }
+
+    const uint64_t CL     = 64;
+    uint64_t       base   = (uint64_t) addr & ~(CL - 1);
+    uint64_t       end    = ((uint64_t) addr + bytes + CL - 1) & ~(CL - 1);
+    uint64_t       nlines = (end - base) / CL;
+    // FENCE;
+    for (uint64_t off = 0; off < nlines; off += 16) {
+        uint64_t batch = nlines - off;
+        if (batch > 16) {
+            batch = 16;
+        }
+        evict_past_l2((const void *) (base + off * CL), batch, CL);
+    }
+}
+
+#endif  // PLATFORM_H

diff --git a/ggml/src/ggml-et/et-kernels/src/quants.h b/ggml/src/ggml-et/et-kernels/src/quants.h
new file mode 100644 (file)
index 0000000..692ca00
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/quants.h
@@ -0,0 +1,72 @@
+// Scalar dequantization helpers and ET-side block-size aliases.
+
+#ifndef QUANTS_H
+#define QUANTS_H
+
+#include "math_fp.h"
+
+#include <stdint.h>
+
+#define GGML_COMMON_DECL_C
+#include "ggml-common.h"
+
+// 64-byte (one cache line) F16 / F32 block sizes.
+#define QK_F16 32
+#define QK_F32 16
+
+static inline void dequantize_q8_0_block(const block_q8_0 * block, float * dst) {
+    const float scale = fp16_to_fp32(block->d);
+
+    for (int i = 0; i < QK8_0; i++) {
+        dst[i] = scale * (float) block->qs[i];
+    }
+}
+
+// Low nibbles -> dst[0..15], high nibbles -> dst[16..31].
+static inline void dequantize_q4_0_block(const block_q4_0 * block, float * dst) {
+    const float scale = fp16_to_fp32(block->d);
+
+    for (int i = 0; i < QK4_0 / 2; i++) {
+        const uint8_t byte = block->qs[i];
+        dst[i]             = scale * (float) ((int) (byte & 0xF) - 8);
+        dst[i + QK4_0 / 2] = scale * (float) ((int) (byte >> 4) - 8);
+    }
+}
+
+// Unpack the 6-bit scale/min pair for Q4_K group j (groups 4-7 split their high bits).
+static inline void get_scale_min_k4(int j, const uint8_t * q, uint8_t * d, uint8_t * m) {
+    if (j < 4) {
+        *d = q[j] & 63;
+        *m = q[j + 4] & 63;
+    } else {
+        *d = (q[j + 4] & 0xF) | ((q[j - 4] >> 6) << 4);
+        *m = (q[j + 4] >> 4) | ((q[j] >> 6) << 4);
+    }
+}
+
+static inline void dequantize_q4_K_block(const block_q4_K * block, float * dst) {
+    const uint8_t * q   = block->qs;
+    const float     d   = fp16_to_fp32(block->d);
+    const float     min = fp16_to_fp32(block->dmin);
+
+    int     is = 0;
+    uint8_t sc, m;
+    for (int j = 0; j < QK_K; j += 64) {
+        get_scale_min_k4(is + 0, block->scales, &sc, &m);
+        const float d1 = d * sc;
+        const float m1 = min * m;
+        get_scale_min_k4(is + 1, block->scales, &sc, &m);
+        const float d2 = d * sc;
+        const float m2 = min * m;
+        for (int l = 0; l < 32; ++l) {
+            *dst++ = d1 * (q[l] & 0xF) - m1;
+        }
+        for (int l = 0; l < 32; ++l) {
+            *dst++ = d2 * (q[l] >> 4) - m2;
+        }
+        q += 32;
+        is += 2;
+    }
+}
+
+#endif  // QUANTS_H

diff --git a/ggml/src/ggml-et/et-kernels/src/repeat_f32.c b/ggml/src/ggml-et/et-kernels/src/repeat_f32.c
new file mode 100644 (file)
index 0000000..4c9b071
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/repeat_f32.c
@@ -0,0 +1,118 @@
+//******************************************************************************
+// Repeat F32 Kernel
+// Tiles src0 into dst: dst.ne[i] = src0.ne[i] * nr[i] for each dimension.
+// All copies are cacheline-aligned (ne00 % 16 == 0).
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+#include <string.h>
+
+struct ggml_et_repeat_params {
+    struct ggml_tensor src0;  // F32 input tensor (tile)
+    struct ggml_tensor dst;   // F32 output tensor (tiled result)
+};
+
+// Copy n floats from src to dst using 8-wide vector loads/stores.
+// n must be a multiple of 16 (cacheline-aligned).
+static inline void copy_row_aligned(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps f11, %[src_vec]\n"
+            "fsw.ps f11, %[dst_vec]\n"
+            : [dst_vec] "=m"(*(float (*)[8]) & dst[i])
+            : [src_vec] "m"(*(const float (*)[8]) & src[i])
+            : "f11");
+    }
+}
+
+// Broadcast a single scalar to n floats using fbc.ps (broadcast to all lanes).
+// n must be a multiple of 16 (cacheline-aligned).
+static inline void broadcast_scalar_aligned(float * dst, float val, int32_t n) {
+    __asm__ volatile("fbc.ps f11, %[v]\n" : : [v] "m"(val) : "f11");
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile("fsw.ps f11, %[dst_vec]\n" : [dst_vec] "=m"(*(float (*)[8]) & dst[i])::"f11");
+    }
+}
+
+int entry_point(struct ggml_et_repeat_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3];
+    const int64_t ne0 = dst->ne[0], ne1 = dst->ne[1], ne2 = dst->ne[2], ne3 = dst->ne[3];
+
+    // src0 strides in bytes
+    const size_t nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    // dst strides in bytes
+    const size_t dnb0 = dst->nb[0], dnb1 = dst->nb[1], dnb2 = dst->nb[2], dnb3 = dst->nb[3];
+
+    // Repeat counts per dimension
+    const int32_t nr0 = (int32_t) (ne0 / ne00);
+    const int32_t nr1 = (int32_t) (ne1 / ne01);
+    const int32_t nr2 = (int32_t) (ne2 / ne02);
+    const int32_t nr3 = (int32_t) (ne3 / ne03);
+
+    // Total output rows across all dimensions (excluding dim 0 tiling)
+    const int64_t total_rows = ne1 * ne2 * ne3;
+
+    for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+        // Decompose linear row index into dst (i1, i2, i3)
+        int64_t i1 = row % ne1;
+        int64_t i2 = (row / ne1) % ne2;
+        int64_t i3 = row / (ne1 * ne2);
+
+        // Map dst indices back to src0 indices (modular wrap)
+        int64_t k1 = i1 % ne01;
+        int64_t k2 = i2 % ne02;
+        int64_t k3 = i3 % ne03;
+
+        const float * src_row = (const float *) ((const char *) src0_data + k1 * nb01 + k2 * nb02 + k3 * nb03);
+        float *       dst_row = (float *) ((char *) dst_data + i1 * dnb1 + i2 * dnb2 + i3 * dnb3);
+
+        if (ne00 == 1) {
+            // Scalar broadcast: splat single value across entire dst row
+            broadcast_scalar_aligned(dst_row, *src_row, (int32_t) ne0);
+        } else if (nr0 == 1) {
+            // No tiling along dim 0 - single cacheline-aligned row copy
+            copy_row_aligned(dst_row, src_row, (int32_t) ne00);
+        } else {
+            // Tile ne00-sized chunks across dim 0
+            for (int32_t i0 = 0; i0 < nr0; i0++) {
+                copy_row_aligned(dst_row + i0 * ne00, src_row, (int32_t) ne00);
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/rms_norm_f32.c b/ggml/src/ggml-et/et-kernels/src/rms_norm_f32.c
new file mode 100644 (file)
index 0000000..d203759
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/rms_norm_f32.c
@@ -0,0 +1,270 @@
+//******************************************************************************
+// RMS Norm F32 Kernel
+// Root Mean Square normalization: y[i] = x[i] / sqrt(mean(x^2) + eps)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+// RMS norm kernel parameters structure
+struct ggml_et_rms_norm_params {
+    struct ggml_tensor src0;  // F32 input tensor
+    struct ggml_tensor dst;   // F32 output tensor
+    float              eps;   // Epsilon parameter for numerical stability
+};
+
+int entry_point(struct ggml_et_rms_norm_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+    float                eps  = params->eps;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+
+    if (eps < 0.0f) {
+        return -1;  // Invalid epsilon
+    }
+
+    const int64_t ne0 = dst->ne[0];  // Inner dimension (row size)
+    const int64_t ne1 = dst->ne[1];  // Dimension 1
+    const int64_t ne2 = dst->ne[2];  // Dimension 2
+    const int64_t ne3 = dst->ne[3];  // Dimension 3
+
+    // Get dst strides (in bytes)
+    const size_t nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+
+    // Get src0 strides (in bytes)
+    const size_t nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+
+    // Verify that src0 and dst have same shape (required for RMS norm)
+    if (src0->ne[0] != ne0 || src0->ne[1] != ne1 || src0->ne[2] != ne2 || src0->ne[3] != ne3) {
+        return -1;  // Shape mismatch
+    }
+
+    // RMS norm processes rows independently
+    // Parallelize across rows using simple striding
+    // TODO: ensure lines don't cross cache lines
+    // Precompute reciprocal of row length (constant across all rows)
+    const float   inv_ne0    = et_fdiv(1.0f, (float) (int32_t) ne0);
+    const int32_t total_rows = (int32_t) (ne1 * ne2 * ne3);
+
+    // Intra-row cooperation only works within a single shire (barrier + L2SCP
+    // are shire-local). Use per-shire thread count for the threshold.
+    const int shire_threads = SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;  // 64
+
+    if (total_rows >= shire_threads) {
+        // Row-parallel: each thread processes whole rows
+        for (int64_t i3 = 0; i3 < ne3; i3++) {
+            for (int64_t i2 = 0; i2 < ne2; i2++) {
+                for (int64_t i1 = thread_id; i1 < ne1; i1 += num_threads) {
+                    const float * src_ptr =
+                        (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                    float * dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+                    // Set mask to enable all 8 vector lanes
+                    unsigned long saved_mask;
+                    __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+                    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+                    // Step 1: Compute sum of squares using 8-wide vectors
+                    __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[x_vec]\n"
+                            "fmadd.ps f10, f11, f11, f10\n"
+                            :
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                            : "f10", "f11");
+                    }
+
+                    // Horizontal reduce
+                    float sum;
+                    __asm__ __volatile__(
+                        "fswizz.ps f1, f10, 0xB1 \n\t"
+                        "fadd.ps   f2, f10, f1, rne \n\t"
+                        "fswizz.ps f3, f2, 0x4E \n\t"
+                        "fadd.ps   f4, f2, f3, rne \n\t"
+                        "fmvz.x.ps t0, f4, 4 \n\t"
+                        "fbcx.ps   f5, t0 \n\t"
+                        "fadd.ps   %[vout], f4, f5, rne \n\t"
+                        : [vout] "=f"(sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+                    // Step 2: scale = rsqrt(mean + eps)
+                    const float scale = et_powf(sum * inv_ne0 + eps, -0.5f);
+
+                    if (!(scale > 0.0f)) {
+                        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+                        return -1;
+                    }
+
+                    // Step 3: Apply scaling: broadcast scale once, reuse across loop
+                    uint32_t scale_bits;
+                    __asm__ volatile("fmv.x.s %0, %1" : "=r"(scale_bits) : "f"(scale));
+                    __asm__ volatile("fbcx.ps f13, %[sb]\n" : : [sb] "r"(scale_bits) : "f13");
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f12, %[x_vec]\n"
+                            "fmul.ps f14, f12, f13\n"
+                            "fsw.ps f14, %[result]\n"
+                            : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                            : "f12", "f14");
+                    }
+
+                    __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+                }
+            }
+        }
+    } else {
+        // Intra-row: threads within each shire cooperate on rows via L2 SCP.
+        // L2 SCP + barrier are shire-local, so use shire-local thread index.
+        int shire_tid       = thread_id % shire_threads;  // 0..63 within this shire
+        int threads_per_row = shire_threads / total_rows;
+        int my_row          = shire_tid / threads_per_row;
+        int local_tid       = shire_tid % threads_per_row;
+        int group_base      = my_row * threads_per_row;  // shire-local group base
+
+        // Excess threads within this shire, barrier and leave
+        if (my_row >= total_rows) {
+            FENCE;
+            et_barrier(ET_BARRIER_SHIRE);
+            return 0;
+        }
+
+        // Unflatten row index
+        int64_t i1 = my_row % ne1;
+        int64_t i2 = (my_row / ne1) % ne2;
+        int64_t i3 = my_row / (ne1 * ne2);
+
+        const float * src_ptr = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+        float *       dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+        // Chunk boundaries aligned to 16 floats (64-byte cache line)
+        const int32_t elems_per_cl   = 16;
+        int32_t       total_cls      = ((int32_t) ne0 + elems_per_cl - 1) / elems_per_cl;
+        int32_t       cls_per_thread = (total_cls + threads_per_row - 1) / threads_per_row;
+        int32_t       my_start       = local_tid * cls_per_thread * elems_per_cl;
+        int32_t       my_end         = my_start + cls_per_thread * elems_per_cl;
+        if (my_end > (int32_t) ne0) {
+            my_end = (int32_t) ne0;
+        }
+        if (my_start >= (int32_t) ne0) {
+            my_start = 0;
+            my_end   = 0;
+        }
+
+        unsigned long saved_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+        // Phase 1: each thread computes partial sum of squares on its chunk
+        __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+        for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+            __asm__ volatile(
+                "flw.ps f11, %[x_vec]\n"
+                "fmadd.ps f10, f11, f11, f10\n"
+                :
+                : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                : "f10", "f11");
+        }
+
+        // Horizontal reduce to scalar
+        float partial_sum;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(partial_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+        // Phase 2: write partial sum to L2 SCP, evict from L1D
+        volatile float * my_slot = (volatile float *) et_shire_l2scp_local((uint64_t) shire_tid * 64);
+        *my_slot                 = partial_sum;
+        FENCE;
+        evict_to_l2((const void *) my_slot, 1, 64);
+        WAIT_CACHEOPS;
+
+        et_barrier(ET_BARRIER_SHIRE);
+
+        // Phase 3: ALL threads read partial sums, compute scale, apply to own chunk.
+        // Each thread independently reduces to avoid a second barrier.
+        int workers = threads_per_row < total_cls ? threads_per_row : total_cls;
+
+        // Evict stale L1D entries for worker slots
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            evict_to_l2((const void *) slot, 1, 64);
+        }
+        WAIT_CACHEOPS;
+
+        // Every thread reduces the same partial sums -> same scale
+        float total_sum = 0.0f;
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            total_sum += *slot;
+        }
+
+        const float scale = et_powf(total_sum * inv_ne0 + eps, -0.5f);
+        if (!(scale > 0.0f)) {
+            __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+            return -1;
+        }
+
+        // Each thread applies scale to its own chunk only
+        if (my_start < my_end) {
+            uint32_t scale_bits;
+            __asm__ volatile("fmv.x.s %0, %1" : "=r"(scale_bits) : "f"(scale));
+            __asm__ volatile("fbcx.ps f13, %[sb]\n" : : [sb] "r"(scale_bits) : "f13");
+
+            for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+                __asm__ volatile(
+                    "flw.ps f12, %[x_vec]\n"
+                    "fmul.ps f14, f12, f13\n"
+                    "fsw.ps f14, %[result]\n"
+                    : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                    : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                    : "f12", "f14");
+            }
+        }
+
+        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/rms_norm_mul_f32.c b/ggml/src/ggml-et/et-kernels/src/rms_norm_mul_f32.c
new file mode 100644 (file)
index 0000000..87e5772
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/rms_norm_mul_f32.c
@@ -0,0 +1,290 @@
+
+// Fused RMS Norm + MUL F32 Kernel
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+// Fused RMS norm + MUL kernel parameters structure
+struct ggml_et_rms_norm_mul_params {
+    struct ggml_tensor src0;  // F32 input tensor (to be normalized)
+    struct ggml_tensor src1;  // F32 weights tensor (element-wise multiply)
+    struct ggml_tensor dst;   // F32 output tensor
+    float              eps;   // Epsilon for numerical stability
+};
+
+static inline size_t tensor_bytes(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+int entry_point(struct ggml_et_rms_norm_mul_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * dst  = &params->dst;
+
+    float eps = params->eps;
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * src1_data = (float *) src1->data;
+    float * dst_data  = (float *) dst->data;
+    // #ifdef ET_UBERKERNEL
+    //     evict_region_past_l2(src0_data, tensor_bytes(src0));
+    //     evict_region_past_l2(src1_data, tensor_bytes(src1));
+    //     // WAIT_CACHEOPS;
+    //     FENCE;
+    //     // et_barrier(ET_BARRIER_GLOBAL);
+    // #endif
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    if (eps < 0.0f) {
+        return -1;  // Invalid epsilon
+    }
+
+    const int64_t ne0 = dst->ne[0];  // Inner dimension (row size)
+    const int64_t ne1 = dst->ne[1];  // Dimension 1
+    const int64_t ne2 = dst->ne[2];  // Dimension 2
+    const int64_t ne3 = dst->ne[3];  // Dimension 3
+
+    // Get dst strides (in bytes)
+    const size_t nb0 = dst->nb[0], nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+
+    // Get src0 strides (in bytes)
+    const size_t nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+
+    // Get src1 (weights) strides (in bytes), supports broadcasting in dims 1,2,3
+    const size_t nb10 = src1->nb[0], nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3];
+
+    // Verify that src0 and dst have same shape (required for RMS norm)
+    if (src0->ne[0] != ne0 || src0->ne[1] != ne1 || src0->ne[2] != ne2 || src0->ne[3] != ne3) {
+        return -1;  // Shape mismatch
+    }
+    // et_barrier(ET_BARRIER_GLOBAL);
+
+    const float   inv_ne0       = et_fdiv(1.0f, (float) (int32_t) ne0);
+    const int32_t total_rows    = (int32_t) (ne1 * ne2 * ne3);
+    const int     shire_threads = SOC_MINIONS_PER_SHIRE * NUM_HARTS_PER_MINION;
+
+    if (total_rows >= shire_threads) {
+        // Row-parallel: each thread processes whole rows
+        for (int64_t i3 = 0; i3 < ne3; i3++) {
+            for (int64_t i2 = 0; i2 < ne2; i2++) {
+                for (int64_t i1 = thread_id; i1 < ne1; i1 += num_threads) {
+                    const float * src_ptr =
+                        (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+                    float * dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+                    const float * wgt_ptr = (const float *) ((const char *) src1_data + (i3 % src1->ne[3]) * nb13 +
+                                                             (i2 % src1->ne[2]) * nb12 + (i1 % src1->ne[1]) * nb11);
+
+                    unsigned long saved_mask;
+                    __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+                    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+                    // Sum of squares
+                    __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[x_vec]\n"
+                            "fmadd.ps f10, f11, f11, f10\n"
+                            :
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                            : "f10", "f11");
+                    }
+
+                    float sum;
+                    __asm__ __volatile__(
+                        "fswizz.ps f1, f10, 0xB1 \n\t"
+                        "fadd.ps   f2, f10, f1, rne \n\t"
+                        "fswizz.ps f3, f2, 0x4E \n\t"
+                        "fadd.ps   f4, f2, f3, rne \n\t"
+                        "fmvz.x.ps t0, f4, 4 \n\t"
+                        "fbcx.ps   f5, t0 \n\t"
+                        "fadd.ps   %[vout], f4, f5, rne \n\t"
+                        : [vout] "=f"(sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+                    const float scale = et_powf(sum * inv_ne0 + eps, -0.5f);
+                    if (!(scale > 0.0f)) {
+                        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+                        return -1;
+                    }
+
+                    uint32_t scale_bits;
+                    __asm__ volatile("fmv.x.s %0, %1" : "=r"(scale_bits) : "f"(scale));
+                    __asm__ volatile("fbcx.ps f13, %[sb]\n" : : [sb] "r"(scale_bits) : "f13");
+
+                    for (int32_t i0 = 0; i0 < (int32_t) ne0; i0 += 8) {
+                        __asm__ volatile(
+                            "flw.ps f12, %[x_vec]\n"
+                            "flw.ps f15, %[w_vec]\n"
+                            "fmul.ps f14, f12, f13\n"
+                            "fmul.ps f14, f14, f15\n"
+                            "fsw.ps f14, %[result]\n"
+                            : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0]), [w_vec] "m"(*(const float (*)[8]) &
+                                                                                            wgt_ptr[i0])
+                            : "f12", "f14", "f15");
+                    }
+                    // #ifdef ET_UBERKERNEL
+                    //                 FENCE;
+                    //                 evict_region_past_l2(dst_ptr, (size_t)ne0 * sizeof(float));
+                    //                 WAIT_CACHEOPS;
+                    //                 FENCE;
+                    // #endif
+                    __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+                }
+            }
+        }
+    } else {
+        // Intra-row: threads within each shire cooperate on rows via L2 SCP.
+        // L2 SCP + barrier are shire-local, so use shire-local thread index.
+        int shire_tid       = thread_id % shire_threads;
+        int threads_per_row = shire_threads / total_rows;
+        int my_row          = shire_tid / threads_per_row;
+        int local_tid       = shire_tid % threads_per_row;
+        int group_base      = my_row * threads_per_row;
+
+        // Excess threads within this shire
+        if (my_row >= total_rows) {
+            __asm__ __volatile__("fence\n" ::: "memory");
+            et_barrier(ET_BARRIER_SHIRE);
+            return 0;
+        }
+
+        // Unflatten row index
+        int64_t i1 = my_row % ne1;
+        int64_t i2 = (my_row / ne1) % ne2;
+        int64_t i3 = my_row / (ne1 * ne2);
+
+        const float * src_ptr = (const float *) ((const char *) src0_data + i3 * nb03 + i2 * nb02 + i1 * nb01);
+        float *       dst_ptr = (float *) ((char *) dst_data + i3 * nb3 + i2 * nb2 + i1 * nb1);
+
+        const float * wgt_ptr = (const float *) ((const char *) src1_data + (i3 % src1->ne[3]) * nb13 +
+                                                 (i2 % src1->ne[2]) * nb12 + (i1 % src1->ne[1]) * nb11);
+
+        // Chunk boundaries aligned to 16 floats (64-byte cache line)
+        const int32_t elems_per_cl   = 16;
+        int32_t       total_cls      = ((int32_t) ne0 + elems_per_cl - 1) / elems_per_cl;
+        int32_t       cls_per_thread = (total_cls + threads_per_row - 1) / threads_per_row;
+        int32_t       my_start       = local_tid * cls_per_thread * elems_per_cl;
+        int32_t       my_end         = my_start + cls_per_thread * elems_per_cl;
+        if (my_end > (int32_t) ne0) {
+            my_end = (int32_t) ne0;
+        }
+        if (my_start >= (int32_t) ne0) {
+            my_start = 0;
+            my_end   = 0;
+        }
+
+        unsigned long saved_mask;
+        __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+        // Phase 1: partial sum of squares on own chunk
+        __asm__ volatile("fbci.pi f10, 0" ::: "f10");
+        for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+            __asm__ volatile(
+                "flw.ps f11, %[x_vec]\n"
+                "fmadd.ps f10, f11, f11, f10\n"
+                :
+                : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+                : "f10", "f11");
+        }
+
+        float partial_sum;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(partial_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+        // Phase 2: write partial sum to L2 SCP, evict from L1D
+        volatile float * my_slot = (volatile float *) et_shire_l2scp_local((uint64_t) shire_tid * 64);
+        *my_slot                 = partial_sum;
+        __asm__ __volatile__("fence\n" ::: "memory");
+        evict_to_l2((const void *) my_slot, 1, 64);
+        WAIT_CACHEOPS;
+
+        et_barrier(ET_BARRIER_SHIRE);
+
+        // Phase 3: all threads read partial sums, compute scale, apply to own chunk
+        int workers = threads_per_row < total_cls ? threads_per_row : total_cls;
+
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            evict_to_l2((const void *) slot, 1, 64);
+        }
+        WAIT_CACHEOPS;
+
+        float total_sum = 0.0f;
+        for (int t = 0; t < workers; t++) {
+            volatile float * slot = (volatile float *) et_shire_l2scp_local((uint64_t) (group_base + t) * 64);
+            total_sum += *slot;
+        }
+
+        const float scale = et_powf(total_sum * inv_ne0 + eps, -0.5f);
+        if (!(scale > 0.0f)) {
+            __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+            return -1;
+        }
+
+        // Apply scale * weights to own chunk
+        if (my_start < my_end) {
+            uint32_t scale_bits;
+            __asm__ volatile("fmv.x.s %0, %1" : "=r"(scale_bits) : "f"(scale));
+            __asm__ volatile("fbcx.ps f13, %[sb]\n" : : [sb] "r"(scale_bits) : "f13");
+
+            for (int32_t i0 = my_start; i0 < my_end; i0 += 8) {
+                __asm__ volatile(
+                    "flw.ps f12, %[x_vec]\n"
+                    "flw.ps f15, %[w_vec]\n"
+                    "fmul.ps f14, f12, f13\n"
+                    "fmul.ps f14, f14, f15\n"
+                    "fsw.ps f14, %[result]\n"
+                    : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+                    : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0]), [w_vec] "m"(*(const float (*)[8]) & wgt_ptr[i0])
+                    : "f12", "f14", "f15");
+            }
+            // #ifdef ET_UBERKERNEL
+            //             FENCE;
+            //             evict_region_past_l2(dst_ptr + my_start, (size_t)(my_end - my_start) * sizeof(float));
+            //             WAIT_CACHEOPS;
+            //             FENCE;
+            // #endif
+        }
+
+        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/rope_f32.c b/ggml/src/ggml-et/et-kernels/src/rope_f32.c
new file mode 100644 (file)
index 0000000..227d6d1
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/rope_f32.c
@@ -0,0 +1,656 @@
+//******************************************************************************
+// ROPE (Rotary Position Encoding) Kernel
+// Experiment 1:
+//   - Keep old scheduling and rotate logic
+//   - ONLY SIMD-ize sin/cos approximation inside compute_rope_cache()
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <etsoc/common/utils.h>
+#include <stdint.h>
+
+// ROPE constants (matching GGML definitions)
+#define GGML_ROPE_TYPE_NEOX   2
+#define GGML_ROPE_TYPE_MROPE  8
+#define GGML_ROPE_TYPE_IMROPE 40
+#define MAX_ROPE_HALF_DIMS    256  // supports up to n_dims=512
+
+#define ROPE_VEC_WIDTH 8
+
+#define ROPE_PI         3.14159265358979323846f
+#define ROPE_TWO_PI     6.28318530717958647693f
+#define ROPE_PI_OVER_2  1.57079632679489661923f
+#define ROPE_INV_TWO_PI 0.15915494309189533577f
+
+// ROPE operation parameters structure (matches ggml-et-ops.h)
+typedef struct {
+    int32_t n_past;
+    int32_t n_dims;  // Number of dimensions to apply ROPE to (must be even)
+    int32_t mode;    // ROPE mode (0=normal, 2=neox)
+    int32_t n_ctx;
+    int32_t n_ctx_orig;
+    float   freq_base;    // Base frequency (usually 10000.0f)
+    float   freq_scale;   // Frequency scaling factor
+    float   ext_factor;   // Extension factor for YaRN
+    float   attn_factor;  // Attention factor for YaRN
+    float   beta_fast;    // Fast beta for YaRN
+    float   beta_slow;    // Slow beta for YaRN
+    int32_t sections[4];  // Sections for multi-modal ROPE
+} rope_params_t;
+
+// ROPE kernel parameters structure (matches ggml_et_rope_params)
+struct ggml_et_rope_params {
+    struct ggml_tensor src0;  // F32 input tensor
+    struct ggml_tensor src1;  // I32 position tensor
+    struct ggml_tensor src2;  // F32 frequency factors (optional)
+    struct ggml_tensor dst;   // F32 output tensor
+    rope_params_t      rope_params;
+};
+
+//------------------------------------------------------------------------------
+// Existing scalar helpers
+//------------------------------------------------------------------------------
+
+// floor/ceil with ±inf and NaN passthrough.
+static inline float rope_floorf(float x) {
+    union {
+        float    f;
+        uint32_t u;
+    } v = { .f = x };
+
+    const uint32_t expo = (v.u >> 23) & 0xFF;
+    if (expo == 0xFF) {
+        return x;  // inf or NaN
+    }
+    if (expo >= 23 + 127) {
+        return x;  // already integer-valued
+    }
+    int i = (int) x;
+    return (x < 0.0f && (float) i != x) ? (float) (i - 1) : (float) i;
+}
+
+static inline float rope_ceilf(float x) {
+    union {
+        float    f;
+        uint32_t u;
+    } v = { .f = x };
+
+    const uint32_t expo = (v.u >> 23) & 0xFF;
+    if (expo == 0xFF) {
+        return x;  // inf or NaN
+    }
+    if (expo >= 23 + 127) {
+        return x;  // already integer-valued
+    }
+    int i = (int) x;
+    return (x > 0.0f && (float) i != x) ? (float) (i + 1) : (float) i;
+}
+
+static inline float rope_yarn_ramp(const float low, const float high, const int i0) {
+    float denom = high - low;
+    if (denom < 0.001f) {
+        denom = 0.001f;
+    }
+
+    const float y       = et_fdiv((float) (i0 / 2) - low, denom);
+    const float clamped = y < 0.0f ? 0.0f : (y > 1.0f ? 1.0f : y);
+    return 1.0f - clamped;
+}
+
+// Matches CPU reference (ggml_rope_yarn_corr_dim).
+static inline float rope_yarn_corr_dim(int n_dims, int n_ctx_orig, float beta, float freq_base) {
+    return (float) n_dims *
+           et_fdiv(et_logf(et_fdiv((float) n_ctx_orig, beta * ROPE_TWO_PI)), 2.0f * et_logf(freq_base));
+}
+
+static inline void rope_yarn_corr_dims(int   n_dims,
+                                       int   n_ctx_orig,
+                                       float freq_base,
+                                       float beta_fast,
+                                       float beta_slow,
+                                       float dims[2]) {
+    // Match CPU: floor on start, ceil on end, then clamp to [0, n_dims-1].
+    float start = rope_floorf(rope_yarn_corr_dim(n_dims, n_ctx_orig, beta_fast, freq_base));
+    float end   = rope_ceilf(rope_yarn_corr_dim(n_dims, n_ctx_orig, beta_slow, freq_base));
+
+    dims[0] = start > 0.0f ? start : 0.0f;
+    dims[1] = end < (float) (n_dims - 1) ? end : (float) (n_dims - 1);
+}
+
+//------------------------------------------------------------------------------
+// SIMD sin/cos approximation
+//------------------------------------------------------------------------------
+
+static const float rope_ps_one[ROPE_VEC_WIDTH]
+    __attribute__((aligned(32))) = { 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f };
+static const float rope_ps_c3[ROPE_VEC_WIDTH]
+    __attribute__((aligned(32))) = { 1.0f / 6.0f, 1.0f / 6.0f, 1.0f / 6.0f, 1.0f / 6.0f,
+                                     1.0f / 6.0f, 1.0f / 6.0f, 1.0f / 6.0f, 1.0f / 6.0f };
+static const float rope_ps_c5[ROPE_VEC_WIDTH]
+    __attribute__((aligned(32))) = { 1.0f / 120.0f, 1.0f / 120.0f, 1.0f / 120.0f, 1.0f / 120.0f,
+                                     1.0f / 120.0f, 1.0f / 120.0f, 1.0f / 120.0f, 1.0f / 120.0f };
+static const float rope_ps_c7[ROPE_VEC_WIDTH]
+    __attribute__((aligned(32))) = { 1.0f / 5040.0f, 1.0f / 5040.0f, 1.0f / 5040.0f, 1.0f / 5040.0f,
+                                     1.0f / 5040.0f, 1.0f / 5040.0f, 1.0f / 5040.0f, 1.0f / 5040.0f };
+static const float rope_ps_c9[ROPE_VEC_WIDTH]
+    __attribute__((aligned(32))) = { 1.0f / 362880.0f, 1.0f / 362880.0f, 1.0f / 362880.0f, 1.0f / 362880.0f,
+                                     1.0f / 362880.0f, 1.0f / 362880.0f, 1.0f / 362880.0f, 1.0f / 362880.0f };
+static const float rope_ps_c11[ROPE_VEC_WIDTH]
+    __attribute__((aligned(32))) = { 1.0f / 39916800.0f, 1.0f / 39916800.0f, 1.0f / 39916800.0f, 1.0f / 39916800.0f,
+                                     1.0f / 39916800.0f, 1.0f / 39916800.0f, 1.0f / 39916800.0f, 1.0f / 39916800.0f };
+
+static inline uint64_t rope_ps_enter_fullmask(void) {
+    uint64_t old_mask;
+    __asm__ volatile(
+        "mova.x.m %0           \n\t"
+        "li       t0, -1       \n\t"
+        "mova.m.x t0           \n\t"
+        : "=r"(old_mask)
+        :
+        : "t0", "memory");
+    return old_mask;
+}
+
+static inline void rope_ps_leave_fullmask(uint64_t old_mask) {
+    __asm__ volatile("mova.m.x %0           \n\t" : : "r"(old_mask) : "memory");
+}
+
+static inline void rope_poly_sin_block8(float * out, const float * x) {
+    __asm__ volatile(
+        "flw.ps    f0,  %[x]           \n\t"
+        "fmul.ps   f1,  f0,  f0        \n\t"
+
+        "flw.ps    f2,  %[c11]         \n\t"
+        "flw.ps    f3,  %[c9]          \n\t"
+        "fnmsub.ps f2,  f1,  f2,  f3   \n\t"
+
+        "flw.ps    f3,  %[c7]          \n\t"
+        "fnmsub.ps f2,  f1,  f2,  f3   \n\t"
+
+        "flw.ps    f3,  %[c5]          \n\t"
+        "fnmsub.ps f2,  f1,  f2,  f3   \n\t"
+
+        "flw.ps    f3,  %[c3]          \n\t"
+        "fnmsub.ps f2,  f1,  f2,  f3   \n\t"
+
+        "flw.ps    f3,  %[one]         \n\t"
+        "fnmsub.ps f2,  f1,  f2,  f3   \n\t"
+
+        "fmul.ps   f4,  f0,  f2        \n\t"
+        "fsw.ps    f4,  %[out]         \n\t"
+        : [out] "=m"(*(float (*)[ROPE_VEC_WIDTH]) out)
+        : [x] "m"(*(const float (*)[ROPE_VEC_WIDTH]) x), [one] "m"(*(const float (*)[ROPE_VEC_WIDTH]) rope_ps_one),
+          [c3] "m"(*(const float (*)[ROPE_VEC_WIDTH]) rope_ps_c3),
+          [c5] "m"(*(const float (*)[ROPE_VEC_WIDTH]) rope_ps_c5),
+          [c7] "m"(*(const float (*)[ROPE_VEC_WIDTH]) rope_ps_c7),
+          [c9] "m"(*(const float (*)[ROPE_VEC_WIDTH]) rope_ps_c9),
+          [c11] "m"(*(const float (*)[ROPE_VEC_WIDTH]) rope_ps_c11)
+        : "f0", "f1", "f2", "f3", "f4", "memory");
+}
+
+static inline void rope_sincos_block8(float * sin8, float * cos8, const float * theta8) {
+    float sin_fold[ROPE_VEC_WIDTH] __attribute__((aligned(32)));
+    float cos_fold[ROPE_VEC_WIDTH] __attribute__((aligned(32)));
+    float sin_sign[ROPE_VEC_WIDTH] __attribute__((aligned(32)));
+    float cos_sign[ROPE_VEC_WIDTH] __attribute__((aligned(32)));
+
+    for (int i = 0; i < ROPE_VEC_WIDTH; ++i) {
+        float x = theta8[i];
+
+        if (x > ROPE_PI || x < -ROPE_PI) {
+            float cycles = x * ROPE_INV_TWO_PI;
+            int   n      = (int) cycles;
+            if (x < 0.0f) {
+                n--;
+            }
+            x = x - (float) n * ROPE_TWO_PI;
+        }
+
+        {
+            float y = x;
+            float s = 1.0f;
+            if (y > ROPE_PI_OVER_2) {
+                y = ROPE_PI - y;
+            } else if (y < -ROPE_PI_OVER_2) {
+                y = -ROPE_PI - y;
+                s = -1.0f;
+            }
+            sin_fold[i] = y;
+            sin_sign[i] = s;
+        }
+
+        {
+            float y = x + ROPE_PI_OVER_2;
+            if (y > ROPE_PI || y < -ROPE_PI) {
+                float cycles = y * ROPE_INV_TWO_PI;
+                int   n      = (int) cycles;
+                if (y < 0.0f) {
+                    n--;
+                }
+                y = y - (float) n * ROPE_TWO_PI;
+            }
+
+            float s = 1.0f;
+            if (y > ROPE_PI_OVER_2) {
+                y = ROPE_PI - y;
+            } else if (y < -ROPE_PI_OVER_2) {
+                y = -ROPE_PI - y;
+                s = -1.0f;
+            }
+            cos_fold[i] = y;
+            cos_sign[i] = s;
+        }
+    }
+
+    {
+        const uint64_t saved_mask = rope_ps_enter_fullmask();
+
+        rope_poly_sin_block8(sin8, sin_fold);
+        rope_poly_sin_block8(cos8, cos_fold);
+
+        __asm__ volatile(
+            "flw.ps    f0, %[sinv]         \n\t"
+            "flw.ps    f1, %[sinsgn]       \n\t"
+            "fmul.ps   f2, f0, f1          \n\t"
+            "fsw.ps    f2, %[sout]         \n\t"
+
+            "flw.ps    f3, %[cosv]         \n\t"
+            "flw.ps    f4, %[cossgn]       \n\t"
+            "fmul.ps   f5, f3, f4          \n\t"
+            "fsw.ps    f5, %[cout]         \n\t"
+            : [sout] "=m"(*(float (*)[ROPE_VEC_WIDTH]) sin8), [cout] "=m"(*(float (*)[ROPE_VEC_WIDTH]) cos8)
+            : [sinv] "m"(*(const float (*)[ROPE_VEC_WIDTH]) sin8),
+              [sinsgn] "m"(*(const float (*)[ROPE_VEC_WIDTH]) sin_sign),
+              [cosv] "m"(*(const float (*)[ROPE_VEC_WIDTH]) cos8),
+              [cossgn] "m"(*(const float (*)[ROPE_VEC_WIDTH]) cos_sign)
+            : "f0", "f1", "f2", "f3", "f4", "f5", "memory");
+
+        rope_ps_leave_fullmask(saved_mask);
+    }
+}
+
+//------------------------------------------------------------------------------
+// Cache build
+//------------------------------------------------------------------------------
+
+// scalar fallback for tail / tiny sizes
+static inline void rope_yarn_scalar(float       theta_extrap,
+                                    float       freq_scale,
+                                    const float corr_dims[2],
+                                    int64_t     i0,
+                                    float       ext_factor,
+                                    float       mscale,
+                                    float *     cos_theta,
+                                    float *     sin_theta) {
+    float theta_interp = freq_scale * theta_extrap;
+    float theta        = theta_interp;
+
+    if (ext_factor != 0.0f) {
+        float ramp_mix = rope_yarn_ramp(corr_dims[0], corr_dims[1], (int) i0) * ext_factor;
+        theta          = theta_interp * (1.0f - ramp_mix) + theta_extrap * ramp_mix;
+        mscale *= 1.0f + 0.1f * et_logf(et_fdiv(1.0f, freq_scale));
+    }
+
+    *cos_theta = et_cosf(theta) * mscale;
+    *sin_theta = et_sinf(theta) * mscale;
+}
+
+// Populate cos/sin cache for a given position using running theta product
+// Experiment 1:
+//   - theta construction and YaRN mixing stay scalar
+//   - actual sin/cos approximation is done in vec8 blocks
+static inline void compute_rope_cache(float *       cos_cache,
+                                      float *       sin_cache,
+                                      int32_t       n_dims,
+                                      float         theta_scale,
+                                      int32_t       pos,
+                                      const float * freq_factors,
+                                      float         freq_scale,
+                                      const float   corr_dims[2],
+                                      float         ext_factor,
+                                      float         attn_factor) {
+    const int32_t half_dims = n_dims / 2;
+    float         theta     = 1.0f;
+
+    int32_t dim_idx = 0;
+
+    for (; dim_idx + ROPE_VEC_WIDTH <= half_dims; dim_idx += ROPE_VEC_WIDTH) {
+        float theta_block[ROPE_VEC_WIDTH] __attribute__((aligned(32)));
+        float theta_local = theta;
+        float mscale      = attn_factor;
+
+        if (ext_factor != 0.0f) {
+            mscale *= 1.0f + 0.1f * et_logf(et_fdiv(1.0f, freq_scale));
+        }
+
+        for (int i = 0; i < ROPE_VEC_WIDTH; ++i) {
+            const int32_t pair_idx     = dim_idx + i;
+            const float   ff           = freq_factors ? freq_factors[pair_idx] : 1.0f;
+            const float   theta_base   = (float) pos * theta_local;
+            const float   theta_extrap = et_fdiv(theta_base, ff);
+
+            float theta_interp = freq_scale * theta_extrap;
+            float theta_mix    = theta_interp;
+
+            if (ext_factor != 0.0f) {
+                float ramp_mix = rope_yarn_ramp(corr_dims[0], corr_dims[1], pair_idx * 2) * ext_factor;
+                theta_mix      = theta_interp * (1.0f - ramp_mix) + theta_extrap * ramp_mix;
+            }
+
+            theta_block[i] = theta_mix;
+            theta_local *= theta_scale;
+        }
+
+        rope_sincos_block8(&sin_cache[dim_idx], &cos_cache[dim_idx], theta_block);
+
+        for (int i = 0; i < ROPE_VEC_WIDTH; ++i) {
+            sin_cache[dim_idx + i] *= mscale;
+            cos_cache[dim_idx + i] *= mscale;
+        }
+
+        theta = theta_local;
+    }
+
+    // tail fallback
+    for (; dim_idx < half_dims; ++dim_idx) {
+        const float ff         = freq_factors ? freq_factors[dim_idx] : 1.0f;
+        const float theta_base = (float) pos * theta;
+
+        rope_yarn_scalar(et_fdiv(theta_base, ff), freq_scale, corr_dims, dim_idx * 2, ext_factor, attn_factor,
+                         &cos_cache[dim_idx], &sin_cache[dim_idx]);
+
+        theta *= theta_scale;
+    }
+}
+
+//------------------------------------------------------------------------------
+// IMROPE cache build (interleaved multi-modal RoPE for Qwen3VL)
+//------------------------------------------------------------------------------
+
+// Builds cos/sin cache with 4 interleaved position channels.
+// Each dimension pair selects from {theta_t, theta_h, theta_w, theta_e}
+// using a mod-3 sector pattern, matching the CPU reference exactly.
+static inline void compute_imrope_cache(float *       cos_cache,
+                                        float *       sin_cache,
+                                        int32_t       n_dims,
+                                        float         theta_scale,
+                                        int32_t       pos_t,
+                                        int32_t       pos_h,
+                                        int32_t       pos_w,
+                                        int32_t       pos_e,
+                                        const int32_t sections[4],
+                                        const float * freq_factors,
+                                        float         freq_scale,
+                                        const float   corr_dims[2],
+                                        float         ext_factor,
+                                        float         attn_factor) {
+    const int32_t half_dims = n_dims / 2;
+    const int32_t sect_dims = sections[0] + sections[1] + sections[2] + sections[3];
+
+    float theta_t = (float) pos_t;
+    float theta_h = (float) pos_h;
+    float theta_w = (float) pos_w;
+    float theta_e = (float) pos_e;
+
+    int32_t dim_idx = 0;
+
+    for (; dim_idx + ROPE_VEC_WIDTH <= half_dims; dim_idx += ROPE_VEC_WIDTH) {
+        float theta_block[ROPE_VEC_WIDTH] __attribute__((aligned(32)));
+        float mscale = attn_factor;
+
+        if (ext_factor != 0.0f) {
+            mscale *= 1.0f + 0.1f * et_logf(et_fdiv(1.0f, freq_scale));
+        }
+
+        for (int i = 0; i < ROPE_VEC_WIDTH; ++i) {
+            const int32_t pair_idx = dim_idx + i;
+            const int32_t sector   = pair_idx % sect_dims;
+            const float   ff       = freq_factors ? freq_factors[pair_idx] : 1.0f;
+
+            // Interleaved sector assignment (mod-3 pattern)
+            float theta;
+            if (sector % 3 == 1 && sector < 3 * sections[1]) {
+                theta = theta_h;
+            } else if (sector % 3 == 2 && sector < 3 * sections[2]) {
+                theta = theta_w;
+            } else if (sector % 3 == 0 && sector < 3 * sections[0]) {
+                theta = theta_t;
+            } else {
+                theta = theta_e;
+            }
+
+            const float theta_extrap = et_fdiv(theta, ff);
+            float       theta_interp = freq_scale * theta_extrap;
+            float       theta_mix    = theta_interp;
+
+            if (ext_factor != 0.0f) {
+                float ramp_mix = rope_yarn_ramp(corr_dims[0], corr_dims[1], pair_idx * 2) * ext_factor;
+                theta_mix      = theta_interp * (1.0f - ramp_mix) + theta_extrap * ramp_mix;
+            }
+
+            theta_block[i] = theta_mix;
+
+            // All 4 thetas advance every iteration
+            theta_t *= theta_scale;
+            theta_h *= theta_scale;
+            theta_w *= theta_scale;
+            theta_e *= theta_scale;
+        }
+
+        rope_sincos_block8(&sin_cache[dim_idx], &cos_cache[dim_idx], theta_block);
+
+        for (int i = 0; i < ROPE_VEC_WIDTH; ++i) {
+            sin_cache[dim_idx + i] *= mscale;
+            cos_cache[dim_idx + i] *= mscale;
+        }
+    }
+
+    // Scalar tail
+    for (; dim_idx < half_dims; ++dim_idx) {
+        const int32_t sector = dim_idx % sect_dims;
+        const float   ff     = freq_factors ? freq_factors[dim_idx] : 1.0f;
+
+        float theta;
+        if (sector % 3 == 1 && sector < 3 * sections[1]) {
+            theta = theta_h;
+        } else if (sector % 3 == 2 && sector < 3 * sections[2]) {
+            theta = theta_w;
+        } else if (sector % 3 == 0 && sector < 3 * sections[0]) {
+            theta = theta_t;
+        } else {
+            theta = theta_e;
+        }
+
+        rope_yarn_scalar(et_fdiv(theta, ff), freq_scale, corr_dims, dim_idx * 2, ext_factor, attn_factor,
+                         &cos_cache[dim_idx], &sin_cache[dim_idx]);
+
+        theta_t *= theta_scale;
+        theta_h *= theta_scale;
+        theta_w *= theta_scale;
+        theta_e *= theta_scale;
+    }
+}
+
+//------------------------------------------------------------------------------
+// Entry point
+//------------------------------------------------------------------------------
+
+int entry_point(struct ggml_et_rope_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return -1;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * src2 = &params->src2;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_I32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float *   src0_data    = (const float *) src0->data;
+    const int32_t * src1_data    = (const int32_t *) src1->data;
+    const float *   freq_factors = (src2 && src2->data) ? (const float *) src2->data : NULL;
+    float *         dst_data     = (float *) dst->data;
+
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;
+    }
+#ifdef ET_UBERKERNEL
+    const size_t src0_bytes = (size_t) src0->ne[0] * src0->ne[1] * src0->ne[2] * src0->ne[3] * src0->nb[0];
+    const size_t src1_bytes = (size_t) src1->ne[0] * src1->ne[1] * src1->ne[2] * src1->ne[3] * src1->nb[0];
+    evict_region_past_l2(src0_data, src0_bytes);
+    evict_region_past_l2(src1_data, src1_bytes);
+    WAIT_CACHEOPS;
+    FENCE;
+    et_barrier(ET_BARRIER_GLOBAL);
+#endif
+    const int64_t head_dim = src0->ne[0];
+    const int64_t heads    = src0->ne[1];
+    const int64_t seq_len  = src0->ne[2];
+    const int64_t batch    = src0->ne[3];
+
+    const rope_params_t * rope_params = &params->rope_params;
+    const int32_t         n_dims      = rope_params->n_dims;
+    const float           freq_base   = rope_params->freq_base;
+    const float           freq_scale  = rope_params->freq_scale;
+    const int32_t         mode        = rope_params->mode;
+
+    if (n_dims <= 0 || n_dims > head_dim || (n_dims & 1) != 0) {
+        return -1;
+    }
+
+    if (n_dims / 2 > MAX_ROPE_HALF_DIMS) {
+        return -1;
+    }
+
+    float cos_cache[MAX_ROPE_HALF_DIMS];
+    float sin_cache[MAX_ROPE_HALF_DIMS];
+
+    float corr_dims[2];
+    rope_yarn_corr_dims(n_dims, rope_params->n_ctx_orig, freq_base, rope_params->beta_fast, rope_params->beta_slow,
+                        corr_dims);
+    et_barrier(ET_BARRIER_GLOBAL);
+
+    // Distribute by individual heads: total = batch * seq_len * heads.
+    const int64_t total_heads = batch * seq_len * heads;
+    const int64_t start_wu    = (total_heads * thread_id) / num_threads;
+    const int64_t end_wu      = (total_heads * (thread_id + 1)) / num_threads;
+
+    if (start_wu >= end_wu) {
+        return 0;
+    }
+
+    const float   theta_scale       = et_powf(freq_base, et_fdiv(-2.0f, (float) n_dims));
+    const int32_t half_dims         = n_dims / 2;
+    const int     is_neox           = (mode & GGML_ROPE_TYPE_NEOX) != 0;
+    const int     is_imrope         = (mode == GGML_ROPE_TYPE_IMROPE);
+    const int     use_neox_rotation = is_neox || is_imrope;
+
+    // For IMROPE position cache invalidation: track all 4 channels
+    int32_t last_pos   = -1;
+    int32_t last_pos_h = -1;
+    int32_t last_pos_w = -1;
+    int32_t last_pos_e = -1;
+
+    for (int64_t wu = start_wu; wu < end_wu; ++wu) {
+        const int64_t h = wu % heads;
+        const int64_t s = (wu / heads) % seq_len;
+        const int64_t b = wu / (heads * seq_len);
+
+        if (is_imrope) {
+            // IMROPE: src1 layout is [p_t(0..S-1), p_h(0..S-1), p_w(0..S-1), p_e(0..S-1)]
+            const int32_t pt = src1_data[s] + rope_params->n_past;
+            const int32_t ph = src1_data[s + seq_len] + rope_params->n_past;
+            const int32_t pw = src1_data[s + seq_len * 2] + rope_params->n_past;
+            const int32_t pe = src1_data[s + seq_len * 3] + rope_params->n_past;
+
+            if (pt != last_pos || ph != last_pos_h || pw != last_pos_w || pe != last_pos_e) {
+                compute_imrope_cache(cos_cache, sin_cache, n_dims, theta_scale, pt, ph, pw, pe, rope_params->sections,
+                                     freq_factors, freq_scale, corr_dims, rope_params->ext_factor,
+                                     rope_params->attn_factor);
+                last_pos   = pt;
+                last_pos_h = ph;
+                last_pos_w = pw;
+                last_pos_e = pe;
+            }
+        } else {
+            const int32_t pos = src1_data[s] + rope_params->n_past;
+
+            if (pos != last_pos) {
+                compute_rope_cache(cos_cache, sin_cache, n_dims, theta_scale, pos, freq_factors, freq_scale, corr_dims,
+                                   rope_params->ext_factor, rope_params->attn_factor);
+                last_pos = pos;
+            }
+        }
+
+        const float * head_src =
+            (const float *) ((const char *) src0_data + b * src0->nb[3] + s * src0->nb[2] + h * src0->nb[1]);
+
+        float * head_dst = (float *) ((char *) dst_data + b * dst->nb[3] + s * dst->nb[2] + h * dst->nb[1]);
+
+        // Copy dimensions beyond n_dims unchanged
+        for (int64_t d = n_dims; d < head_dim; ++d) {
+            head_dst[d] = head_src[d];
+        }
+
+        if (use_neox_rotation) {
+            // NEOX/IMROPE: pairs at (i, i+half_dims)
+            uint64_t temp_mask;
+            __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+            __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+            for (int32_t dim_idx = 0; dim_idx < half_dims; dim_idx += 8) {
+                __asm__ volatile(
+                    "flw.ps f0, %[x0_src]       \n\t"
+                    "flw.ps f1, %[x1_src]       \n\t"
+                    "flw.ps f2, %[sin_cache]    \n\t"
+                    "flw.ps f3, %[cos_cache]    \n\t"
+                    "fmul.ps f4, f0, f3         \n\t"
+                    "fmul.ps f5, f0, f2         \n\t"
+                    "fnmsub.ps f4, f1, f2, f4   \n\t"
+                    "fmadd.ps f5, f1, f3, f5    \n\t"
+                    "fsw.ps f4, %[x0_dst]       \n\t"
+                    "fsw.ps f5, %[x1_dst]       \n\t"
+                    : [x0_dst] "=m"(*(float (*)[8]) & head_dst[dim_idx]), [x1_dst] "=m"(*(float (*)[8]) &
+                                                                                        head_dst[dim_idx + half_dims])
+                    : [x0_src] "m"(*(const float (*)[8]) & head_src[dim_idx]),
+                      [x1_src] "m"(*(const float (*)[8]) & head_src[dim_idx + half_dims]),
+                      [sin_cache] "m"(*(const float (*)[8]) & sin_cache[dim_idx]),
+                      [cos_cache] "m"(*(const float (*)[8]) & cos_cache[dim_idx])
+                    : "f0", "f1", "f2", "f3", "f4", "f5", "memory");
+            }
+
+            __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+        } else {
+            // Standard: adjacent pairs (2i, 2i+1)
+            for (int32_t pair_idx = 0; pair_idx < half_dims; ++pair_idx) {
+                const int32_t dim_in_head = pair_idx * 2;
+                const float   x0          = head_src[dim_in_head];
+                const float   x1          = head_src[dim_in_head + 1];
+
+                head_dst[dim_in_head]     = x0 * cos_cache[pair_idx] - x1 * sin_cache[pair_idx];
+                head_dst[dim_in_head + 1] = x0 * sin_cache[pair_idx] + x1 * cos_cache[pair_idx];
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/rwkv_wkv6_f32.c b/ggml/src/ggml-et/et-kernels/src/rwkv_wkv6_f32.c
new file mode 100644 (file)
index 0000000..4c00b1a
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/rwkv_wkv6_f32.c
@@ -0,0 +1,184 @@
+//******************************************************************************
+// RWKV WKV6 F32 Kernel
+//
+// Implements the RWKV-6 linear attention recurrence:
+//   dst = r @ (time_faaaa * (k @ v) + state)
+//   state = time_decay * state + (k @ v)
+//
+// For each head h, timestep t, row i:
+//   kv[j]       = v[j] * k[i]
+//   temp[j]     = kv[j] * tf[i] + state[i][j]
+//   dst[j]     += temp[j] * r[i]     (accumulated across all i)
+//   state[i][j] = state[i][j] * td[i] + kv[j]
+//
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_rwkv_wkv6_params {
+    float * k;         // src[0]: [S, H, T]  key
+    float * v;         // src[1]: [S, H, T]  value
+    float * r;         // src[2]: [S, H, T]  receptance
+    float * tf;        // src[3]: [S, H]     time_faaaa (per-head, not per-token)
+    float * td;        // src[4]: [S, H, T]  time_decay
+    float * state_in;  // src[5]: [S*S*H, n_seqs]  initial state
+    float * dst;       // [C, T + S*n_seqs]  output + state_out
+    int32_t C;         // total channels (S * H)
+    int32_t H;         // number of heads
+    int32_t S;         // head size
+    int32_t T;         // number of tokens
+    int32_t n_seqs;    // number of sequences
+};
+
+int entry_point(struct ggml_et_rwkv_wkv6_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    const float * k        = params->k;
+    const float * v        = params->v;
+    const float * r        = params->r;
+    const float * tf       = params->tf;
+    const float * td       = params->td;
+    const float * state_in = params->state_in;
+    float *       dst_data = params->dst;
+
+    const int32_t C      = params->C;
+    const int32_t H      = params->H;
+    const int32_t S      = params->S;
+    const int32_t T      = params->T;
+    const int32_t n_seqs = params->n_seqs;
+
+    if (!k || !v || !r || !tf || !td || !state_in || !dst_data) {
+        return -1;
+    }
+
+    const int32_t tps       = T / n_seqs;  // tokens per sequence
+    float *       state_out = dst_data + C * T;
+    float         zero      = 0.0f;
+
+    // Tile j by one cache line so each hart's dst/state writes never share
+    // a 64-B line with another hart's writes (the chip is non-coherent).
+    // Tiling on j (not i) is required for WKV6 because dst[j] is accumulated
+    // across i — splitting i across harts would race on dst writes.
+    // For S=64 this gives 4 tiles per head; for S<16 or odd S we fall back
+    // to one-hart-per-head (= the original parallelism).
+    const int32_t j_tile         = (S % 16 == 0) ? 16 : S;
+    const int32_t tiles_per_head = S / j_tile;
+    const int32_t total_units    = H * tiles_per_head;
+
+    // Parallelize across (head, j-tile) pairs.  The t loop stays inside this
+    // unit loop so the same hart owns the same column slice of state across
+    // all timesteps — required for the recurrence to read back its own
+    // writes without going through L2.
+    for (int32_t u = thread_id; u < total_units; u += num_threads) {
+        const int32_t h       = u / tiles_per_head;
+        const int32_t tile    = u % tiles_per_head;
+        const int32_t j_start = tile * j_tile;
+        const int32_t j_end   = j_start + j_tile;
+
+        const int32_t h_off = h * S;      // offset within C for this head
+        const int32_t s2d   = h * S * S;  // offset within state for this head
+
+        for (int32_t t = 0; t < T; t++) {
+            const int32_t seq       = t / tps;
+            const int32_t t_in_seq  = t % tps;
+            const int32_t seq_state = seq * S * C;
+
+            const float * s_prev;
+            float *       s_cur = state_out + seq_state + s2d;
+
+            if (t_in_seq == 0) {
+                s_prev = state_in + seq_state + s2d;
+            } else {
+                s_prev = s_cur;
+            }
+
+            const int32_t th = t * C + h_off;
+
+            // Pointers for this timestep/head
+            const float * k_ptr  = k + th;
+            const float * v_ptr  = v + th;
+            const float * r_ptr  = r + th;
+            const float * tf_ptr = tf + h_off;  // tf is per-head, no t offset
+            const float * td_ptr = td + th;
+
+            // Zero this hart's slice of dst: dst[th + j_start..th + j_end-1]
+            // WKV6 accumulates dst[j] across all i, so must start from zero
+            float * dst_row = dst_data + th;
+            for (int32_t j = j_start; j < j_end; j += 8) {
+                __asm__ volatile(
+                    "fbc.ps f10, %[z]\n"
+                    "fsw.ps f10, %[dst_vec]\n"
+                    : [dst_vec] "=m"(*(float (*)[8]) & dst_row[j])
+                    : [z] "m"(zero)
+                    : "f10");
+            }
+
+            for (int32_t i = 0; i < S; i++) {
+                const float * sp_row = s_prev + i * S;  // state_prev row i
+                float *       sc_row = s_cur + i * S;   // state_cur  row i
+
+                float k_val  = k_ptr[i];
+                float r_val  = r_ptr[i];
+                float tf_val = tf_ptr[i];
+                float td_val = td_ptr[i];
+
+                // Broadcast k[i], r[i], tf[i], td[i] to vector registers
+                __asm__ volatile(
+                    "fbc.ps f20, %[kv]\n"   // f20 = k[i] broadcast
+                    "fbc.ps f21, %[rv]\n"   // f21 = r[i] broadcast
+                    "fbc.ps f22, %[tfv]\n"  // f22 = tf[i] broadcast
+                    "fbc.ps f23, %[tdv]\n"  // f23 = td[i] broadcast
+                    :
+                    : [kv] "m"(k_val), [rv] "m"(r_val), [tfv] "m"(tf_val), [tdv] "m"(td_val)
+                    : "f20", "f21", "f22", "f23");
+
+                for (int32_t j = j_start; j < j_end; j += 8) {
+                    __asm__ volatile(
+                        // Load v[j], state_prev[i][j], dst[j]
+                        "flw.ps f10, %[v_vec]\n"  // v[j..j+7]
+                        "flw.ps f11, %[s_vec]\n"  // state_prev[i][j..j+7]
+                        "flw.ps f12, %[d_vec]\n"  // dst[j..j+7] (accumulated)
+
+                        // kv = v * k_broadcast
+                        "fmul.ps f13, f10, f20\n"  // kv = v * k
+
+                        // temp = kv * tf_broadcast + state_prev
+                        "fmadd.ps f14, f13, f22, f11\n"  // temp = kv * tf + state
+
+                        // dst[j] += temp * r_broadcast
+                        "fmadd.ps f12, f14, f21, f12\n"  // dst += temp * r
+                        "fsw.ps f12, %[d_out]\n"         // store updated dst
+
+                        // state_cur[i][j] = state_prev * td_broadcast + kv
+                        "fmadd.ps f11, f11, f23, f13\n"  // state = state * td + kv
+                        "fsw.ps f11, %[s_out]\n"         // store new state
+
+                        : [d_out] "=m"(*(float (*)[8]) & dst_row[j]), [s_out] "=m"(*(float (*)[8]) & sc_row[j])
+                        : [v_vec] "m"(*(const float (*)[8]) & v_ptr[j]), [s_vec] "m"(*(const float (*)[8]) & sp_row[j]),
+                          [d_vec] "m"(*(const float (*)[8]) & dst_row[j])
+                        : "f10", "f11", "f12", "f13", "f14");
+                }
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/rwkv_wkv7_f32.c b/ggml/src/ggml-et/et-kernels/src/rwkv_wkv7_f32.c
new file mode 100644 (file)
index 0000000..08e4ba2
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/rwkv_wkv7_f32.c
@@ -0,0 +1,272 @@
+//******************************************************************************
+// RWKV WKV7 F32 Kernel
+//
+// Implements the RWKV-7 linear attention recurrence:
+//   For each head h, timestep t, row i:
+//     sa       = dot(a, state[i])
+//     state[i] = state[i] * w + v[i]*k + sa * b
+//     output[i]= dot(state[i], r)
+//
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_rwkv_wkv7_params {
+    float * r;         // [S, H, T]  receptance
+    float * w;         // [S, H, T]  decay
+    float * k;         // [S, H, T]  key
+    float * v;         // [S, H, T]  value
+    float * a;         // [S, H, T]  bonus gate
+    float * b;         // [S, H, T]  bonus key
+    float * state_in;  // [S*S*H, n_seqs]  initial state
+    float * dst;       // [C, T + S*n_seqs]  output + state_out
+    int32_t C;         // total channels (S * H)
+    int32_t H;         // number of heads
+    int32_t S;         // head size
+    int32_t T;         // number of tokens
+    int32_t n_seqs;    // number of sequences
+};
+
+// Horizontal sum of 8-wide vector register f10 -> scalar float
+static inline float hsum_f10(void) {
+    float result;
+    __asm__ __volatile__(
+        "fswizz.ps f1, f10, 0xB1 \n\t"
+        "fadd.ps   f2, f10, f1, rne \n\t"
+        "fswizz.ps f3, f2, 0x4E \n\t"
+        "fadd.ps   f4, f2, f3, rne \n\t"
+        "fmvz.x.ps t0, f4, 4 \n\t"
+        "fbcx.ps   f5, t0 \n\t"
+        "fadd.ps   %[vout], f4, f5, rne \n\t"
+        : [vout] "=f"(result)::"t0", "f1", "f2", "f3", "f4", "f5");
+    return result;
+}
+
+int entry_point(struct ggml_et_rwkv_wkv7_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    const float * r        = params->r;
+    const float * w        = params->w;
+    const float * k        = params->k;
+    const float * v        = params->v;
+    const float * a        = params->a;
+    const float * b        = params->b;
+    const float * state_in = params->state_in;
+    float *       dst_data = params->dst;
+
+    const int32_t C      = params->C;
+    const int32_t H      = params->H;
+    const int32_t S      = params->S;
+    const int32_t T      = params->T;
+    const int32_t n_seqs = params->n_seqs;
+
+    if (!r || !w || !k || !v || !a || !b || !state_in || !dst_data) {
+        return -1;
+    }
+
+    const int32_t tps       = T / n_seqs;  // tokens per sequence
+    float *       state_out = dst_data + C * T;
+
+    // Fix #2: hoist w[0..S-1] across the i loop.  In the inner j-loop of pass
+    // 2, w/k/b/r are loop-invariant w.r.t. i but were being reloaded for every
+    // i value (16 times redundantly after Fix #1).  Pinning all four arrays
+    // would need 32 vector regs (won't fit), so we hoist just w — it's used
+    // in the critical fmadd chain and lives cleanly in f24-f31, which the
+    // existing kernel never touches.  Saves ~20% of pass-2 load issues.
+    //
+    // GCC local register variables: declared as `float` but the underlying
+    // f-reg holds the wide vector loaded by flw.ps.  GCC reserves f24-f31 for
+    // these variables for the whole function and never generates code that
+    // touches them on its own, so the upper 7 lanes survive between asm
+    // blocks.  Only used when S == 64 (the RWKV-7 case); other head sizes
+    // fall through to the original unhoisted path.
+    register float w_h0 __asm__("f24");
+    register float w_h1 __asm__("f25");
+    register float w_h2 __asm__("f26");
+    register float w_h3 __asm__("f27");
+    register float w_h4 __asm__("f28");
+    register float w_h5 __asm__("f29");
+    register float w_h6 __asm__("f30");
+    register float w_h7 __asm__("f31");
+    const int      wkv7_fast = (S == 64);
+
+    // Tile i by one cache line so each hart's output writes never share a
+    // 64-B line with another hart's writes (the chip is non-coherent).
+    // For S=64 this gives 4 tiles per head; for S<16 or odd S we fall back
+    // to one-hart-per-head (= the original parallelism).
+    const int32_t i_tile         = (S % 16 == 0) ? 16 : S;
+    const int32_t tiles_per_head = S / i_tile;
+    const int32_t total_units    = H * tiles_per_head;
+
+    // Parallelize across (head, i-tile) pairs.  The t loop stays inside this
+    // unit loop so the same hart owns the same state rows across all
+    // timesteps — required for the recurrence to read back its own writes
+    // without going through L2.
+    for (int32_t u = thread_id; u < total_units; u += num_threads) {
+        const int32_t h       = u / tiles_per_head;
+        const int32_t tile    = u % tiles_per_head;
+        const int32_t i_start = tile * i_tile;
+        const int32_t i_end   = i_start + i_tile;
+
+        const int32_t h_off = h * S;      // offset within C for this head
+        const int32_t s2d   = h * S * S;  // offset within state for this head
+
+        for (int32_t t = 0; t < T; t++) {
+            const int32_t seq       = t / tps;
+            const int32_t t_in_seq  = t % tps;
+            const int32_t seq_state = seq * S * C;  // state offset for this sequence
+
+            const float * s_prev;
+            float *       s_cur = state_out + seq_state + s2d;
+
+            if (t_in_seq == 0) {
+                s_prev = state_in + seq_state + s2d;
+            } else {
+                s_prev = s_cur;
+            }
+
+            // Pointers for this timestep/head
+            const int32_t th    = t * C + h_off;
+            const float * r_ptr = r + th;
+            const float * w_ptr = w + th;
+            const float * k_ptr = k + th;
+            const float * v_ptr = v + th;
+            const float * a_ptr = a + th;
+            const float * b_ptr = b + th;
+
+            // Hoist w[0..63] into f24-f31 once per (h, t).  These values are
+            // invariant across the i loop below, so the inner j-unroll can
+            // reference them by register name and skip the per-i reload.
+            if (wkv7_fast) {
+                __asm__ volatile(
+                    "flw.ps f24,   0(%[wp])\n"
+                    "flw.ps f25,  32(%[wp])\n"
+                    "flw.ps f26,  64(%[wp])\n"
+                    "flw.ps f27,  96(%[wp])\n"
+                    "flw.ps f28, 128(%[wp])\n"
+                    "flw.ps f29, 160(%[wp])\n"
+                    "flw.ps f30, 192(%[wp])\n"
+                    "flw.ps f31, 224(%[wp])\n"
+                    : "=f"(w_h0), "=f"(w_h1), "=f"(w_h2), "=f"(w_h3), "=f"(w_h4), "=f"(w_h5), "=f"(w_h6), "=f"(w_h7)
+                    : [wp] "r"(w_ptr));
+            }
+
+            for (int32_t i = i_start; i < i_end; i++) {
+                const float * sp_row = s_prev + i * S;  // state_prev row i
+                float *       sc_row = s_cur + i * S;   // state_cur  row i
+
+                // ----------------------------------------------------------
+                // Step 1: sa = dot(a, state_prev[i])
+                // Accumulate in f10
+                // ----------------------------------------------------------
+                float zero = 0.0f;
+                __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+                for (int32_t j = 0; j < S; j += 8) {
+                    __asm__ volatile(
+                        "flw.ps f11, %[a_vec]\n"
+                        "flw.ps f12, %[s_vec]\n"
+                        "fmadd.ps f10, f11, f12, f10\n"
+                        :
+                        : [a_vec] "m"(*(const float (*)[8]) & a_ptr[j]), [s_vec] "m"(*(const float (*)[8]) & sp_row[j])
+                        : "f10", "f11", "f12");
+                }
+
+                float sa = hsum_f10();
+
+                // ----------------------------------------------------------
+                // Step 2: state update + result accumulation
+                //   kv       = v[i] * k[j]
+                //   state[j] = state[j] * w[j] + kv + sa * b[j]
+                //   result  += state[j] * r[j]
+                // ----------------------------------------------------------
+                float v_val = v_ptr[i];
+
+                // Broadcast v_val and sa, zero result accumulator (f10)
+                __asm__ volatile(
+                    "fbc.ps f20, %[vv]\n"
+                    "fbc.ps f21, %[sv]\n"
+                    "fbc.ps f10, %[z]\n"
+                    :
+                    : [vv] "m"(v_val), [sv] "m"(sa), [z] "m"(zero)
+                    : "f10", "f20", "f21");
+
+                if (wkv7_fast) {
+// Fast path: 8 chunks unrolled, w hoisted to f24-f31.
+// Saves one flw per chunk vs the original loop.
+#define WKV7_PASS2_CHUNK(j_off, w_var)                                                                           \
+    __asm__ volatile(                                                                                            \
+        "flw.ps f11, %[s_vec]\n"                                                                                 \
+        "flw.ps f13, %[k_vec]\n"                                                                                 \
+        "flw.ps f14, %[b_vec]\n"                                                                                 \
+        "flw.ps f15, %[r_vec]\n"                                                                                 \
+        "fmul.ps f16, f20, f13\n"                                                                                \
+        "fmadd.ps f11, f11, %[w_h], f16\n"                                                                       \
+        "fmadd.ps f11, f21, f14, f11\n"                                                                          \
+        "fsw.ps f11, %[sc_vec]\n"                                                                                \
+        "fmadd.ps f10, f11, f15, f10\n"                                                                          \
+        : [sc_vec] "=m"(*(float (*)[8]) & sc_row[j_off])                                                         \
+        : [s_vec] "m"(*(const float (*)[8]) & sp_row[j_off]), [k_vec] "m"(*(const float (*)[8]) & k_ptr[j_off]), \
+          [b_vec] "m"(*(const float (*)[8]) & b_ptr[j_off]), [r_vec] "m"(*(const float (*)[8]) & r_ptr[j_off]),  \
+          [w_h] "f"(w_var)                                                                                       \
+        : "f10", "f11", "f13", "f14", "f15", "f16")
+
+                    WKV7_PASS2_CHUNK(0, w_h0);
+                    WKV7_PASS2_CHUNK(8, w_h1);
+                    WKV7_PASS2_CHUNK(16, w_h2);
+                    WKV7_PASS2_CHUNK(24, w_h3);
+                    WKV7_PASS2_CHUNK(32, w_h4);
+                    WKV7_PASS2_CHUNK(40, w_h5);
+                    WKV7_PASS2_CHUNK(48, w_h6);
+                    WKV7_PASS2_CHUNK(56, w_h7);
+
+#undef WKV7_PASS2_CHUNK
+                } else {
+                    for (int32_t j = 0; j < S; j += 8) {
+                        __asm__ volatile(
+                            "flw.ps f11, %[s_vec]\n"         // state_prev[j..j+7]
+                            "flw.ps f12, %[w_vec]\n"         // w[j..j+7]
+                            "flw.ps f13, %[k_vec]\n"         // k[j..j+7]
+                            "flw.ps f14, %[b_vec]\n"         // b[j..j+7]
+                            "flw.ps f15, %[r_vec]\n"         // r[j..j+7]
+                            "fmul.ps f16, f20, f13\n"        // kv = v_broadcast * k
+                            "fmadd.ps f11, f11, f12, f16\n"  // state*w + kv
+                            "fmadd.ps f11, f21, f14, f11\n"  // + sa*b
+                            "fsw.ps f11, %[sc_vec]\n"        // store new state
+                            "fmadd.ps f10, f11, f15, f10\n"  // result += new_state * r
+
+                            : [sc_vec] "=m"(*(float (*)[8]) & sc_row[j])
+                            : [s_vec] "m"(*(const float (*)[8]) & sp_row[j]),
+                              [w_vec] "m"(*(const float (*)[8]) & w_ptr[j]),
+                              [k_vec] "m"(*(const float (*)[8]) & k_ptr[j]),
+                              [b_vec] "m"(*(const float (*)[8]) & b_ptr[j]),
+                              [r_vec] "m"(*(const float (*)[8]) & r_ptr[j])
+                            : "f10", "f11", "f12", "f13", "f14", "f15", "f16");
+                    }
+                }
+
+                dst_data[th + i] = hsum_f10();
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/scale_f32.c b/ggml/src/ggml-et/et-kernels/src/scale_f32.c
new file mode 100644 (file)
index 0000000..ad0c649
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/scale_f32.c
@@ -0,0 +1,94 @@
+//******************************************************************************
+// Scale F32 Kernel
+// dst[i] = src0[i] * scale + bias
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_scale_params {
+    struct ggml_tensor src0;   // F32 input tensor
+    struct ggml_tensor dst;    // F32 output tensor
+    float              scale;  // Scale factor
+    float              bias;   // Bias (additive offset)
+};
+
+int entry_point(struct ggml_et_scale_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+
+    float scale = params->scale;
+    float bias  = params->bias;
+
+    // Total elements across all dimensions
+    const int64_t total_elements = src0->ne[0] * src0->ne[1] * src0->ne[2] * src0->ne[3];
+
+    // Cache line = 64 bytes = 16 floats, but vector width = 8 floats
+    // Parallelize at cache line granularity (16 floats)
+    const int64_t elements_per_cacheline = 16;
+    const int64_t total_cachelines       = (total_elements + elements_per_cacheline - 1) / elements_per_cacheline;
+
+    int64_t cachelines_per_thread = (total_cachelines + num_threads - 1) / num_threads;
+    int64_t start_cacheline       = thread_id * cachelines_per_thread;
+    int64_t end_cacheline         = start_cacheline + cachelines_per_thread;
+
+    if (end_cacheline > total_cachelines) {
+        end_cacheline = total_cachelines;
+    }
+
+    if (start_cacheline >= total_cachelines) {
+        return 0;
+    }
+
+    int64_t start_elem = start_cacheline * elements_per_cacheline;
+    int64_t end_elem   = end_cacheline * elements_per_cacheline;
+    if (end_elem > total_elements) {
+        end_elem = total_elements;
+    }
+
+    unsigned long temp_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(temp_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+    __asm__ volatile("fbc.ps f20, %[scale_ptr]\n" : : [scale_ptr] "m"(scale) : "f20");
+    __asm__ volatile("fbc.ps f21, %[bias_ptr]\n" : : [bias_ptr] "m"(bias) : "f21");
+
+    for (int64_t i = start_elem; i < end_elem; i += 8) {
+        __asm__ volatile(
+            "flw.ps f10, %[src]\n"
+            "fmadd.ps f10, f10, f20, f21\n"  // dst = src*scale + bias
+            "fsw.ps f10, %[dst_out]\n"
+            : [dst_out] "=m"(*(float (*)[8]) & dst_data[i])
+            : [src] "m"(*(const float (*)[8]) & src0_data[i])
+            : "f10", "f20", "f21");
+    }
+    __asm__ volatile("mova.m.x %0" ::"r"(temp_mask));
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/set_f32.c b/ggml/src/ggml-et/et-kernels/src/set_f32.c
new file mode 100644 (file)
index 0000000..aea2b61
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/set_f32.c
@@ -0,0 +1,101 @@
+//******************************************************************************
+// SET F32 Kernel
+// Minimal ET implementation for inplace F32 SET into a contiguous destination
+// using a contiguous F32 source view and explicit destination view strides.
+//
+// Supported shape family:
+// - dst/base is contiguous F32
+// - src1 is contiguous F32
+// - src1.ne[0] is cacheline-aligned (multiple of 16 floats)
+// - destination view strides/offset are cacheline-aligned
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_set_params {
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+    int32_t            nb1;
+    int32_t            nb2;
+    int32_t            nb3;
+    int32_t            offset;
+};
+
+static inline void copy_row_aligned(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps f11, %[src_vec]\n"
+            "fsw.ps f11, %[dst_vec]\n"
+            : [dst_vec] "=m"(*(float (*)[8]) & dst[i])
+            : [src_vec] "m"(*(const float (*)[8]) & src[i])
+            : "f11");
+    }
+}
+
+int entry_point(struct ggml_et_set_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float * src1_data = (const float *) src1->data;
+    float *       dst_data  = (float *) dst->data;
+    if (!src1_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne10 = src1->ne[0];
+    const int64_t ne11 = src1->ne[1];
+    const int64_t ne12 = src1->ne[2];
+    const int64_t ne13 = src1->ne[3];
+
+    if (src1->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float) || ne10 % 16 != 0) {
+        return -1;
+    }
+
+    const int64_t nb11 = src1->nb[1];
+    const int64_t nb12 = src1->nb[2];
+    const int64_t nb13 = src1->nb[3];
+
+    const int64_t dnb1   = params->nb1;
+    const int64_t dnb2   = params->nb2;
+    const int64_t dnb3   = params->nb3;
+    const int64_t offset = params->offset;
+
+    const int64_t total_rows = ne11 * ne12 * ne13;
+
+    for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+        const int64_t i1 = row % ne11;
+        const int64_t i2 = (row / ne11) % ne12;
+        const int64_t i3 = row / (ne11 * ne12);
+
+        const float * src_row = (const float *) ((const char *) src1_data + i1 * nb11 + i2 * nb12 + i3 * nb13);
+        float *       dst_row = (float *) ((char *) dst_data + offset + i1 * dnb1 + i2 * dnb2 + i3 * dnb3);
+
+        copy_row_aligned(dst_row, src_row, (int32_t) ne10);
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/set_rows_f32.c b/ggml/src/ggml-et/et-kernels/src/set_rows_f32.c
new file mode 100644 (file)
index 0000000..16e1758
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/set_rows_f32.c
@@ -0,0 +1,394 @@
+//******************************************************************************
+// Bare Metal SET_ROWS F32 Kernel
+// Writes source data rows to specific indices in destination tensor
+//
+// Algorithm:
+// 1. Read row indices from src1 (int64 tensor)
+// 2. For each source row, write it to destination at the specified index
+// 3. Handle type conversion: F32 source -> F32/F16 destination
+// 4. Support multi-dimensional tensor operations
+//
+// Operation: dst[indices[i]] = src[i] for i = 0..num_source_rows
+// This is the inverse of GET_ROWS operation
+//
+// As ET is not a cache coherent processor yet SET_ROWS often are setting
+// small mount of large rows (KV cache). There's several strategies to
+// optimize this operation, including cacheline-based parallelization.
+//
+// - distribute work at cacheline granularity
+// - if previous does not work, find the LCM of cacheline size
+//
+// Features supported:
+// - F32 source data (always F32 input)
+// - F32 and F16 destination data (with transcoding)
+// - Int64 row indices (vs Int32 in GET_ROWS)
+// - Multi-dimensional tensor support
+// - Sequential source reads, scattered destination writes
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#define CACHE_LINE_SIZE_BYTES 64
+#define CACHE_LINE_F32_ELEMS  16  // 64 / 4
+#define CACHE_LINE_F16_ELEMS  32  // 64 / 2
+
+static int64_t gcd64(int64_t a, int64_t b) {
+    while (b) {
+        int64_t t = b;
+        b         = a % b;
+        a         = t;
+    }
+    return a;
+}
+
+struct ggml_et_set_rows_params {
+    struct ggml_tensor src0;  // F32 source data tensor
+    struct ggml_tensor src1;  // I64 row indices tensor
+    struct ggml_tensor dst;   // F32/F16 destination tensor
+};
+
+// Copy exactly one cache line (64 bytes = 16 F32 elements) using wide loads/stores
+static void copy_cache_aligned_f32(float * dst, const float * src) {
+    __asm__ volatile(
+        "flq2 f0, 0(%[src]) \n\t"   // Load 32 bytes
+        "flq2 f1, 32(%[src]) \n\t"  // Load next 32 bytes
+        "fsq2 f0, 0(%[dst]) \n\t"   // Store 32 bytes
+        "fsq2 f1, 32(%[dst]) \n\t"  // Store next 32 bytes
+        :
+        : [src] "r"(src), [dst] "r"(dst)
+        : "f0", "f1", "memory");
+}
+
+// Convert and copy one dst cache line worth of F32->F16 (32 elements src -> 64 bytes dst)
+static void copy_cache_aligned_f16(uint16_t * dst, const float * src) {
+    unsigned long mask_temp;
+
+    // Build offset vector for consecutive 16-bit stores: [0, 2, 4, 6, 8, 10, 12, 14]
+    float      offset_vec_storage[8];
+    uint32_t * offsets = (uint32_t *) offset_vec_storage;
+    for (int j = 0; j < 8; j++) {
+        offsets[j] = j * 2;
+    }
+
+    __asm__ volatile(
+        "mova.x.m  %[mask_temp]         \n\t"
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+        "flw.ps    f1, 0(%[offsets])    \n\t"
+        : [mask_temp] "=&r"(mask_temp)
+        : [offsets] "r"(offset_vec_storage)
+        : "f1");
+
+    // 4 iterations of 8 elements = 32 F16 elements = 64 bytes = 1 cache line
+    for (int i = 0; i < 32; i += 8) {
+        __asm__ volatile(
+            "flw.ps    f2, 0(%[src_ptr])    \n\t"
+            "fcvt.f16.ps f3, f2             \n\t"
+            "fsch.ps   f3, f1(%[dst_ptr])   \n\t"
+            :
+            : [src_ptr] "r"(src + i), [dst_ptr] "r"(dst + i)
+            : "f2", "f3", "memory");
+    }
+
+    __asm__ volatile("mova.m.x  %[mask_temp]         \n\t" : : [mask_temp] "r"(mask_temp));
+}
+
+static inline size_t tensor_bytes(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+int entry_point(struct ggml_et_set_rows_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;  // Source data tensor (F32)
+    struct ggml_tensor * src1 = &params->src1;  // Row indices tensor (I64)
+    struct ggml_tensor * dst  = &params->dst;   // Destination tensor (F32/F16)
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_I64) {
+        return -1;  // Invalid source types
+    }
+
+    if (dst->type != GGML_TYPE_F32 && dst->type != GGML_TYPE_F16) {
+        return -1;  // Unsupported destination type
+    }
+
+    float *   src0_data = (float *) src0->data;
+    int64_t * src1_data = (int64_t *) src1->data;
+    void *    dst_data  = dst->data;
+
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    const int64_t ne00 = src0->ne[0];  // Source columns (row width)
+    const int64_t ne01 = src0->ne[1];  // Source rows (number of rows to write)
+    const int64_t ne02 = src0->ne[2];  // Source batch dimension
+    const int64_t ne03 = src0->ne[3];  // Source outer batch dimension
+
+    const int64_t nb01 = src0->nb[1];
+    const int64_t nb02 = src0->nb[2];
+    const int64_t nb03 = src0->nb[3];
+
+    const int64_t ne10 = src1->ne[0];  // Number of indices in dimension 0
+    const int64_t ne11 = src1->ne[1];  // Number of indices in dimension 1
+    const int64_t ne12 = src1->ne[2];  // Batch dimension for indices
+
+    const int64_t nb10 = src1->nb[0];
+    const int64_t nb11 = src1->nb[1];
+    const int64_t nb12 = src1->nb[2];
+
+    const int64_t ne_dst1 = dst->ne[1];  // Number of rows in destination (for bounds checking)
+
+    const int64_t nb1 = dst->nb[1];
+    const int64_t nb2 = dst->nb[2];
+    const int64_t nb3 = dst->nb[3];
+
+    // Validate that number of indices matches number of source rows
+    if (ne10 != ne01) {
+        return -1;  // Number of indices must match number of source rows
+    }
+#ifdef ET_UBERKERNEL
+    evict_region_past_l2(params->src0.data, tensor_bytes(&params->src0));
+    evict_region_past_l2(params->src1.data, tensor_bytes(&params->src1));
+    FENCE;
+    et_barrier(ET_BARRIER_GLOBAL);
+#endif
+    const int64_t total_rows = ne01 * ne02 * ne03;
+
+    // Determine cache-line element count based on destination type
+    const int64_t dst_cl_elems = (dst->type == GGML_TYPE_F16) ? CACHE_LINE_F16_ELEMS : CACHE_LINE_F32_ELEMS;
+
+    // Check if rows are cache-line aligned in the destination
+    const bool row_cache_aligned = (ne00 >= dst_cl_elems) && (ne00 % dst_cl_elems == 0);
+
+    if (row_cache_aligned) {
+        // Cache-aligned path: distribute dst cache lines across threads
+        // Each thread owns complete cache lines -> no coherence conflicts
+        const int64_t cls_per_row    = ne00 / dst_cl_elems;
+        const int64_t total_cls      = total_rows * cls_per_row;
+        const int64_t cls_per_thread = (total_cls + num_threads - 1) / num_threads;
+        const int64_t my_start       = thread_id * cls_per_thread;
+        int64_t       my_end         = my_start + cls_per_thread;
+        if (my_end > total_cls) {
+            my_end = total_cls;
+        }
+        if (my_start >= total_cls) {
+            return 0;
+        }
+
+        for (int64_t cl = my_start; cl < my_end; cl++) {
+            // Map flat cache-line index -> (row, offset within row)
+            const int64_t row_flat  = cl / cls_per_row;
+            const int64_t cl_in_row = cl % cls_per_row;
+
+            // Decompose flat row -> (i03, i02, i01)
+            const int64_t i01 = row_flat % ne01;
+            const int64_t tmp = row_flat / ne01;
+            const int64_t i02 = tmp % ne02;
+            const int64_t i03 = tmp / ne02;
+
+            // Look up destination row index
+            const int64_t i12               = i03 % ne12;
+            const int64_t i11               = i02 % ne11;
+            const int64_t i10               = i01;
+            const int64_t index_byte_offset = i10 * nb10 + i11 * nb11 + i12 * nb12;
+            const int64_t dst_row_index     = *(int64_t *) ((char *) src1_data + index_byte_offset);
+
+            if (dst_row_index < 0 || dst_row_index >= ne_dst1) {
+                return -1;
+            }
+
+            // Source pointer: row base + cache-line offset (always F32 source)
+            const int64_t elem_offset = cl_in_row * dst_cl_elems;
+            const float * src_ptr =
+                (const float *) ((char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03) + elem_offset;
+
+            // Destination pointer: scattered row base + cache-line offset
+            char * dst_row_base = (char *) dst_data + dst_row_index * nb1 + i02 * nb2 + i03 * nb3;
+
+            if (dst->type == GGML_TYPE_F32) {
+                float * dst_ptr = (float *) dst_row_base + elem_offset;
+                copy_cache_aligned_f32(dst_ptr, src_ptr);
+            } else {
+                uint16_t * dst_ptr = (uint16_t *) dst_row_base + elem_offset;
+                copy_cache_aligned_f16(dst_ptr, src_ptr);
+            }
+        }
+    } else if (nb1 % CACHE_LINE_SIZE_BYTES == 0) {
+        // LCM-aligned path: destination row stride is cache-line-aligned, so
+        // scattered rows never share a cache line even though ne00 doesn't
+        // fill complete cache lines.  Group rows via lcm(ne00, dst_cl_elems)
+        // and distribute cache lines across threads — each thread exclusively
+        // owns its cache lines, so normal stores are safe (no atomics needed).
+        const int64_t g              = gcd64(ne00, dst_cl_elems);
+        const int64_t rows_per_group = dst_cl_elems / g;  // lcm / ne00
+        const int64_t cls_per_group  = ne00 / g;          // lcm / dst_cl_elems
+
+        const int64_t total_groups   = (total_rows + rows_per_group - 1) / rows_per_group;
+        const int64_t total_cls      = total_groups * cls_per_group;
+        const int64_t cls_per_thread = (total_cls + num_threads - 1) / num_threads;
+        const int64_t my_start       = thread_id * cls_per_thread;
+        int64_t       my_end         = my_start + cls_per_thread;
+        if (my_end > total_cls) {
+            my_end = total_cls;
+        }
+        if (my_start >= total_cls) {
+            return 0;
+        }
+
+#ifdef BUILD_FOR_UBERKERNEL
+    et_barrier(ET_BARRIER_GLOBAL);
+    // evict_region_past_l2(src0_data, tensor_bytes(src0));
+    // evict_region_past_l2(src1_data, tensor_bytes(src1));
+    // // et_barrier(ET_BARRIER_GLOBAL);
+    // FENCE;
+#endif
+
+
+        for (int64_t cl = my_start; cl < my_end; cl++) {
+            const int64_t group_idx   = cl / cls_per_group;
+            const int64_t cl_in_group = cl % cls_per_group;
+
+            // Element range [elem_start, elem_end) within the flattened group
+            const int64_t elem_start = cl_in_group * dst_cl_elems;
+            const int64_t elem_end   = elem_start + dst_cl_elems;
+
+            // Which row(s) inside this group does the cache line touch?
+            const int64_t r_first = elem_start / ne00;
+            const int64_t r_last  = (elem_end - 1) / ne00;
+
+            for (int64_t r = r_first; r <= r_last; r++) {
+                const int64_t row_flat = group_idx * rows_per_group + r;
+                if (row_flat >= total_rows) {
+                    break;
+                }
+
+                // Column range within this row
+                int64_t col_begin = (r == r_first) ? (elem_start - r * ne00) : 0;
+                int64_t col_end   = (r == r_last) ? (elem_end - r * ne00) : ne00;
+                if (col_end > ne00) {
+                    col_end = ne00;
+                }
+
+                // Decompose flat row -> (i03, i02, i01)
+                const int64_t i01 = row_flat % ne01;
+                const int64_t tmp = row_flat / ne01;
+                const int64_t i02 = tmp % ne02;
+                const int64_t i03 = tmp / ne02;
+
+                // Look up destination row index
+                const int64_t i12               = i03 % ne12;
+                const int64_t i11               = i02 % ne11;
+                const int64_t i10               = i01;
+                const int64_t index_byte_offset = i10 * nb10 + i11 * nb11 + i12 * nb12;
+                const int64_t dst_row_index     = *(int64_t *) ((char *) src1_data + index_byte_offset);
+
+                if (dst_row_index < 0 || dst_row_index >= ne_dst1) {
+                    return -1;
+                }
+
+                const float * src_row = (const float *) ((char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03);
+                char *        dst_row_base = (char *) dst_data + dst_row_index * nb1 + i02 * nb2 + i03 * nb3;
+
+                // nb1 is cache-line-aligned, so dst_row_base is too.
+                // Use aligned copy when the column range fills a complete
+                // cache line at a cache-line-aligned offset within the row.
+                const bool full_cl = (col_begin % dst_cl_elems == 0) && (col_end - col_begin == dst_cl_elems);
+
+                if (dst->type == GGML_TYPE_F32) {
+                    float * dp = (float *) dst_row_base;
+                    if (full_cl) {
+                        copy_cache_aligned_f32(dp + col_begin, src_row + col_begin);
+                    } else {
+                        for (int64_t i = col_begin; i < col_end; i++) {
+                            dp[i] = src_row[i];
+                        }
+                    }
+                } else {
+                    uint16_t * dp = (uint16_t *) dst_row_base;
+                    if (full_cl) {
+                        copy_cache_aligned_f16(dp + col_begin, src_row + col_begin);
+                    } else {
+                        for (int64_t i = col_begin; i < col_end; i++) {
+                            dp[i] = fp32_to_fp16(src_row[i]);
+                        }
+                    }
+                }
+            }
+        }
+
+#ifdef BUILD_FOR_UBERKERNEL
+    et_barrier(ET_BARRIER_GLOBAL);
+    // evict_region_past_l2(src0_data, tensor_bytes(src0));
+    // evict_region_past_l2(src1_data, tensor_bytes(src1));
+    // // et_barrier(ET_BARRIER_GLOBAL);
+    // FENCE;
+#endif
+
+
+    } else {
+        // Fallback: nb1 not cache-line-aligned, so scattered destination rows
+        // may share a cache line.  Use atomic global stores to bypass L1D.
+        for (int64_t row_flat = thread_id; row_flat < total_rows; row_flat += num_threads) {
+            const int64_t i01 = row_flat % ne01;
+            const int64_t tmp = row_flat / ne01;
+            const int64_t i02 = tmp % ne02;
+            const int64_t i03 = tmp / ne02;
+
+            // Look up destination row index
+            const int64_t i12               = i03 % ne12;
+            const int64_t i11               = i02 % ne11;
+            const int64_t i10               = i01;
+            const int64_t index_byte_offset = i10 * nb10 + i11 * nb11 + i12 * nb12;
+            const int64_t dst_row_index     = *(int64_t *) ((char *) src1_data + index_byte_offset);
+
+            if (dst_row_index < 0 || dst_row_index >= ne_dst1) {
+                return -1;
+            }
+
+            const float * src_row      = (const float *) ((char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03);
+            char *        dst_row_base = (char *) dst_data + dst_row_index * nb1 + i02 * nb2 + i03 * nb3;
+
+            if (dst->type == GGML_TYPE_F32) {
+                volatile float * dst_row = (volatile float *) dst_row_base;
+                for (int64_t i = 0; i < ne00; i++) {
+                    atomic_store_f32(dst_row + i, src_row[i]);
+                }
+            } else {
+                volatile uint16_t * dst_row = (volatile uint16_t *) dst_row_base;
+                for (int64_t i = 0; i < ne00; i++) {
+                    atomic_store_f16(dst_row + i, fp32_to_fp16(src_row[i]));
+                }
+            }
+        }
+    }
+
+#ifdef BUILD_FOR_UBERKERNEL
+    et_barrier(ET_BARRIER_GLOBAL);
+    // evict_region_past_l2(src0_data, tensor_bytes(src0));
+    // evict_region_past_l2(src1_data, tensor_bytes(src1));
+    // // et_barrier(ET_BARRIER_GLOBAL);
+    // FENCE;
+#endif
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/softmax_f32.c b/ggml/src/ggml-et/et-kernels/src/softmax_f32.c
new file mode 100644 (file)
index 0000000..5b322db
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/softmax_f32.c
@@ -0,0 +1,698 @@
+//******************************************************************************
+// Bare Metal Softmax F32 Kernel
+// Softmax function: y[i] = exp(x[i] - max) / sum(exp(x[j] - max))
+//
+// Algorithm:
+// 1. Apply scaling: x' = x * scale
+// 2. Add mask/bias if present: x' = x' + mask * slope (ALiBi support)
+// 3. Find max value for numerical stability: max = max(x')
+// 4. Compute exponentials: exp_vals[i] = exp(x'[i] - max)
+// 5. Compute sum: sum = sum(exp_vals)
+// 6. Normalize: y[i] = exp_vals[i] / sum
+//
+// Features supported:
+// - Temperature scaling via scale parameter
+// - Attention masking (transformer masks)
+// - ALiBi (Attention with Linear Biases) positional encoding
+// - Numerical stability (subtract max before exp)
+// - ggml broadcasting rules for mask tensors
+//
+// Mask Broadcasting Rules (ggml-specific, not standard numpy):
+// - Dimension 0: mask.ne[0] == input.ne[0] (exact match required)
+// - Dimension 1: mask.ne[1] >= input.ne[1] (allows larger pre-allocated masks)
+// - Dimension 2: input.ne[2] % mask.ne[2] == 0 (modulo broadcasting)
+// - Dimension 3: input.ne[3] % mask.ne[3] == 0 (modulo broadcasting)
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <assert.h>
+#include <math.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+// Softmax kernel parameters structure (from ggml-et-ops.h)
+struct ggml_et_softmax_params {
+    struct ggml_tensor src0;      // F32 input tensor
+    struct ggml_tensor src1;      // F32 mask tensor (optional, may be zeroed if not used)
+    struct ggml_tensor src2;      // F32 sinks tensor (optional, may be zeroed if not used)
+    struct ggml_tensor dst;       // F32 output tensor
+    float              scale;     // Scale factor (temperature scaling)
+    float              max_bias;  // Max bias for ALiBi (0.0f if not used)
+};
+
+#define LOG2E_F 1.4426950408889634f
+
+typedef struct {
+    float    max_val;
+    float    sum_val;
+    uint32_t valid_mask;
+} softmax_params_t;
+
+static inline bool softmax_lane_is_valid(float x) {
+    return (x == x) && (x != -INFINITY) && (x != INFINITY);
+}
+
+static inline softmax_params_t softmax_params_empty(void) {
+    softmax_params_t p;
+    p.max_val    = -INFINITY;
+    p.sum_val    = 0.0f;
+    p.valid_mask = 0;
+    return p;
+}
+
+// chunk_transform_ps_8_branchless_mask
+//
+// Vector transform for 8 logits:
+//
+//   x = src * scale + (mask ? mask * slope : 0)
+//
+// Implemented branchlessly so masked and unmasked paths share the same
+// instruction stream. Used by pass1 and pass2 vector loops.
+static inline void chunk_transform_ps_8_branchless_mask(float *       tmp8,
+                                                        const float * src,
+                                                        const float * mask,
+                                                        float         scale,
+                                                        float         slope) {
+    unsigned long       ms;
+    const float         zero         = 0.0f;
+    const unsigned long mask_load_m0 = (mask != NULL) ? 0xFFul : 0x00ul;
+    const float *       mp           = (mask != NULL) ? mask : &zero;
+
+    __asm__ volatile(
+        "mova.x.m  %[ms]                \n\t"
+
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+        "fbc.ps    f10, 0(%[p_scale])   \n\t"
+        "fbc.ps    f11, 0(%[p_slope])   \n\t"
+        "fbc.ps    f1, 0(%[p_zero])    \n\t"
+
+        "mov.m.x   m0, %[maskm0], 0     \n\t"  // load mask if needed
+        "flw.ps    f1, 0(%[mp])         \n\t"
+
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+
+        "flw.ps    f0, 0(%[sp])         \n\t"
+        "fmul.ps   f0, f0, f10          \n\t"
+        "fmul.ps   f1, f1, f11          \n\t"
+        "fadd.ps   f0, f0, f1, rne      \n\t"
+        "fsw.ps    f0, 0(%[tp])         \n\t"
+
+        "mova.m.x  %[ms]                \n\t"
+        : [ms] "=&r"(ms)
+        : [tp] "r"(tmp8), [sp] "r"(src), [mp] "r"(mp), [p_zero] "r"(&zero), [p_scale] "r"(&scale),
+          [p_slope] "r"(&slope), [maskm0] "r"(mask_load_m0)
+        : "f0", "f1", "f10", "f11", "memory");
+}
+
+// chunk_transform_ps_8_tail
+//
+// Same as chunk_transform_ps_8_branchless_mask but gates loads, compute,
+// and stores with a caller-supplied m0 mask so that only `count` elements
+// (1-7) are touched.  Used for the last sub-8 chunk of a non-aligned row.
+static inline void chunk_transform_ps_8_tail(float *       tmp8,
+                                             const float * src,
+                                             const float * mask,
+                                             float         scale,
+                                             float         slope,
+                                             unsigned long tail_m0) {
+    unsigned long       ms;
+    const float         zero         = 0.0f;
+    const unsigned long mask_load_m0 = (mask != NULL) ? tail_m0 : 0x00ul;
+    const float *       mp           = (mask != NULL) ? mask : &zero;
+
+    __asm__ volatile(
+        "mova.x.m  %[ms]                \n\t"
+
+        // Broadcast constants with all lanes enabled
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+        "fbc.ps    f10, 0(%[p_scale])   \n\t"
+        "fbc.ps    f11, 0(%[p_slope])   \n\t"
+        "fbc.ps    f1, 0(%[p_zero])    \n\t"
+
+        // Load mask data gated by tail mask
+        "mov.m.x   m0, %[maskm0], 0     \n\t"
+        "flw.ps    f1, 0(%[mp])         \n\t"
+
+        // Load source, compute, and store gated by tail mask
+        "mov.m.x   m0, %[tailm0], 0     \n\t"
+
+        "flw.ps    f0, 0(%[sp])         \n\t"
+        "fmul.ps   f0, f0, f10          \n\t"
+        "fmul.ps   f1, f1, f11          \n\t"
+        "fadd.ps   f0, f0, f1, rne      \n\t"
+        "fsw.ps    f0, 0(%[tp])         \n\t"
+
+        "mova.m.x  %[ms]                \n\t"
+        : [ms] "=&r"(ms)
+        : [tp] "r"(tmp8), [sp] "r"(src), [mp] "r"(mp), [p_zero] "r"(&zero), [p_scale] "r"(&scale),
+          [p_slope] "r"(&slope), [maskm0] "r"(mask_load_m0), [tailm0] "r"(tail_m0)
+        : "f0", "f1", "f10", "f11", "memory");
+}
+
+// softmax_pass1_range
+//
+// Computes the numerically-stable softmax scan over a sub-range of a row.
+//
+// This implements the 1st pass of online softmax
+//
+//   max' = max(max, x)
+//   sum' = sum * exp(old_max - max') + exp(x - max')
+//
+// and returns a partial result containing:
+//
+//   - max_val : maximum logit observed in this range
+//   - sum_val : exp-normalized sum relative to max_val
+//
+// These partial results can be merged with softmax_params_merge() to obtain
+// the result for the full row.
+static inline softmax_params_t softmax_pass1_range(const float * src,
+                                                   const float * mask,
+                                                   int           begin,
+                                                   int           end,
+                                                   float         scale,
+                                                   float         slope) {
+    __attribute__((aligned(32))) float lane_max[8];
+    __attribute__((aligned(32))) float lane_sum[8];
+    __attribute__((aligned(32))) float tmp[8];
+
+    uint8_t valid_mask = 0;
+
+    const float one_f   = 1.0f;
+    const float zero_f  = 0.0f;
+    const float neg_inf = -INFINITY;
+    const float log2e   = LOG2E_F;
+
+    unsigned long ms;
+
+    __asm__ volatile(
+        "mova.x.m  %[ms]                \n\t"
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+        "fbc.ps    f20, 0(%[p_ninf])    \n\t"
+        "fbc.ps    f21, 0(%[p_zero])    \n\t"
+        "fbc.ps    f22, 0(%[p_one])     \n\t"
+        "fbc.ps    f23, 0(%[p_log2e])   \n\t"
+        : [ms] "=&r"(ms)
+        : [p_ninf] "r"(&neg_inf), [p_zero] "r"(&zero_f), [p_one] "r"(&one_f), [p_log2e] "r"(&log2e)
+        : "f20", "f21", "f22", "f23");
+
+    const int aligned_end = begin + ((end - begin) & ~7);
+
+    // Process full 8-element chunks
+    int i = begin;
+    for (; i < aligned_end; i += 8) {
+        chunk_transform_ps_8_branchless_mask(tmp, src + i, mask ? (mask + i) : NULL, scale, slope);
+
+        uint8_t cur_mask = 0;
+        for (int j = 0; j < 8; ++j) {
+            if (softmax_lane_is_valid(tmp[j])) {
+                cur_mask |= (uint8_t) (1u << j);
+            }
+        }
+
+        const uint8_t init_mask = (uint8_t) (cur_mask & ~valid_mask);
+        const uint8_t upd_mask  = (uint8_t) (cur_mask & valid_mask);
+
+        if (init_mask || upd_mask) {
+            __asm__ volatile(
+                "flw.ps    f0, 0(%[p_tmp])       \n\t"
+
+                "mov.m.x   m0, %[initm], 0       \n\t"
+                "fcmovm.ps f20, f0,  f20         \n\t"
+                "fcmovm.ps f21, f22, f21         \n\t"
+
+                "mov.m.x   m0, %[updm], 0        \n\t"
+                "fmax.ps   f1, f20, f0           \n\t"
+
+                "fsub.ps   f2, f20, f1, rne      \n\t"
+                "fmul.ps   f2, f2,  f23          \n\t"
+                "fexp.ps   f2, f2                \n\t"
+
+                "fsub.ps   f3, f0,  f1, rne      \n\t"
+                "fmul.ps   f3, f3,  f23          \n\t"
+                "fexp.ps   f3, f3                \n\t"
+
+                "fmul.ps   f21, f21, f2          \n\t"
+                "fadd.ps   f21, f21, f3, rne     \n\t"
+                "fcmovm.ps f20, f1,  f20         \n\t"
+
+                "mov.m.x   m0, x0, 0xFF          \n\t"
+                :
+                : [p_tmp] "r"(tmp), [initm] "r"((unsigned long) init_mask), [updm] "r"((unsigned long) upd_mask)
+                : "f0", "f1", "f2", "f3", "memory");
+
+            valid_mask |= cur_mask;
+        }
+    }
+
+    // Tail chunk: m0-gated load/compute/store for remaining 1-7 elements
+    if (i < end) {
+        const unsigned long tail_m0 = (1ul << (end - i)) - 1;
+
+        // Fill tmp with NaN so invalid lanes fail softmax_lane_is_valid
+        for (int j = 0; j < 8; j++) {
+            tmp[j] = __builtin_nanf("");
+        }
+
+        chunk_transform_ps_8_tail(tmp, src + i, mask ? (mask + i) : NULL, scale, slope, tail_m0);
+
+        uint8_t cur_mask = 0;
+        for (int j = 0; j < 8; ++j) {
+            if (softmax_lane_is_valid(tmp[j])) {
+                cur_mask |= (uint8_t) (1u << j);
+            }
+        }
+
+        const uint8_t init_mask = (uint8_t) (cur_mask & ~valid_mask);
+        const uint8_t upd_mask  = (uint8_t) (cur_mask & valid_mask);
+
+        if (init_mask || upd_mask) {
+            __asm__ volatile(
+                "flw.ps    f0, 0(%[p_tmp])       \n\t"
+
+                "mov.m.x   m0, %[initm], 0       \n\t"
+                "fcmovm.ps f20, f0,  f20         \n\t"
+                "fcmovm.ps f21, f22, f21         \n\t"
+
+                "mov.m.x   m0, %[updm], 0        \n\t"
+                "fmax.ps   f1, f20, f0           \n\t"
+
+                "fsub.ps   f2, f20, f1, rne      \n\t"
+                "fmul.ps   f2, f2,  f23          \n\t"
+                "fexp.ps   f2, f2                \n\t"
+
+                "fsub.ps   f3, f0,  f1, rne      \n\t"
+                "fmul.ps   f3, f3,  f23          \n\t"
+                "fexp.ps   f3, f3                \n\t"
+
+                "fmul.ps   f21, f21, f2          \n\t"
+                "fadd.ps   f21, f21, f3, rne     \n\t"
+                "fcmovm.ps f20, f1,  f20         \n\t"
+
+                "mov.m.x   m0, x0, 0xFF          \n\t"
+                :
+                : [p_tmp] "r"(tmp), [initm] "r"((unsigned long) init_mask), [updm] "r"((unsigned long) upd_mask)
+                : "f0", "f1", "f2", "f3", "memory");
+
+            valid_mask |= cur_mask;
+        }
+    }
+
+    __asm__ volatile(
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+        "fsw.ps    f20, 0(%[p_lmax])    \n\t"
+        "fsw.ps    f21, 0(%[p_lsum])    \n\t"
+        "mova.m.x  %[ms]                \n\t"
+        :
+        : [p_lmax] "r"(lane_max), [p_lsum] "r"(lane_sum), [ms] "r"(ms)
+        : "memory");
+
+    softmax_params_t out = softmax_params_empty();
+    out.valid_mask       = valid_mask;
+
+    for (int k = 0; k < 8; ++k) {
+        if (valid_mask & (1u << k)) {
+            if (out.valid_mask == (1u << k) || out.max_val == -INFINITY || lane_max[k] > out.max_val) {
+                out.max_val = lane_max[k];
+            }
+        }
+    }
+
+    if (out.max_val != -INFINITY) {
+        // Compute lane correction factors via fexp.ps to stay consistent
+        // with the fexp.ps used inside the online softmax loop above.
+        // corr[k] = exp2((lane_max[k] - out.max_val) * LOG2E) = exp(lane_max[k] - out.max_val)
+        const float                        neg_max_l2 = -out.max_val * LOG2E_F;
+        __attribute__((aligned(32))) float corr[8];
+        __asm__ volatile(
+            "mova.x.m  %[ms]              \n\t"
+            "mov.m.x   m0, x0, 0xFF       \n\t"
+            "fbc.ps    f0, 0(%[p_nml2])   \n\t"
+            "fbc.ps    f2, 0(%[p_l2e])    \n\t"
+            "flw.ps    f1, 0(%[p_lmax])   \n\t"
+            "fmadd.ps  f0, f1, f2, f0     \n\t"
+            "fexp.ps   f0, f0             \n\t"
+            "fsw.ps    f0, 0(%[p_corr])   \n\t"
+            "mova.m.x  %[ms]              \n\t"
+            :
+            : [p_nml2] "r"(&neg_max_l2), [p_l2e] "r"(&log2e), [p_lmax] "r"(lane_max), [p_corr] "r"(corr), [ms] "r"(ms)
+            : "f0", "f1", "f2", "memory");
+        for (int k = 0; k < 8; ++k) {
+            if (valid_mask & (1u << k)) {
+                out.sum_val += lane_sum[k] * corr[k];
+            }
+        }
+    }
+
+    return out;
+}
+
+// Pass 2 (normalize) over [begin, end).
+//
+// Computes: dst[i] = exp(x[i]*scale + mask[i]*slope - max) / sum
+//
+// Uses fexp.ps for the numerator; the denominator (params.sum_val) must
+// already be fully computed by the caller (pass1 + any sink merge).
+static inline void softmax_pass2_range(float *          dst,
+                                       const float *    src,
+                                       const float *    mask,
+                                       int              begin,
+                                       int              end,
+                                       float            scale,
+                                       float            slope,
+                                       softmax_params_t params) {
+    const float s2      = scale * LOG2E_F;
+    const float sl2     = slope * LOG2E_F;
+    const float neg_ml2 = -params.max_val * LOG2E_F;
+    const float inv_sum = et_fdiv(1.0f, params.sum_val);
+
+    unsigned long ms;
+
+    __asm__ volatile(
+        "mova.x.m  %[ms]                \n\t"
+        "mov.m.x   m0, x0, 0xFF         \n\t"
+        "fbc.ps    f10, 0(%[p_s2])      \n\t"
+        "fbc.ps    f12, 0(%[p_nml2])    \n\t"
+        "fbc.ps    f13, 0(%[p_inv])     \n\t"
+        : [ms] "=&r"(ms)
+        : [p_s2] "r"(&s2), [p_nml2] "r"(&neg_ml2), [p_inv] "r"(&inv_sum)
+        : "f10", "f12", "f13");
+
+    const int aligned_end = begin + ((end - begin) & ~7);
+
+    if (mask != NULL) {
+        __asm__ volatile("fbc.ps    f11, 0(%[p_sl2]) \n\t" : : [p_sl2] "r"(&sl2) : "f11");
+
+        for (int c = begin; c < aligned_end; c += 8) {
+            __asm__ volatile(
+                "flw.ps    f0, 0(%[sp])           \n\t"
+                "flw.ps    f1, 0(%[mp])           \n\t"
+                "fmadd.ps  f0, f0, f10, f12       \n\t"
+                "fmadd.ps  f0, f1, f11, f0        \n\t"
+                "fexp.ps   f0, f0                 \n\t"
+                "fmul.ps   f0, f0, f13            \n\t"
+                "fsw.ps    f0, 0(%[dp])           \n\t"
+                :
+                : [sp] "r"(src + c), [mp] "r"(mask + c), [dp] "r"(dst + c)
+                : "f0", "f1", "memory");
+        }
+
+        // Tail chunk with m0 gating
+        if (aligned_end < end) {
+            const unsigned long tail_m0 = (1ul << (end - aligned_end)) - 1;
+            __asm__ volatile(
+                "mov.m.x   m0, %[tm], 0              \n\t"
+                "flw.ps    f0, 0(%[sp])           \n\t"
+                "flw.ps    f1, 0(%[mp])           \n\t"
+                "fmadd.ps  f0, f0, f10, f12       \n\t"
+                "fmadd.ps  f0, f1, f11, f0        \n\t"
+                "fexp.ps   f0, f0                 \n\t"
+                "fmul.ps   f0, f0, f13            \n\t"
+                "fsw.ps    f0, 0(%[dp])           \n\t"
+                "mov.m.x   m0, x0, 0xFF           \n\t"
+                :
+                : [sp] "r"(src + aligned_end), [mp] "r"(mask + aligned_end), [dp] "r"(dst + aligned_end),
+                  [tm] "r"(tail_m0)
+                : "f0", "f1", "memory");
+        }
+    } else {
+        for (int c = begin; c < aligned_end; c += 8) {
+            __asm__ volatile(
+                "flw.ps    f0, 0(%[sp])           \n\t"
+                "fmadd.ps  f0, f0, f10, f12       \n\t"
+                "fexp.ps   f0, f0                 \n\t"
+                "fmul.ps   f0, f0, f13            \n\t"
+                "fsw.ps    f0, 0(%[dp])           \n\t"
+                :
+                : [sp] "r"(src + c), [dp] "r"(dst + c)
+                : "f0", "memory");
+        }
+
+        // Tail chunk with m0 gating
+        if (aligned_end < end) {
+            const unsigned long tail_m0 = (1ul << (end - aligned_end)) - 1;
+            __asm__ volatile(
+                "mov.m.x   m0, %[tm], 0              \n\t"
+                "flw.ps    f0, 0(%[sp])           \n\t"
+                "fmadd.ps  f0, f0, f10, f12       \n\t"
+                "fexp.ps   f0, f0                 \n\t"
+                "fmul.ps   f0, f0, f13            \n\t"
+                "fsw.ps    f0, 0(%[dp])           \n\t"
+                "mov.m.x   m0, x0, 0xFF           \n\t"
+                :
+                : [sp] "r"(src + aligned_end), [dp] "r"(dst + aligned_end), [tm] "r"(tail_m0)
+                : "f0", "memory");
+        }
+    }
+
+    __asm__ volatile("mova.m.x  %[ms] \n\t" ::[ms] "r"(ms));
+}
+
+// Single-core row path.
+// pass1_range and pass2_range handle non-8-aligned cols internally via
+// m0-gated tail chunks, so this function just passes cols directly.
+static inline void compute_softmax_row(float *       dst,
+                                       const float * src,
+                                       const float * mask,
+                                       int           cols,
+                                       float         scale,
+                                       float         slope,
+                                       float         sink_value,
+                                       bool          use_sinks) {
+    softmax_params_t params = softmax_pass1_range(src, mask, 0, cols, scale, slope);
+
+    if (use_sinks) {
+        // For sinks, use fully scalar et_expf to match the reference CPU
+        // backend's expf precision.  Sink tests use small arrays (ne<=32)
+        // so the scalar path has negligible performance impact.
+        float max_val = params.max_val;
+        if (sink_value > max_val) {
+            max_val = sink_value;
+        }
+
+        // Compute sum = Σ exp(x'[i] - max) + exp(sink - max)  (scalar)
+        float sum = 0.0f;
+        for (int i = 0; i < cols; ++i) {
+            float x = src[i] * scale;
+            if (mask != NULL) {
+                x += mask[i] * slope;
+            }
+            sum += et_expf(x - max_val);
+        }
+        sum += et_expf(sink_value - max_val);
+
+        // Normalize: dst[i] = exp(x'[i] - max) / sum  (scalar)
+        float inv_sum = et_fdiv(1.0f, sum);
+        for (int i = 0; i < cols; ++i) {
+            float x = src[i] * scale;
+            if (mask != NULL) {
+                x += mask[i] * slope;
+            }
+            dst[i] = et_expf(x - max_val) * inv_sum;
+        }
+    } else {
+        if (!params.valid_mask) {
+            return;
+        }
+        softmax_pass2_range(dst, src, mask, 0, cols, scale, slope, params);
+    }
+}
+
+// Main entry point for Softmax kernel
+int entry_point(struct ggml_et_softmax_params * params, void * env) {
+    // Cast env to proper type
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    // Validate environment pointer
+    if (!kernel_env) {
+        return -1;
+    }
+
+    // Get thread info using shire mask from environment
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    // Return early if this hart is not active
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    // Basic safety check on params
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    // Extract tensor references
+    struct ggml_tensor * src0     = &params->src0;     // Input tensor
+    struct ggml_tensor * src1     = &params->src1;     // Mask tensor (optional)
+    struct ggml_tensor * src2     = &params->src2;     // Sinks tensor (optional)
+    struct ggml_tensor * dst      = &params->dst;      // Output tensor
+    float                scale    = params->scale;     // Scale factor
+    float                max_bias = params->max_bias;  // ALiBi max bias
+
+    // Validate tensor types (F32 only)
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    // Check if mask is used and validate type
+    bool use_mask = (src1->data != NULL && (src1->type == GGML_TYPE_F32 || src1->type == GGML_TYPE_F16));
+
+    bool use_sinks = (src2->data != NULL && src2->type == GGML_TYPE_F32);
+
+    float * src0_data  = (float *) src0->data;
+    float * dst_data   = (float *) dst->data;
+    float * mask_data  = use_mask ? (float *) src1->data : NULL;
+    float * sinks_data = use_sinks ? (float *) src2->data : NULL;
+
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+
+    const int64_t ne00 = src0->ne[0];  // Sequence length (columns)
+    const int64_t ne01 = src0->ne[1];  // Number of rows
+    const int64_t ne02 = src0->ne[2];  // Batch/head dimension
+    const int64_t ne03 = src0->ne[3];  // Outer batch dimension
+
+    // Fast path: softmax of a single element is always 1.0
+    // (exp(x) / exp(x) == 1 for any x, regardless of scale/mask/bias)
+    // Skip all ALiBi, mask, and sink setup.
+    //
+    // Each output element is 4 bytes.  A cache line is 64 bytes = 16 floats.
+    // L1 is not coherent across harts, so each thread must own whole cache
+    // lines to avoid cross-hart conflicts.
+    if (ne00 == 1) {
+        const int64_t total_elems  = ne01 * ne02 * ne03;
+        const int64_t elems_per_cl = ET_CACHE_LINE_SIZE_BYTES / (int64_t) sizeof(float);  // 16
+        const int64_t total_cls    = (total_elems + elems_per_cl - 1) / elems_per_cl;
+
+        for (int64_t cl = thread_id; cl < total_cls; cl += num_threads) {
+            const int64_t start = cl * elems_per_cl;
+            int64_t       end   = start + elems_per_cl;
+            if (end > total_elems) {
+                end = total_elems;
+            }
+            for (int64_t idx = start; idx < end; idx++) {
+                dst_data[idx] = 1.0f;
+            }
+        }
+        return 0;
+    }
+
+    const int64_t ne10 = use_mask ? src1->ne[0] : 0;  // Mask sequence length
+    const int64_t ne11 = use_mask ? src1->ne[1] : 0;  // Mask rows
+    const int64_t ne12 = use_mask ? src1->ne[2] : 0;  // Mask batch/head dimension
+    const int64_t ne13 = use_mask ? src1->ne[3] : 0;  // Mask outer batch dimension
+
+    if (use_mask) {
+        // - Dimension 0: mask must equal input exactly
+        // - Dimension 1: mask must be >= input (allows larger pre-allocated masks)
+        // - Dimension 2: input must be divisible by mask (modulo broadcasting)
+        // - Dimension 3: input must be divisible by mask (modulo broadcasting)
+        if (ne10 != ne00 ||                    // Dimension 0: exact match required
+            ne11 < ne01 ||                     // Dimension 1: mask >= input
+            (ne12 > 0 && ne02 % ne12 != 0) ||  // Dimension 2: input % mask == 0
+            (ne13 > 0 && ne03 % ne13 != 0)) {  // Dimension 3: input % mask == 0
+            return -1;                         // Incompatible dimensions for ggml softmax broadcasting
+        }
+    }
+
+    // ALiBi slope calculation - compute per attention head
+    const uint32_t n_head      = (uint32_t) ne02;
+    uint32_t       n_head_log2 = 0;
+    float          m0          = 1.0f;
+    float          m1          = 1.0f;
+
+    if (max_bias > 0.0f) {
+        // This is equivalent to: 1 << floor(log2(n_head))
+        n_head_log2 = 1;
+        while (n_head_log2 < n_head) {
+            n_head_log2 <<= 1;
+        }
+        if (n_head_log2 > n_head) {
+            n_head_log2 >>= 1;
+        }
+
+        // Compute base slopes for ALiBi
+        // m0 = 2^(-max_bias / n_head_log2)
+        // m1 = 2^(-max_bias / (2 * n_head_log2))
+        float inv_n_head_log2 = et_fdiv(1.0f, (float) n_head_log2);
+        m0                    = et_expf(-max_bias * 0.69314718f * inv_n_head_log2);  // 0.69314718 = ln(2)
+        m1                    = et_expf(-max_bias * 0.69314718f * inv_n_head_log2 * 0.5f);
+    }
+
+    // Process tensor row by row in parallel across flattened rows.
+    // Flattened row index spans [i03, i02, i01] with row length ne00.
+    //
+    // When ne00 * sizeof(float) is not a multiple of the cache line size,
+    // adjacent rows share cache lines.  Assign contiguous write groups to
+    // each thread so every thread's write footprint covers whole cache
+    // lines, preventing cross-hart L1 coherency issues.  When rows ARE
+    // cache-line aligned, rows_per_wg == 1 and this degenerates to the
+    // original stride-by-num_threads distribution.
+    const int64_t rows_per_i03 = ne02 * ne01;
+    const int64_t total_rows   = ne03 * rows_per_i03;
+    const int64_t rows_per_wg  = et_rows_per_cacheline_group(ne00, sizeof(float));
+    const int64_t total_wgs    = (total_rows + rows_per_wg - 1) / rows_per_wg;
+
+    for (int64_t wg = thread_id; wg < total_wgs; wg += num_threads) {
+        const int64_t row_start = wg * rows_per_wg;
+        int64_t       row_end   = row_start + rows_per_wg;
+        if (row_end > total_rows) {
+            row_end = total_rows;
+        }
+
+        for (int64_t row = row_start; row < row_end; row++) {
+            const int64_t i03 = row / rows_per_i03;
+            const int64_t rem = row % rows_per_i03;
+            const int64_t i02 = rem / ne01;
+            const int64_t i01 = rem % ne01;
+
+            // Calculate ALiBi slope for this attention head
+            float slope = 1.0f;
+            if (max_bias > 0.0f) {
+                const uint32_t h = (uint32_t) i02;  // head index
+                if (h < n_head_log2) {
+                    slope = m0;
+                    for (uint32_t i = 0; i < h; i++) {
+                        slope *= m0;
+                    }
+                } else {
+                    const uint32_t exp = 2 * (h - n_head_log2) + 1;
+                    slope              = m1;
+                    for (uint32_t i = 1; i < exp; i++) {
+                        slope *= m1;
+                    }
+                }
+            }
+
+            float sink_value = 0.0f;
+            if (use_sinks && sinks_data) {
+                sink_value = sinks_data[i02];
+            }
+
+            const int64_t src_offset = i03 * ne02 * ne01 * ne00 + i02 * ne01 * ne00 + i01 * ne00;
+
+            const float * src_row  = src0_data + src_offset;
+            float *       dst_row  = dst_data + src_offset;
+            const float * mask_row = NULL;
+
+            if (use_mask && mask_data) {
+                const int64_t mask_i03 = (ne13 > 0) ? i03 % ne13 : 0;
+                const int64_t mask_i02 = (ne12 > 0) ? i02 % ne12 : 0;
+                const int64_t mask_i01 = i01;
+
+                const int64_t mask_offset = mask_i03 * ne12 * ne11 * ne10 + mask_i02 * ne11 * ne10 + mask_i01 * ne10;
+
+                mask_row = mask_data + mask_offset;
+            }
+
+            compute_softmax_row(dst_row, src_row, mask_row, (int) ne00, scale, slope, sink_value, use_sinks);
+        }
+    }
+
+    return 0;  // Success
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/solve_tri_f32.c b/ggml/src/ggml-et/et-kernels/src/solve_tri_f32.c
new file mode 100644 (file)
index 0000000..b65e299
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/solve_tri_f32.c
@@ -0,0 +1,109 @@
+//******************************************************************************
+// Solve Triangular F32 Kernel
+// Forward substitution: solve AX = B where A is lower-triangular.
+//
+// src0 (A): [n, n, B1, B2]  lower-triangular matrix
+// src1 (B): [k, n, B1, B2]  right-hand side
+// dst  (X): [k, n, B1, B2]  solution
+//
+// For each column j (parallelized across threads):
+//   For i = 0..n-1:
+//     X[i,j] = (B[i,j] - dot(A[i,0..i-1], X[0..i-1,j])) / A[i,i]
+//
+// Lower-triangular, left-side, non-unit variant implemented.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_solve_tri_params {
+    struct ggml_tensor src0;  // A: lower-triangular [n, n, B1, B2]
+    struct ggml_tensor src1;  // B: RHS [k, n, B1, B2]
+    struct ggml_tensor dst;   // X: solution [k, n, B1, B2]
+};
+
+int entry_point(struct ggml_et_solve_tri_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;  // A
+    struct ggml_tensor * src1 = &params->src1;  // B
+    struct ggml_tensor * dst  = &params->dst;   // X
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float * A_data = (const float *) src0->data;
+    const float * B_data = (const float *) src1->data;
+    float *       X_data = (float *) dst->data;
+
+    if (!A_data || !B_data || !X_data) {
+        return -1;
+    }
+
+    const int64_t n   = src0->ne[1];  // A is n×n
+    const int64_t k   = src1->ne[0];  // number of RHS columns
+    const int64_t ne2 = src0->ne[2];
+    const int64_t ne3 = src0->ne[3];
+
+    // Strides in bytes
+    const size_t nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    const size_t nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3];
+    const size_t nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+
+    // k % 16 == 0 guaranteed by supports_op. Rows are cache-line aligned,
+    // so column groups of 16 map to exclusive cache lines.
+    // TODO: Vectorize the thing
+    const int64_t cols_per_cl    = 16;
+    const int64_t num_col_groups = k / cols_per_cl;
+    const int64_t total_work     = num_col_groups * ne2 * ne3;
+
+    for (int64_t work = thread_id; work < total_work; work += num_threads) {
+        const int64_t cg = work % num_col_groups;
+        const int64_t i2 = (work / num_col_groups) % ne2;
+        const int64_t i3 = work / (num_col_groups * ne2);
+
+        const int64_t j_start = cg * cols_per_cl;
+        const int64_t j_end   = j_start + cols_per_cl;
+
+        const float * A_batch = (const float *) ((const char *) A_data + i2 * nb02 + i3 * nb03);
+        const float * B_batch = (const float *) ((const char *) B_data + i2 * nb12 + i3 * nb13);
+        float *       X_batch = (float *) ((char *) X_data + i2 * nb2 + i3 * nb3);
+
+        for (int64_t j = j_start; j < j_end; j++) {
+            for (int64_t i = 0; i < n; i++) {
+                const float * A_row = (const float *) ((const char *) A_batch + i * nb01);
+                float *       X_row = (float *) ((char *) X_batch + i * nb1);
+                const float * B_row = (const float *) ((const char *) B_batch + i * nb11);
+
+                float sum = 0.0f;
+                for (int64_t t = 0; t < i; t++) {
+                    const float * X_t = (const float *) ((const char *) X_batch + t * nb1);
+                    sum += A_row[t] * X_t[j];
+                }
+
+                X_row[j] = et_fdiv(B_row[j] - sum, A_row[i]);
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/sqr_f32.c b/ggml/src/ggml-et/et-kernels/src/sqr_f32.c
new file mode 100644 (file)
index 0000000..c184ab7
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/sqr_f32.c
@@ -0,0 +1,88 @@
+//******************************************************************************
+// SQR F32 Kernel
+// Element-wise square: y[i] = x[i] * x[i]
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+// SQR kernel parameters structure (unary op: src0 -> dst)
+struct ggml_et_sqr_params {
+    struct ggml_tensor src0;  // F32 input tensor
+    struct ggml_tensor dst;   // F32 output tensor
+};
+
+int entry_point(struct ggml_et_sqr_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;  // Invalid pointer
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;  // Unsupported type combination
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;  // Null data pointer
+    }
+
+    // Both src and dst are contiguous F32: flatten and distribute by cache lines
+    const int64_t total_elements         = dst->ne[0] * dst->ne[1] * dst->ne[2] * dst->ne[3];
+    const int64_t elements_per_cacheline = 16;  // 64 bytes / 4 bytes per float
+    const int64_t total_cachelines       = (total_elements + elements_per_cacheline - 1) / elements_per_cacheline;
+
+    const int64_t cl_per_thread = (total_cachelines + num_threads - 1) / num_threads;
+    const int64_t cl_start      = thread_id * cl_per_thread;
+    int64_t       cl_end        = cl_start + cl_per_thread;
+    if (cl_end > total_cachelines) {
+        cl_end = total_cachelines;
+    }
+
+    if (cl_start >= total_cachelines) {
+        return 0;
+    }
+
+    const int64_t elem_start = cl_start * elements_per_cacheline;
+    int64_t       elem_end   = cl_end * elements_per_cacheline;
+    if (elem_end > total_elements) {
+        elem_end = total_elements;
+    }
+
+    const float * src_ptr = src0_data + elem_start;
+    float *       dst_ptr = dst_data + elem_start;
+    const int32_t count   = (int32_t) (elem_end - elem_start);
+
+    // Process 8 elements at a time: dst[i] = src[i] * src[i]
+    for (int32_t i0 = 0; i0 < count; i0 += 8) {
+        __asm__ volatile(
+            "flw.ps f10, %[x_vec]\n"   // Load 8 input values
+            "fmul.ps f11, f10, f10\n"  // x * x (8-wide)
+            "fsw.ps f11, %[result]\n"  // Store 8 results
+
+            : [result] "=m"(*(float (*)[8]) & dst_ptr[i0])
+            : [x_vec] "m"(*(const float (*)[8]) & src_ptr[i0])
+            : "f10", "f11");
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/ssm_conv_f32.c b/ggml/src/ggml-et/et-kernels/src/ssm_conv_f32.c
new file mode 100644 (file)
index 0000000..d65ef87
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/ssm_conv_f32.c
@@ -0,0 +1,129 @@
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_ssm_conv_params {
+    struct ggml_tensor src0;  // conv_x: [d_conv - 1 + n_t, d_inner, n_seqs]
+    struct ggml_tensor src1;  // conv1d.weight: [d_conv, d_inner]
+    struct ggml_tensor dst;   // output: [d_inner, n_t, n_seqs]
+};
+
+int entry_point(struct ggml_et_ssm_conv_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float * src0_data = (const float *) src0->data;
+    const float * src1_data = (const float *) src1->data;
+    float *       dst_data  = (float *) dst->data;
+
+    if (!src0_data || !src1_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t nc  = src1->ne[0];
+    const int64_t ncs = src0->ne[0];
+    const int64_t nr  = src0->ne[1];
+    const int64_t n_t = dst->ne[1];
+    const int64_t n_s = dst->ne[2];
+
+    if (dst->ne[0] != nr || src1->ne[1] != nr || ncs != nc - 1 + n_t || src0->nb[0] != sizeof(float) ||
+        src1->nb[0] != sizeof(float) || dst->nb[0] != sizeof(float) || src0->nb[1] != (size_t) ncs * sizeof(float) ||
+        src1->nb[1] != (size_t) nc * sizeof(float)) {
+        return -1;
+    }
+
+    // Parallelize over d_inner in cache-line-aligned chunks (16 floats = 64B)
+    const int64_t chunk    = 16;
+    const int64_t n_chunks = (nr + chunk - 1) / chunk;
+
+    // Save and set vector mask to all 8 lanes
+    unsigned long saved_mask;
+    __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+    __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+    for (int64_t i3 = 0; i3 < n_s; ++i3) {
+        for (int64_t i2 = 0; i2 < n_t; ++i2) {
+            const float * s = (const float *) ((const char *) src0_data + i2 * src0->nb[0] + i3 * src0->nb[2]);
+            float *       x = (float *) ((char *) dst_data + i2 * dst->nb[1] + i3 * dst->nb[2]);
+
+            for (int64_t ci = thread_id; ci < n_chunks; ci += num_threads) {
+                const int64_t i1_start = ci * chunk;
+                const int64_t i1_end   = i1_start + chunk < nr ? i1_start + chunk : nr;
+
+                // Process 8 channels at a time with SIMD
+                int64_t i1 = i1_start;
+                for (; i1 + 8 <= i1_end; i1 += 8) {
+                    // Gather 8 channels' data into contiguous buffers for each tap
+                    float tmp_s[8], tmp_c[8];
+                    float acc[8] = { 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f };
+
+                    for (int64_t i0 = 0; i0 < nc; ++i0) {
+                        // TODO: Some way to get rid of this gather
+                        for (int j = 0; j < 8; ++j) {
+                            tmp_s[j] = s[(i1 + j) * ncs + i0];
+                            tmp_c[j] = src1_data[(i1 + j) * nc + i0];
+                        }
+
+                        __asm__ volatile(
+                            "flw.ps f10, %[acc]\n"
+                            "flw.ps f11, %[sv]\n"
+                            "flw.ps f12, %[cv]\n"
+                            "fmadd.ps f10, f11, f12, f10\n"
+                            "fsw.ps f10, %[out]\n"
+                            : [out] "=m"(*(float (*)[8]) acc)
+                            : [acc] "m"(*(const float (*)[8]) acc), [sv] "m"(*(const float (*)[8]) tmp_s),
+                              [cv] "m"(*(const float (*)[8]) tmp_c)
+                            : "f10", "f11", "f12");
+                    }
+
+                    // Store 8 results — dst is contiguous along d_inner
+                    __asm__ volatile(
+                        "flw.ps f10, %[acc]\n"
+                        "fsw.ps f10, %[dst]\n"
+                        : [dst] "=m"(*(float (*)[8])(x + i1))
+                        : [acc] "m"(*(const float (*)[8]) acc)
+                        : "f10");
+                }
+
+                // Scalar tail for remaining channels
+                for (; i1 < i1_end; ++i1) {
+                    const float * c     = src1_data + i1 * nc;
+                    const float * s_row = s + i1 * ncs;
+                    float         sumf  = 0.0f;
+                    for (int64_t i0 = 0; i0 < nc; ++i0) {
+                        sumf += s_row[i0] * c[i0];
+                    }
+                    x[i1] = sumf;
+                }
+            }
+        }
+    }
+
+    // Restore mask
+    __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/ssm_scan_f32.c b/ggml/src/ggml-et/et-kernels/src/ssm_scan_f32.c
new file mode 100644 (file)
index 0000000..c114e99
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/ssm_scan_f32.c
@@ -0,0 +1,271 @@
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_ssm_scan_params {
+    struct ggml_tensor src0;  // s:   [d_state, head_dim, n_head, n_seqs]
+    struct ggml_tensor src1;  // x:   [head_dim, n_head, n_seq_tokens, n_seqs]
+    struct ggml_tensor src2;  // dt:  [n_head, n_seq_tokens, n_seqs]
+    struct ggml_tensor src3;  // A:   [d_state, n_head] or [1, n_head]
+    struct ggml_tensor src4;  // B:   [d_state, n_group, n_seq_tokens, n_seqs]
+    struct ggml_tensor src5;  // C:   [d_state, n_group, n_seq_tokens, n_seqs]
+    struct ggml_tensor src6;  // ids: [n_seqs] i32
+    struct ggml_tensor dst;   // packed [y, final_state]
+};
+
+static inline float softplus_f32(float x) {
+    return x <= 20.0f ? et_logf(1.0f + et_expf(x)) : x;
+}
+
+int entry_point(struct ggml_et_ssm_scan_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    const int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    const int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * src1 = &params->src1;
+    struct ggml_tensor * src2 = &params->src2;
+    struct ggml_tensor * src3 = &params->src3;
+    struct ggml_tensor * src4 = &params->src4;
+    struct ggml_tensor * src5 = &params->src5;
+    struct ggml_tensor * src6 = &params->src6;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || src1->type != GGML_TYPE_F32 || src2->type != GGML_TYPE_F32 ||
+        src3->type != GGML_TYPE_F32 || src4->type != GGML_TYPE_F32 || src5->type != GGML_TYPE_F32 ||
+        src6->type != GGML_TYPE_I32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    const float *   s_data   = (const float *) src0->data;
+    const float *   x_data   = (const float *) src1->data;
+    const float *   dt_data  = (const float *) src2->data;
+    const float *   A_data   = (const float *) src3->data;
+    const float *   B_data   = (const float *) src4->data;
+    const float *   C_data   = (const float *) src5->data;
+    const int32_t * ids      = (const int32_t *) src6->data;
+    float *         dst_data = (float *) dst->data;
+
+    if (!s_data || !x_data || !dt_data || !A_data || !B_data || !C_data || !ids || !dst_data) {
+        return -1;
+    }
+
+    const int64_t d_state      = src0->ne[0];
+    const int64_t head_dim     = src0->ne[1];
+    const int64_t n_head       = src1->ne[1];
+    const int64_t n_group      = src4->ne[1];
+    const int64_t n_seq_tokens = src1->ne[2];
+    const int64_t n_seqs       = src1->ne[3];
+    const int64_t y_elems      = src1->ne[0] * src1->ne[1] * src1->ne[2] * src1->ne[3];
+
+    if (src0->nb[0] != sizeof(float) || src1->nb[0] != sizeof(float) || src2->nb[0] != sizeof(float) ||
+        src3->nb[0] != sizeof(float) || src4->nb[0] != sizeof(float) || src5->nb[0] != sizeof(float) ||
+        src6->nb[0] != sizeof(int32_t) || dst->nb[0] != sizeof(float)) {
+        return -1;
+    }
+
+    if (n_group <= 0 || n_head % n_group != 0) {
+        return -1;
+    }
+
+    // Cache-line bundling on the dst output (1 dst float per (head, dim, token)).
+    //   - When head_dim < 16: bundle 16/head_dim heads per work-unit (1 line of dst).
+    //   - When head_dim >= 16: each head's dim slice spans head_dim/16 lines, so we
+    //     can split dims into chunks of 16 across threads without false sharing.
+    const int64_t dst_lanes_per_cl    = 16;
+    const int64_t heads_per_cacheline = head_dim >= dst_lanes_per_cl ? 1 : (dst_lanes_per_cl / head_dim);
+    const int64_t heads_per_block     = heads_per_cacheline > 0 ? heads_per_cacheline : 1;
+    const int64_t blocks_per_seq      = (n_head + heads_per_block - 1) / heads_per_block;
+    const int64_t dim_chunk_lanes     = head_dim >= dst_lanes_per_cl ? dst_lanes_per_cl : head_dim;
+    const int64_t dim_chunks_per_head = (head_dim + dim_chunk_lanes - 1) / dim_chunk_lanes;
+
+    // A "unit" = (seq, head_block, dim_chunk). This expands the parallelism by a
+    // factor of dim_chunks_per_head over the prior block-only scheme; for Mamba-2
+    // shapes (head_dim=64) that's a 4x bump in active threads.
+    const int64_t units_per_seq    = blocks_per_seq * dim_chunks_per_head;
+    const int64_t total_units      = n_seqs * units_per_seq;
+    const int64_t units_per_thread = (total_units + num_threads - 1) / num_threads;
+    const int64_t unit_begin       = (int64_t) thread_id * units_per_thread;
+    int64_t       unit_end         = unit_begin + units_per_thread;
+
+    if (unit_begin >= total_units) {
+        return 0;
+    }
+
+    if (unit_end > total_units) {
+        unit_end = total_units;
+    }
+
+    const int     A_broadcast = (src3->ne[0] == 1);
+    const int64_t d_state_vec = (d_state / 8) * 8;  // largest multiple of 8 <= d_state
+    const float   log2e_const = 1.4426950408889634f;
+
+    for (int64_t unit = unit_begin; unit < unit_end; ++unit) {
+        const int64_t seq_idx       = unit / units_per_seq;
+        const int64_t unit_in_seq   = unit % units_per_seq;
+        const int64_t block_in_seq  = unit_in_seq / dim_chunks_per_head;
+        const int64_t dim_chunk_idx = unit_in_seq % dim_chunks_per_head;
+        const int64_t head_begin    = block_in_seq * heads_per_block;
+        int64_t       head_end      = head_begin + heads_per_block;
+
+        if (head_end > n_head) {
+            head_end = n_head;
+        }
+
+        const int64_t dim_begin = dim_chunk_idx * dim_chunk_lanes;
+        int64_t       dim_end   = dim_begin + dim_chunk_lanes;
+        if (dim_end > head_dim) {
+            dim_end = head_dim;
+        }
+
+        const int32_t state_seq = ids[seq_idx];
+
+        for (int64_t head_idx = head_begin; head_idx < head_end; ++head_idx) {
+            const int64_t group_idx = head_idx / (n_head / n_group);
+
+            // A pointer for this head: contiguous over state_idx when not broadcast
+            const float * A_row = (const float *) ((const char *) A_data + (size_t) head_idx * src3->nb[1]);
+
+            for (int64_t dim_idx = dim_begin; dim_idx < dim_end; ++dim_idx) {
+                const float * state_src =
+                    (const float *) ((const char *) s_data + (size_t) dim_idx * src0->nb[1] +
+                                     (size_t) head_idx * src0->nb[2] + (size_t) state_seq * src0->nb[3]);
+
+                float * state_dst =
+                    (float *) ((char *) dst_data + (size_t) y_elems * sizeof(float) + (size_t) dim_idx * src0->nb[1] +
+                               (size_t) head_idx * src0->nb[2] + (size_t) seq_idx * src0->nb[3]);
+
+                for (int64_t token_idx = 0; token_idx < n_seq_tokens; ++token_idx) {
+                    const float * x_ptr =
+                        (const float *) ((const char *) x_data + (size_t) dim_idx * src1->nb[0] +
+                                         (size_t) head_idx * src1->nb[1] + (size_t) token_idx * src1->nb[2] +
+                                         (size_t) seq_idx * src1->nb[3]);
+
+                    const float * dt_ptr =
+                        (const float *) ((const char *) dt_data + (size_t) head_idx * src2->nb[0] +
+                                         (size_t) token_idx * src2->nb[1] + (size_t) seq_idx * src2->nb[2]);
+
+                    const float * B_row =
+                        (const float *) ((const char *) B_data + (size_t) group_idx * src4->nb[1] +
+                                         (size_t) token_idx * src4->nb[2] + (size_t) seq_idx * src4->nb[3]);
+
+                    const float * C_row =
+                        (const float *) ((const char *) C_data + (size_t) group_idx * src5->nb[1] +
+                                         (size_t) token_idx * src5->nb[2] + (size_t) seq_idx * src5->nb[3]);
+
+                    const float dt_softplus = softplus_f32(*dt_ptr);
+                    const float x_dt        = (*x_ptr) * dt_softplus;
+                    const float dt_log2e    = dt_softplus * log2e_const;
+
+                    // Source of "previous state" for this token: input state on token 0,
+                    // last token's state thereafter (we wrote it into state_dst).
+                    const float * prev_row = (token_idx == 0) ? state_src : state_dst;
+
+                    float   sumf      = 0.0f;
+                    int64_t state_idx = 0;
+
+                    if (d_state_vec > 0) {
+                        // Save mask, enable all 8 vector lanes for the state loop.
+                        unsigned long saved_mask;
+                        __asm__ volatile("mova.x.m %0" : "=r"(saved_mask));
+                        __asm__ volatile("mov.m.x m0, x0, 0xFF");
+
+                        // Per-token broadcasts:
+                        //   f20 = x_dt     (B*x_dt)
+                        //   f21 = dt_log2e (for fexp.ps when A is per-state)
+                        //   f22 = dA       (only when A is broadcast scalar)
+                        //   f23 = sum-of-products accumulator (zeroed)
+                        __asm__ volatile(
+                            "fbc.ps f20, %[xdt]\n\t"
+                            "fbc.ps f21, %[dtl]\n\t"
+                            "fbci.pi f23, 0\n\t"
+                            :
+                            : [xdt] "m"(x_dt), [dtl] "m"(dt_log2e)
+                            : "f20", "f21", "f23");
+
+                        if (A_broadcast) {
+                            // dA is a per-head scalar — compute once and splat.
+                            const float dA_scalar = et_expf(dt_softplus * (*A_row));
+                            __asm__ volatile("fbc.ps f22, %[da]\n\t" : : [da] "m"(dA_scalar) : "f22");
+                        }
+
+                        for (; state_idx < d_state_vec; state_idx += 8) {
+                            if (!A_broadcast) {
+                                // f22 = exp(dt_softplus * A[state..state+7])
+                                //     = 2^((dt_softplus * A) * log2e) via fexp.ps
+                                __asm__ volatile(
+                                    "flw.ps  f24, %[av]\n\t"
+                                    "fmul.ps f24, f24, f21\n\t"  // A * dt_log2e
+                                    "fexp.ps f22, f24\n\t"       // dA = 2^(...)
+                                    :
+                                    : [av] "m"(*(const float (*)[8]) & A_row[state_idx])
+                                    : "f22", "f24");
+                            }
+
+                            // state = prev * dA + B * x_dt
+                            // sumf += state * C
+                            // Reads prev before writing state_dst — safe even when
+                            // prev_row == state_dst (write-after-read, same index).
+                            __asm__ volatile(
+                                "flw.ps  f25, %[prev]\n\t"
+                                "flw.ps  f26, %[bv]\n\t"
+                                "flw.ps  f27, %[cv]\n\t"
+                                "fmul.ps f26, f26, f20\n\t"        // B * x_dt
+                                "fmadd.ps f25, f25, f22, f26\n\t"  // state = prev*dA + B*x_dt
+                                "fsw.ps  f25, %[sd]\n\t"
+                                "fmadd.ps f23, f25, f27, f23\n\t"  // sum += state*C
+                                : [sd] "=m"(*(float (*)[8]) & state_dst[state_idx])
+                                : [prev] "m"(*(const float (*)[8]) & prev_row[state_idx]),
+                                  [bv] "m"(*(const float (*)[8]) & B_row[state_idx]),
+                                  [cv] "m"(*(const float (*)[8]) & C_row[state_idx])
+                                : "f25", "f26", "f27");
+                        }
+
+                        // Horizontal reduce f23 (8 lanes) -> scalar sumf.
+                        __asm__ volatile(
+                            "fswizz.ps f1, f23, 0xB1\n\t"
+                            "fadd.ps   f2, f23, f1, rne\n\t"
+                            "fswizz.ps f3, f2, 0x4E\n\t"
+                            "fadd.ps   f4, f2, f3, rne\n\t"
+                            "fmvz.x.ps t0, f4, 4\n\t"
+                            "fbcx.ps   f5, t0\n\t"
+                            "fadd.ps   %[vout], f4, f5, rne\n\t"
+                            : [vout] "=f"(sumf)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+                        __asm__ volatile("mova.m.x %0" ::"r"(saved_mask));
+                    }
+
+                    // Scalar tail (d_state not a multiple of 8).
+                    for (; state_idx < d_state; ++state_idx) {
+                        const float prev_state = prev_row[state_idx];
+                        const float A_val      = A_broadcast ? *A_row : A_row[state_idx];
+                        const float dA         = et_expf(dt_softplus * A_val);
+                        const float st         = prev_state * dA + B_row[state_idx] * x_dt;
+                        state_dst[state_idx]   = st;
+                        sumf += st * C_row[state_idx];
+                    }
+
+                    dst_data[seq_idx * (n_seq_tokens * n_head * head_dim) + token_idx * (n_head * head_dim) +
+                             head_idx * head_dim + dim_idx] = sumf;
+                }
+            }
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/sum_rows_f32.c b/ggml/src/ggml-et/et-kernels/src/sum_rows_f32.c
new file mode 100644 (file)
index 0000000..968707f
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/sum_rows_f32.c
@@ -0,0 +1,103 @@
+//******************************************************************************
+// SUM_ROWS F32 Kernel
+// Row-wise sum reduction: dst[0, i1, i2, i3] = sum(src0[0..ne00-1, i1, i2, i3])
+// Vectorized 8-wide accumulation with horizontal reduction.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_sum_rows_params {
+    struct ggml_tensor src0;  // F32 input tensor [ne00, ne01, ne02, ne03]
+    struct ggml_tensor dst;   // F32 output tensor [1, ne01, ne02, ne03]
+};
+
+int entry_point(struct ggml_et_sum_rows_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+
+    const int64_t ne00 = src0->ne[0];  // Row length (to be summed)
+    const int64_t ne01 = src0->ne[1];
+    const int64_t ne02 = src0->ne[2];
+    const int64_t ne03 = src0->ne[3];
+
+    const size_t nb01 = src0->nb[1];
+    const size_t nb02 = src0->nb[2];
+    const size_t nb03 = src0->nb[3];
+
+    const size_t nb1 = dst->nb[1];
+    const size_t nb2 = dst->nb[2];
+    const size_t nb3 = dst->nb[3];
+
+    // Flatten rows across dimensions 1,2,3 and distribute across threads
+    const int64_t total_rows = ne01 * ne02 * ne03;
+
+    for (int64_t ir = thread_id; ir < total_rows; ir += num_threads) {
+        const int64_t i03 = ir / (ne02 * ne01);
+        const int64_t i02 = (ir - i03 * ne02 * ne01) / ne01;
+        const int64_t i01 = ir - i03 * ne02 * ne01 - i02 * ne01;
+
+        const float * src_row = (const float *) ((const char *) src0_data + i01 * nb01 + i02 * nb02 + i03 * nb03);
+        float *       dst_ptr = (float *) ((char *) dst_data + i01 * nb1 + i02 * nb2 + i03 * nb3);
+
+        // Vectorized 8-wide sum accumulation
+        float zero = 0.0f;
+        __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+        for (int32_t i0 = 0; i0 < (int32_t) ne00; i0 += 8) {
+            __asm__ volatile(
+                "flw.ps f11, %[x_vec]\n"
+                "fadd.ps f10, f10, f11\n"
+                :
+                : [x_vec] "m"(*(const float (*)[8]) & src_row[i0])
+                : "f10", "f11");
+        }
+
+        // Horizontal sum of 8 accumulated values in f10
+        float row_sum;
+        __asm__ __volatile__(
+            "fswizz.ps f1, f10, 0xB1 \n\t"
+            "fadd.ps   f2, f10, f1, rne \n\t"
+            "fswizz.ps f3, f2, 0x4E \n\t"
+            "fadd.ps   f4, f2, f3, rne \n\t"
+            "fmvz.x.ps t0, f4, 4 \n\t"
+            "fbcx.ps   f5, t0 \n\t"
+            "fadd.ps   %[vout], f4, f5, rne \n\t"
+            : [vout] "=f"(row_sum)::"t0", "f1", "f2", "f3", "f4", "f5");
+
+        atomic_store_f32(dst_ptr, row_sum);
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/tensor.h b/ggml/src/ggml-et/et-kernels/src/tensor.h
new file mode 100644 (file)
index 0000000..043a2a3
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/tensor.h
@@ -0,0 +1,897 @@
+#ifndef __TENSORS_H
+#define __TENSORS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__cplusplus) && (__cplusplus >= 201103L)
+#    include <cinttypes>
+#    if (__cplusplus < 202002L)
+#        include <cstdbool>
+#    endif
+#else
+#    include <inttypes.h>
+#    include <stdbool.h>
+#endif
+
+/*! \def QUANT_LAST_TRANS
+    \brief Tensor Quant instruction: Do not perform any more transformations.
+*/
+#define QUANT_LAST_TRANS 0
+
+/*! \def QUANT_INT32_TO_FP32
+    \brief Tensor Quant instruction: Convert all elements of A from 32-bit signed integer values to single-precision
+    floating-point values.
+*/
+#define QUANT_INT32_TO_FP32 1
+
+/*! \def QUANT_FP32_TO_INT32
+    \brief Tensor Quant instruction: Convert all elements of A from single-precision floating-point values to 32-
+    bit signed integer values.
+*/
+#define QUANT_FP32_TO_INT32 2
+
+/*! \def QUANT_RELU
+    \brief Tensor Quant instruction: Convert all negative INT32 values in A to 0
+*/
+#define QUANT_RELU 3
+
+/*! \def QUANT_INT32_ADD_ROW
+    \brief Tensor Quant instruction: Read the low-order COLS+1 32-bit signed integer values from an L1
+    scratchpad line, and add this vector to every row of the 32-bit signed integer
+    matrix A.
+*/
+#define QUANT_INT32_ADD_ROW 4
+
+/*! \def QUANT_INT32_ADD_COL
+    \brief Tensor Quant instruction: Read the low-order ROWS+1 32-bit signed integer values from an L1
+    scratchpad line, and add this vector to every column of the 32-bit signed
+    integer matrix A.
+*/
+#define QUANT_INT32_ADD_COL 5
+
+/*! \def QUANT_FP32_MUL_ROW
+    \brief Tensor Quant instruction: Read the low-order COLS+1 single-precision floating-point values from an
+    L1 scratchpad line, and multiply the single-precision elements of each row
+    of matrix A element-wise by this vector.
+*/
+#define QUANT_FP32_MUL_ROW 6
+
+/*! \def QUANT_FP32_MUL_COL
+    \brief Tensor Quant instruction: Read the low-order ROWS+1 single-precision floating-point values from an
+    L1 scratchpad line, and multiply the single-precision elements of each col-
+    umn of matrix A element-wise by this vector.
+*/
+#define QUANT_FP32_MUL_COL 7
+
+/*! \def QUANT_SATINT8
+    \brief Tensor Quant instruction: Clamp all 32-bit signed integer values in A to the range [-128, 127].
+    The values are written in bits 7:0 of each element, with bits 31:8 set to zero.
+*/
+#define QUANT_SATINT8 8
+
+/*! \def QUANT_SATUINT8
+    \brief Tensor Quant instruction: Clamp all 32-bit signed integer values in A to the range [0, 255]. The values
+    are written in bits 7:0 of each element, with bits 31:8 set to zero.
+*/
+#define QUANT_SATUINT8 9
+
+/*! \def QUANT_PACK_128B
+    \brief Tensor Quant instruction: Copy the low-order byte of the n-th 32-bit value in each row of A to the n-th
+    byte of the row.
+*/
+#define QUANT_PACK_128B 10
+
+/*! \def TENSOR_REDUCE_OP_FADD
+    \brief Tensor Reduce instruction: The result is the addition of the incoming single-precision floating-point data
+    and the single-precision floating-point values in the vector register file.
+*/
+#define TENSOR_REDUCE_OP_FADD 0
+
+// #define TENSOR_REDUCE_OP_FSUB 1 -- Not supported
+
+/*! \def TENSOR_REDUCE_OP_FMAX
+    \brief Tensor Reduce instruction: The result is the maximum of the incoming single-precision floating-point data
+and the single-precision floating-point values in the vector register file.
+*/
+#define TENSOR_REDUCE_OP_FMAX 2
+
+/*! \def TENSOR_REDUCE_OP_FMIN
+    \brief Tensor Reduce instruction: The result is the minimum of the incoming single-precision floating-point data
+and the single-precision floating-point values in the vector register file..
+*/
+#define TENSOR_REDUCE_OP_FMIN 3
+
+/*! \def TENSOR_REDUCE_OP_IADD
+    \brief Tensor Reduce instruction: The result is the addition of the incoming 32-bit integer data and the 32-bit inte-
+ger values in the vector register file.
+*/
+#define TENSOR_REDUCE_OP_IADD 4
+
+// #define TENSOR_REDUCE_OP_ISUB 5 -- Not supported
+
+/*! \def TENSOR_REDUCE_OP_IMAX
+    \brief Tensor Reduce instruction: The result is the maximum of the incoming 32-bit signed integer data and the
+32-bit signed integer values in the vector register file.
+*/
+#define TENSOR_REDUCE_OP_IMAX 6
+
+/*! \def TENSOR_REDUCE_OP_IMIN
+    \brief Tensor Reduce instruction: The result is the minimum of the incoming 32-bit signed integer data and the
+32-bit signed integer values in the vector register file.
+*/
+#define TENSOR_REDUCE_OP_IMIN 7
+
+/*! \def TENSOR_REDUCE_OP_FGET
+    \brief Tensor Reduce instruction get function to be performed
+*/
+#define TENSOR_REDUCE_OP_FGET 8
+
+/*! \def TENSOR_LOAD_WAIT_0
+    \brief Tensor load to L1 Scratchpad with ID = 0 is complete.
+*/
+#define TENSOR_LOAD_WAIT_0 0
+
+/*! \def TENSOR_LOAD_WAIT_1
+    \brief Tensor load to L1 Scratchpad with ID = 1 is complete.
+*/
+#define TENSOR_LOAD_WAIT_1 1
+
+/*! \def TENSOR_FMA_WAIT
+    \brief All previous tensor matrix multiplication instructions are complete.
+*/
+#define TENSOR_FMA_WAIT 7
+
+/*! \def TENSOR_STORE_WAIT
+    \brief All previous tensor store instructions are complete.
+*/
+#define TENSOR_STORE_WAIT 8
+
+/*! \def TENSOR_REDUCE_WAIT
+    \brief All previous tensor reduction instructions are complete
+*/
+#define TENSOR_REDUCE_WAIT 9
+
+/*! \def TENSOR_QUANT_WAIT
+    \brief TensorQuant is complete
+*/
+#define TENSOR_QUANT_WAIT 10
+
+// TensorFMA opcode values (tensor_fma CSR 0x801, bits 3:1)
+#define TENSOR_FMA_OP_FP32 0  // TensorFMA32:    FP32  x FP32  -> FP32
+#define TENSOR_FMA_OP_FP16 1  // TensorFMA16A32: FP16  x FP16  -> FP32
+// opcode 2 is reserved
+#define TENSOR_FMA_OP_INT8 3  // TensorIMA8A32:  INT8  x INT8  -> INT32
+
+// TensorLoad transformation values (tensor_load CSR 0x83F, bits 61:59)
+#define TENSOR_LOAD_PLAIN        0  // TensorLoad:             64B rows
+#define TENSOR_LOAD_INTERLEAVE8  1  // TensorLoadInterleave8:  for TensorIMA8A32 B
+#define TENSOR_LOAD_INTERLEAVE16 2  // TensorLoadInterleave16: for TensorFMA16A32 B
+// transformations 3-4 are reserved
+#define TENSOR_LOAD_TRANSPOSE8   5  // TensorLoadTranspose8:   8-bit transpose
+#define TENSOR_LOAD_TRANSPOSE16  6  // TensorLoadTranspose16:  16-bit transpose
+#define TENSOR_LOAD_TRANSPOSE32  7  // TensorLoadTranspose32:  32-bit transpose
+
+/*! \def TENSOR_ERROR_LOAD_TRANSFORM
+    \brief Define for tensor load transform error.
+*/
+#define TENSOR_ERROR_LOAD_TRANSFORM 1
+
+/*! \def TENSOR_ERROR_FCC_OVERFLOW
+    \brief Define for tensor fcc overflow error.
+*/
+#define TENSOR_ERROR_FCC_OVERFLOW 3
+
+/*! \def TENSOR_ERROR_SCP_DISABLED
+    \brief Define for tensor scp disabled error.
+*/
+#define TENSOR_ERROR_SCP_DISABLED 4
+
+/*! \def TENSOR_ERROR_LOCKSW
+    \brief Define for tensor locksw error.
+*/
+#define TENSOR_ERROR_LOCKSW 5
+
+/*! \def TENSOR_ERROR_TL1_FMA
+    \brief Define for L1 FMA error.
+*/
+#define TENSOR_ERROR_TL1_FMA 6
+
+/*! \def TENSOR_ERROR_MEM_FAULT
+    \brief Define for Memory fault error.
+*/
+#define TENSOR_ERROR_MEM_FAULT 7
+
+/*! \def TENSOR_ERROR_STORE_COOP
+    \brief Define for store coop error.
+*/
+#define TENSOR_ERROR_STORE_COOP 8
+
+/*! \def TENSOR_ERROR_REDUCE
+    \brief Define for tensor reduce error.
+*/
+#define TENSOR_ERROR_REDUCE 9
+
+/*! \struct et_tensor_load_l2scp_conf
+    \brief Tensor load from scp instruction configuration structure.
+*/
+typedef struct et_tensor_load_l2scp_conf {
+    bool     use_tmask;
+    uint64_t dst_start;
+    uint64_t addr;
+    uint64_t num_lines;
+    uint64_t stride;
+    uint64_t id;
+} et_tensor_load_l2scp_conf_t;
+
+/*! \enum reduce_transform_t
+    \brief enum transform mode for tensor reduce.
+*/
+typedef enum {
+    FADD = 0x0ULL,
+    FSUB = 0x1ULL,
+    FMAX = 0x2ULL,
+    FMIN = 0x3ULL,
+    IADD = 0x4ULL,
+    ISUB = 0x5ULL,
+    IMAX = 0x6ULL,
+    IMIN = 0x7ULL,
+    FGET = 0x8ULL
+} reduce_transform_t;
+
+/*! \struct et_tensor_load_conf
+    \brief Tensor load instruction configuration structure.
+*/
+typedef struct et_tensor_load_conf {
+    bool     use_tmask;
+    bool     use_coop;
+    bool     use_tenb;
+    uint64_t dst_start;
+    uint64_t transformation;
+    uint64_t rd_l2scp;
+    uint64_t addr;
+    uint64_t offset;
+    uint64_t num_lines;
+    uint64_t stride;
+    uint64_t id;
+} et_tensor_load_conf_t;
+
+/*! \fn inline void tensor_wait(long id)
+    \brief Tensor wait instruction, Tensor Wait can be used to stall execution until
+    a previously issued tensor instruction completes.
+    \param id tensor ID
+    \return none
+    \tensorops Implementation of tensor_wait api
+*/
+inline __attribute__((always_inline)) void tensor_wait(long id) {
+    __asm__ __volatile__(" csrw 0x830, %[id]\n" : : [id] "r"(id) : "memory");
+}
+
+/*! \fn inline void tensor_load (tensor_load *conf)
+    \brief Tensor load instruction, it loads data from memory (bypass-ing the L1 cache)
+    into the L1 scratchpad. Input parameter defines the configuration to tensor load.
+    \param use_tmask the tensor_mask register is used for this operation
+    \param use_coop the operation is a cooperative tensor load.
+    \param dst_start L1 Scratchpad starting cache line
+    \param transformation These bits, along with bit 52, decodes the type of tensor operation.
+    \param use_tenb This bit, along with transformation, decodes the type of tensor operation.
+    \param addr tensor load address
+    \param offset tensor load address offset
+    \param num_lines tensor load number of cache lines
+    \param stride tensor load stride value
+    \param id tensor load id
+    \return none
+    \tensorops Implementation of tensor_load api
+
+*/
+// 1. Load Matrix A segment (1 row x 16 cols) into SCP ID 0
+// dst_start 0 refers to the first line of L1 Scratchpad
+// tensor_load(false, false, 0, 0, 0,
+//             (uint64_t)(src0_data + m * K + kb), 0, 1, 0, 0);
+
+inline void __attribute__((always_inline)) tensor_load(bool     use_tmask,
+                                                       bool     use_coop,
+                                                       uint64_t dst_start,
+                                                       uint64_t transformation,
+                                                       uint64_t use_tenb,
+                                                       uint64_t addr,
+                                                       uint64_t offset,
+                                                       uint64_t num_lines,
+                                                       uint64_t stride,
+                                                       uint64_t id) {
+    // Address alignment depends on transformation type:
+    //   Interleave8, Transpose8  (1,5): 16B aligned, addr bits 47:4
+    //   Interleave16, Transpose16 (2,6): 32B aligned, addr bits 47:5
+    //   Load, Transpose32, LoadB  (0,7): 64B aligned, addr bits 47:6
+    uint64_t addr_mask = (transformation == 1 || transformation == 5) ? 0xFFFFFFFFFFF0ULL :
+                         (transformation == 2 || transformation == 6) ? 0xFFFFFFFFFFE0ULL :
+                                                                        0xFFFFFFFFFFC0ULL;
+    uint64_t csr_enc   = (((uint64_t) use_tmask & 1) << 63) | (((uint64_t) use_coop & 1) << 62) |
+                         ((transformation & 0x7) << 59) | ((dst_start & 0x3F) << 53) | ((use_tenb & 0x1) << 52) |
+                         ((addr & addr_mask)) | ((offset & 0x3) << 4) | ((num_lines & 0xF));
+
+    uint64_t x31_enc = (stride & 0xFFFFFFFFFFC0ULL) | (id & 0x1);
+
+    __asm__ __volatile__(
+        "mv x31, %[x31v]\n"
+        "csrw 0x83f, %[csrv]\n"
+        :
+        : [x31v] "r"(x31_enc), [csrv] "r"(csr_enc)
+        : "x31", "memory");
+}
+
+/*! \fn inline void et_tensor_load (et_tensor_load_conf_t *conf)
+    \brief Tensor load instruction, it loads data from memory (bypass-ing the L1 cache)
+    into the L1 scratchpad. Input parameter defines the configuration to tensor load.
+    \param conf tensor load configuration
+    \return none
+    \tensorops Implementation of et_tensor_load api
+*/
+inline void __attribute__((always_inline)) et_tensor_load(et_tensor_load_conf_t * conf) {
+    tensor_load(conf->use_tmask, conf->use_coop, conf->dst_start, conf->transformation, (uint64_t) conf->use_tenb,
+                conf->addr, conf->offset, conf->num_lines, conf->stride, conf->id);
+}
+
+/*! \fn inline void tensor_load_setup_b(bool use_coop, uint64_t addr, uint64_t num_lines, uint64_t stride, uint64_t id)
+    \brief Tensor load instruction setup
+    \param use_coop the operation is a cooperative tensor load.
+    \param addr tensor load address
+    \param num_lines tensor load number of cache lines
+    \param stride tensor load stride value
+    \param id tensor load id
+    \return none
+    \tensorops Implementation of tensor_load_setup_b api
+*/
+inline void __attribute__((always_inline)) tensor_load_setup_b(bool     use_coop,
+                                                               uint64_t addr,
+                                                               uint64_t num_lines,
+                                                               uint64_t stride,
+                                                               uint64_t id) {
+    uint64_t csr_enc =
+        (((uint64_t) use_coop & 1) << 62) | (0x1ULL << 52) | ((addr & 0xFFFFFFFFFFC0ULL)) | ((num_lines & 0xF));
+    uint64_t x31_enc = (stride & 0xFFFFFFFFFFC0ULL) | (id & 0x1);
+
+    __asm__ __volatile__(
+        "mv x31, %[x31v]\n"
+        "csrw 0x83f, %[csrv]\n"
+        :
+        : [x31v] "r"(x31_enc), [csrv] "r"(csr_enc)
+        : "x31", "memory");
+}
+
+/*! \fn inline void et_tensor_load_l2scp (et_tensor_load_l2scp_conf_t *conf)
+    \brief Tensor load l2scp loads data from memory (bypassing the L1 and L2 caches) into the L2 scratchpad.
+   \param conf tensor load configuration
+   \return none
+   \tensorops Implementation of et_tensor_load_l2scp api
+*/
+inline void __attribute__((always_inline)) et_tensor_load_l2scp(et_tensor_load_l2scp_conf_t * conf) {
+    uint64_t csr_enc =
+        (((((uint64_t) conf->use_tmask) & 1) << 63) | ((conf->dst_start & 0x1FFFCUL) << (48 - 2)) |
+         ((conf->dst_start & 0x3UL) << 4) | ((conf->addr & 0xFFFFFFFFFFC0UL)) | ((conf->num_lines & 0x0FUL)));
+    uint64_t x31_enc = (conf->stride & 0xFFFFFFFFFFC0ULL) | (conf->id & 0x1);
+
+    __asm__ __volatile__(
+        "mv x31, %[x31v]\n"
+        "csrw 0x85f, %[csrv]\n"
+        :
+        : [x31v] "r"(x31_enc), [csrv] "r"(csr_enc)
+        : "x31", "memory");
+}
+
+/*! \fn inline void tensor_store_scp(uint64_t entry_stride,
+                                     uint64_t start_scp_entry,
+                                     uint64_t Arows,
+                                     uint64_t addr,
+                                     uint64_t stride)
+   \brief Tensor Store writes a series of 64-byte blocks of data from the L1 scratchpad into memory.
+   A matrix X can have up to 16 rows, and each row can be up to 64B in size (the number of columns depends on the type of elements of X).
+   \param entry_stride Register stride
+   \param start_scp_entry Start register
+   \param Arows A matrix row size
+   \param addr Virtual Address
+   \param stride This value is the distance in bytes between consecutive tensor rows in memory
+   \return none
+   \tensorops Implementation of tensor_store_scp api
+*/
+inline void __attribute__((always_inline)) tensor_store_scp(uint64_t entry_stride,
+                                                            uint64_t start_scp_entry,
+                                                            uint64_t Arows,
+                                                            uint64_t addr,
+                                                            uint64_t stride) {
+    uint64_t csr_enc = ((entry_stride & 0x3) << 62) | ((start_scp_entry & 0x3F) << 56) | ((addr & 0xFFFFFFFFFFC0ULL)) |
+                       ((Arows & 0xF) << 51) | (((uint64_t) 1) << 48);
+    uint64_t x31_enc = (stride & 0xFFFFFFFFFFC0UL);
+
+    __asm__ __volatile__(
+        "mv x31, %[x31v]\n"
+        "csrw 0x87f, %[csrv]\n"
+        :
+        : [x31v] "r"(x31_enc), [csrv] "r"(csr_enc)
+        : "x31", "memory");
+}
+
+/*! \fn inline void tensor_store(uint64_t reg_stride,
+                                 uint64_t start_reg,
+                                 uint64_t cols,
+                                 uint64_t Arows,
+                                 uint64_t addr,
+                                 uint64_t coop_store,
+                                 uint64_t stride)
+   \brief The Tensor store instruction reads a tensor from the vector register files and writes it to memory,
+   bypassing the L1 data cache and the L2 cache. For the purposes of this instruction the tensor has ROWS+1 rows,
+   and each row is 16*SIZE+16 bytes in size.
+   \param reg_stride Register stride
+   \param start_reg start register address
+   \param cols  matrix row size.
+   \param Arows  matrix row size
+   \param addr Virtual Address
+   \param coop_store Number of minions to cooperate with
+   \param stride This value is the distance in bytes between consecutive tensor rows in memory
+   \return none
+   \tensorops Implementation of tensor_store api
+*/
+inline void __attribute__((always_inline)) tensor_store(uint64_t reg_stride,
+                                                        uint64_t start_reg,
+                                                        uint64_t cols,
+                                                        uint64_t Arows,
+                                                        uint64_t addr,
+                                                        uint64_t coop_store,
+                                                        uint64_t stride) {
+    uint64_t warl    = 0;
+    uint64_t csr_enc = ((reg_stride & 0x3) << 62) | ((start_reg & 0x1F) << 57) | ((cols & 0x3) << 55) |
+                       ((addr & 0xFFFFFFFFFFF0)) | ((Arows & 0xF) << 51) | ((coop_store & 0x3) << 49) | ((warl & 0xF));
+
+    uint64_t x31_enc = (stride & 0xFFFFFFFFFF0UL);
+
+    __asm__ __volatile__(
+        "mv x31, %[x31v]\n"
+        "csrw 0x87f, %[csrv]\n"
+        :
+        : [x31v] "r"(x31_enc), [csrv] "r"(csr_enc)
+        : "x31", "memory");
+}
+
+/*! \fn inline void tensor_fma(bool use_tmask,
+                               uint64_t b_num_col,
+                               uint64_t a_num_rows,
+                               uint64_t a_num_cols,
+                               uint64_t offset,
+                               bool tenc_loc,
+                               bool tenb_unsigned,
+                               bool tena_unsigned,
+                               bool tenb_loc,
+                               uint64_t scp_loc_b,
+                               uint64_t scp_loc_a,
+                               uint64_t opcode,
+                               bool first_pass)
+   \brief The Tensor FMA instruction multiplies two matrices A and B, optionally adds the resulting matrix
+   to a third matrix C, and writes the result back onto matrix C
+   \param use_tmask Use tensor_mask CSR to skip operations in an A row granularity.
+   \param b_num_col B matrix number of columns
+   \param a_num_rows A matrix number of rows
+   \param a_num_cols A matrix number of columns
+   \param offset A matrix starting column for the operation.
+   \param tenc_loc Location of matrix C (0 = L1 scratchpad, 1 = memory).
+   \param tenb_unsigned TenB is signed (0) or unsigned (1).
+   \param tena_unsigned TenA is signed (0) or unsigned (1).
+   \param tenb_loc Location of matrix B (0 = L1 scratchpad, 1 = memory).
+   \param scp_loc_b Starting L1 scratchpad cache line where matrix B is stored, ignored when xs[20] = 1.
+   \param scp_loc_a Starting L1 scratchpad cache line where matrix A is stored, ignored when xs[20] = 1.
+   \param opcode 0 = TensorFMA32 (F32xF32->F32), 1 = TensorFMA16A32 (F16xF16->F32), 3 = TensorIMA8A32 (I8xF8->I32).
+            Other opcodes are invalid.
+   \param first_pass if set to 0 then the initial value of TenC is added to the result
+   \return none
+   \tensorops Implementation of tensor_fma api
+*/
+inline void __attribute__((always_inline)) tensor_fma(bool     use_tmask,
+                                                      uint64_t b_num_col,
+                                                      uint64_t a_num_rows,
+                                                      uint64_t a_num_cols,
+                                                      uint64_t offset,
+                                                      bool     tenc_loc,
+                                                      bool     tenb_unsigned,
+                                                      bool     tena_unsigned,
+                                                      bool     tenb_loc,
+                                                      uint64_t scp_loc_b,
+                                                      uint64_t scp_loc_a,
+                                                      uint64_t opcode,
+                                                      bool     first_pass) {
+    uint64_t csr_enc = (((uint64_t) use_tmask & 1) << 63) | ((b_num_col & 0x3) << 55) | ((a_num_rows & 0xF) << 51) |
+                       ((a_num_cols & 0xF) << 47) | ((offset & 0xF) << 43) | (((uint64_t) tenc_loc & 1) << 23) |
+                       (((uint64_t) tena_unsigned & 1) << 22) | (((uint64_t) tenb_unsigned & 1) << 21) |
+                       (((uint64_t) tenb_loc & 1) << 20) | ((scp_loc_b & 0xFF) << 12) | ((scp_loc_a & 0xFF) << 4) |
+                       ((opcode & 0x7) << 1) | ((uint64_t) first_pass & 1);
+
+    __asm__ __volatile__("csrw 0x801, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) :);
+}
+
+/*! \fn inline uint32_t tensor_reduce_uint32(uint32_t value, uint64_t operation, uint64_t partnerID, uint64_t action)
+   \brief Tensor reduce allows a group of harts to communicate values held in floating-point registers to collectively calculate a reduction
+   function.
+   \param value Register stride
+   \param operation Function to be performed.
+   \param partnerID Receiver minionID.
+   \param action action value
+   \return uint32_t value after reduction
+   \tensorops Implementation of tensor_reduce_uint32 api
+*/
+inline uint32_t __attribute__((always_inline)) tensor_reduce_uint32(uint32_t value,
+                                                                    uint64_t operation,
+                                                                    uint64_t partnerID,
+                                                                    uint64_t action) {
+    uint64_t warl = 0;
+    uint32_t out;
+    uint64_t csr_enc = ((warl & 0x2) << 62) | ((0ULL & 0x1F) << 57) | ((warl & 0x1FFFFFFF) << 28) |
+                       ((operation & 0xF) << 24) | ((1ULL & 0xFF) << 16) | ((partnerID & 0x1FFF) << 3) |
+                       ((warl & 0x1) << 2) | ((action & 0x3));
+
+    __asm__ __volatile__(
+        "fmv.s.x     f0, %[value]\n"
+        "csrw 0x800, %[csr_enc]\n"
+        "fmv.x.s     %[out], f0\n"
+        : [out] "=r"(out)
+        : [csr_enc] "r"(csr_enc), [value] "r"(value)
+        : "f0");
+
+    return out;
+}
+
+/*! \fn inline float tensor_reduce_float(float freg, uint64_t operation, uint64_t num_reg, uint64_t partnerID, uint64_t action) {
+   \brief TensorReduce allows a group of harts to communicate values held in floating-point registers to collectively calculate a reduction
+   function.
+   \param freg Freg register stride
+   \param operation Function to be performed.
+   \param num_reg number of registers to use
+   \param partnerID Receiver minionID.
+   \param action action value
+   \return float value after reduction
+   \tensorops Implementation of tensor_reduce_float api
+*/
+inline float __attribute__((always_inline)) tensor_reduce_float(float    freg,
+                                                                uint64_t operation,
+                                                                uint64_t num_reg,
+                                                                uint64_t partnerID,
+                                                                uint64_t action) {
+    uint64_t warl = 0;
+    float    out;
+    uint64_t csr_enc = ((warl & 0x2) << 62) | ((0ULL & 0x1F) << 57) | ((warl & 0x1FFFFFFF) << 28) |
+                       ((operation & 0xF) << 24) | ((num_reg & 0xFF) << 16) | ((partnerID & 0x1FFF) << 3) |
+                       ((warl & 0x1) << 2) | ((action & 0x3));
+
+    __asm__ __volatile__(
+        "fmv.s   f0, %[freg]\n"
+        "csrw 0x800, %[csr_enc]\n"
+        "fmv.s   %[out], f0\n"
+        : [out] "=f"(out)
+        : [csr_enc] "r"(csr_enc), [freg] "f"(freg)
+        : "f0");
+
+    return out;
+}
+
+//#define tensor_reduce_float1(fval, operation, partnerID, action) do {
+//   uint64_t warl = 0;
+//   float out;
+//   uint64_t csr_enc = ((warl      & 0x2        ) << 62) |
+//                      ((0         & 0x1F       ) << 57) |
+//                      ((warl      & 0x1FFFFFFF ) << 28) |
+//                      ((operation & 0xF        ) << 24) |
+//                      ((1         & 0xFF       ) << 16) |
+//                      ((partnerID & 0x1FFF     ) << 3 ) |
+//                      ((warl      & 0x1        ) << 2 ) |
+//                      ((action    & 0x3        )      );
+//
+//   register float asm("f0") fval;
+//   __asm__ volatile (
+//         "csrw 0x800, %[csr_enc]"
+//         : "+r" (ftmp)
+//         : [csr_enc] "r" (csr_enc)
+//   );
+//} while (0)
+//
+//
+//inline float __attribute__((always_inline)) tensor_reduce_float(uint64_t fstart, uint64_t operation, uint64_t num_reg, uint64_t partnerID, uint64_t action) {
+//   uint64_t warl = 0;
+//   float out;
+//   uint64_t csr_enc = ((warl      & 0x2        ) << 62) |
+//                      ((fstart    & 0x1F       ) << 57) |
+//                      ((warl      & 0x1FFFFFFF ) << 28) |
+//                      ((operation & 0xF        ) << 24) |
+//                      ((num_reg   & 0xFF       ) << 16) |
+//                      ((partnerID & 0x1FFF     ) << 3 ) |
+//                      ((warl      & 0x1        ) << 2 ) |
+//                      ((action    & 0x3        )      );
+//
+//   __asm__ volatile (
+//         "csrw 0x800, %[csr_enc]\n"
+//         : /*empty*/
+//      : [csr_enc] "r" (csr_enc),
+//         : /*"f0", "f1", "f2", "f3", "f4",
+//           "f5", "f6", "f7", "f8", "f9",
+//           "f10", "f11", "f12", "f13", "f14",
+//           "f15", "f16", "f17", "f18", "f19",
+//           "f20", "f21", "f22", "f23", "f24",
+//           "f25", "f26", "f27", "f28", "f29",
+//           "f30", "f31"*/
+//   );
+//
+//   return out;
+//}
+
+/*! \fn inline void tensor_reduce(uint64_t start_reg, uint64_t operation, uint64_t num_reg, uint64_t partnerID, uint64_t action)
+   \brief The TensorReduce instruction allows up to 216 harts to collectively calculate a reduction function.
+   \param start_reg starting register
+   \param operation Function to be performed.
+   \param num_reg number of registers
+   \param partnerID Receiver minionID.
+   \param action action value
+   \return uint32_t value after reduction
+   \tensorops Implementation of tensor_reduce api
+*/
+
+inline void __attribute__((always_inline)) tensor_reduce(uint64_t start_reg,
+                                                         uint64_t operation,
+                                                         uint64_t num_reg,
+                                                         uint64_t partnerID,
+                                                         uint64_t action) {
+    uint64_t warl = 0;
+
+    uint64_t csr_enc = ((warl & 0x2) << 62) | ((start_reg & 0x1F) << 57) | ((warl & 0x1FFFFFFF) << 28) |
+                       ((operation & 0xF) << 24) | ((num_reg & 0xFF) << 16) | ((partnerID & 0x1FFF) << 3) |
+                       ((warl & 0x1) << 2) | ((action & 0x3));
+
+    __asm__ __volatile__("csrw 0x800, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) :);
+}
+
+/*! \fn inline void tensor_reduce_send(uint64_t start_reg, uint64_t num_reg, uint64_t partnerID)
+   \brief This function applies reduce instruction to function and then sends to partner minion.
+   \param start_reg starting register
+   \param num_reg number of registers
+   \param partnerID Receiver minionID.
+   \return none
+   \tensorops Implementation of tensor_reduce_send api
+*/
+inline void __attribute__((always_inline)) tensor_reduce_send(uint64_t start_reg,
+                                                              uint64_t num_reg,
+                                                              uint64_t partnerID) {
+    uint64_t warl = 0;
+    tensor_reduce(start_reg, warl, num_reg, partnerID, 0);
+}
+
+/*! \fn inline void tensor_reduce_recv(uint64_t start_reg, uint64_t operation, uint64_t num_reg, uint64_t partnerID)
+   \brief This function recieves reduce function from partner minion.
+   \param start_reg starting register
+   \param operation operation to be performed
+   \param num_reg number of registers
+   \param partnerID Receiver minionID.
+   \return none
+   \tensorops Implementation of tensor_reduce_recv api
+*/
+inline void __attribute__((always_inline)) tensor_reduce_recv(uint64_t start_reg,
+                                                              uint64_t operation,
+                                                              uint64_t num_reg,
+                                                              uint64_t partnerID) {
+    tensor_reduce(start_reg, operation, num_reg, partnerID, 1);
+}
+
+/*! \fn inline void tensor_reduce_auto(uint64_t start_reg, uint64_t operation, uint64_t num_reg, uint64_t tree_depth)
+   \brief The Tensor reduce instruction allows up to 216 harts to collectively calculate a reduction function.
+   \param start_reg starting register
+   \param operation operation to be performed
+   \param num_reg number of registers
+   \param tree_depth tree depth
+   \return none
+   \tensorops Implementation of tensor_reduce_auto api
+*/
+inline void __attribute__((always_inline)) tensor_reduce_auto(uint64_t start_reg,
+                                                              uint64_t operation,
+                                                              uint64_t num_reg,
+                                                              uint64_t tree_depth) {
+    tensor_reduce(start_reg, operation, num_reg, (0ULL << 4) | (tree_depth & 0xF), 3);
+}
+
+/*! \fn inline void tensor_broadcast(uint64_t start_reg, uint64_t operation, uint64_t num_reg, uint64_t tree_depth) {
+   \brief The Tensor broadcast instruction allows up to 216 harts to receive values held in the vector registers
+   of one of the harts in the group. The broadcast operation is performed in a binary-tree fashion, where the source
+   data is originally in the root node and the final result ends up in the leaf nodes.
+   \param start_reg Starting floating-point register
+   \param operation operation to be performed
+   \param num_reg Number of floating-point registers
+   \param tree_depth tree depth
+   \return none
+   \tensorops Implementation of tensor_broadcast api
+*/
+inline void __attribute__((always_inline)) tensor_broadcast(uint64_t start_reg,
+                                                            uint64_t operation,
+                                                            uint64_t num_reg,
+                                                            uint64_t tree_depth) {
+    tensor_reduce(start_reg, operation, num_reg, (0ULL << 4) | (tree_depth & 0xF), 2);
+}
+
+/*! \fn inline void tensor_reduce_autopair(uint64_t start_reg, uint64_t operation, uint64_t num_reg, uint64_t start_lvl, uint64_t end_lvl, uint64_t action) {
+   \brief This function is wrapper of Tensor Reduce (auto-pair variant) instruction.
+   \param start_reg Starting floating-point register
+   \param operation Function to be performed
+   \param num_reg Number of floating-point registers
+   \param start_lvl starting level value
+   \param end_lvl ending level value
+   \param action action value
+   \return none
+   \tensorops Implementation of tensor_reduce_autopair api
+
+*/
+inline void __attribute__((always_inline)) tensor_reduce_autopair(uint64_t start_reg,
+                                                                  uint64_t operation,
+                                                                  uint64_t num_reg,
+                                                                  uint64_t start_lvl,
+                                                                  uint64_t end_lvl,
+                                                                  uint64_t action) {
+    uint64_t partnerID;
+    // PRM-10 defines the partnerID field for Tensor Reduce (auto-pair variant) as following:
+    // [15:11] WARL(0)
+    // [10: 7] End level for autopair
+    // [ 6: 3] Start level for autopair
+    uint64_t warl = 0;
+    partnerID     = ((warl & 0xF) << 11) | ((end_lvl & 0xF) << 7) | ((start_lvl & 0xF) << 3);
+    // Operations encoding:
+    // 0000=fadd, 0001=fsub, 0010=fmax, 0011=fmin, 0100=iadd, 0101=isub, 0110=imax, 0111=imin, 1000=fget
+    //
+    // Action encoding:
+    // 00=send, 01=receive, 10=auto-pair broadcast derive from hartid,11=auto-pair reduce derive from hartid
+    tensor_reduce(start_reg, operation, num_reg, (partnerID >> 3), action);
+}
+
+/*! \fn inline void tensor_quant(uint64_t start_reg, uint64_t col, uint64_t row, uint64_t scp_loc, uint64_t transf9, uint64_t transf8, uint64_t transf7, uint64_t transf6, uint64_t transf5, uint64_t transf4, uint64_t transf3, uint64_t transf2, uint64_t transf1, uint64_t transf0 )
+   \brief Tensor quantization (TensorQuant) instructions are encoded as writes to the tensor_quant CSR. The TensorQuant
+   instruction performs a sequence of up to 10 transformations to a matrix A
+   \param start_reg Starting register
+   \param col A matrix number of columns.
+   \param row A matrix number of rows.
+   \param scp_loc L1 scratchpad cache line where the first vector is stored.
+   \param transf9 Transformation 9.
+   \param transf8 Transformation 8.
+   \param transf7 Transformation 7.
+   \param transf6 Transformation 6.
+   \param transf5 Transformation 5.
+   \param transf4 Transformation 4.
+   \param transf3 Transformation 3.
+   \param transf2 Transformation 2.
+   \param transf1 Transformation 1.
+   \param transf0 Transformation 0.
+   \return none
+   \tensorops Implementation of tensor_quant api
+*/
+inline void __attribute__((always_inline)) tensor_quant(uint64_t start_reg,
+                                                        uint64_t col,
+                                                        uint64_t row,
+                                                        uint64_t scp_loc,
+                                                        uint64_t transf9,
+                                                        uint64_t transf8,
+                                                        uint64_t transf7,
+                                                        uint64_t transf6,
+                                                        uint64_t transf5,
+                                                        uint64_t transf4,
+                                                        uint64_t transf3,
+                                                        uint64_t transf2,
+                                                        uint64_t transf1,
+                                                        uint64_t transf0) {
+    uint64_t csr_enc = ((start_reg & 0x1F) << 57) | ((col & 0x3) << 55) | ((row & 0xF) << 51) |
+                       ((scp_loc & 0x3F) << 45) | ((transf9 & 0xF) << 36) | ((transf8 & 0xF) << 32) |
+                       ((transf7 & 0xF) << 28) | ((transf6 & 0xF) << 24) | ((transf5 & 0xF) << 20) |
+                       ((transf4 & 0xF) << 16) | ((transf3 & 0xF) << 12) | ((transf2 & 0xF) << 8) |
+                       ((transf1 & 0xF) << 4) | ((transf0 & 0xF) << 0);
+
+    __asm__ __volatile__("csrw 0x806, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) :);
+}
+
+/*! \fn inline void tensor_mask(uint64_t zeros, uint64_t mask_bits)
+   \brief The TensorLoad, TensorFMA, and CacheOp instructions can operate under the
+   control of the tensor_mask CSR. The tensor_mask CSR contains one bit for each
+   of the destination lines that TensorLoad can potentially write into the scratchpad
+   \param zeros all zeros
+   \param mask_bits tensor bit mask
+   \return none
+   \tensorops Implementation of tensor_mask api
+*/
+inline void __attribute__((always_inline)) tensor_mask(uint64_t zeros, uint64_t mask_bits) {
+    uint64_t csr_enc = ((zeros & 0x000000000000) << 16) | (mask_bits & 0xFFFF);
+
+    __asm__ __volatile__("csrw 0x805, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) :);
+}
+
+/*! \fn inline void tensor_coop(uint64_t val)
+   \brief The tensor_coop instruction specifies which harts participate in cooperative tensor load operations. Only the first hart of each
+   selected Minion core participates in the cooperative operations, since the second hart cannot issue tensor load operations.
+   \param val value contains encoded coop id, minion and neigh mask
+   \return none
+   \tensorops Implementation of tensor_coop api
+*/
+inline void __attribute__((always_inline)) tensor_coop(uint64_t val) {
+    __asm__ __volatile__("csrw 0x804, %[val]\n" : : [val] "r"(val) :);
+}
+
+/*! \fn inline void convolution_ctrl(uint64_t row_start, uint64_t col_start)
+   \brief This function modifies the convolution control register.
+   This register encodes the location of a tensor inside a larger two-dimensional array.
+   \param row_start signed integer value specifying the row inside the array where the first row of the tensor resides
+   \param col_start signed integer value specifying the column inside the array where the first column of the tensor resides
+   \return none
+   \tensorops Implementation of convolution_ctrl api
+*/
+inline void __attribute__((always_inline)) convolution_ctrl(uint64_t row_start, uint64_t col_start) {
+    uint64_t csr_enc = ((row_start & 0xFFFF) << 32) | (col_start & 0xFFFF);
+
+    __asm__ __volatile__("csrw 0x803, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) :);
+}
+
+/*! \fn inline void convolution_size(uint64_t srow, uint64_t nrow, uint64_t scol, uint64_t ncol)
+   \brief This function modifies the convolution size register.
+   This register specifies the layout of a two-dimensional array used for convolutions.
+   \param srow integer value specifying the row inside the array where the first row of the tensor resides
+   \param nrow integer values specifying the number of rows of the array
+   \param scol integer value specifying the distance, in number of columns, between consecutive column accesses to the array during
+    convolution operations
+   \param ncol integer values specifying the number of columns of the array
+   \return none
+   \tensorops Implementation of convolution_size api
+*/
+inline void __attribute__((always_inline)) convolution_size(uint64_t srow,
+                                                            uint64_t nrow,
+                                                            uint64_t scol,
+                                                            uint64_t ncol) {
+    uint64_t csr_enc = ((srow & 0xFF) << 56) | ((nrow & 0xFFFF) << 32) | ((scol & 0xFF) << 24) | ((ncol & 0xFFFF));
+
+    __asm__ __volatile__("csrw 0x802, %[csr_enc]\n" : : [csr_enc] "r"(csr_enc) :);
+}
+
+/*! \fn inline unsigned get_tensor_error()
+   \brief This function returns tensor error register value.
+   The tensor_error register accrues errors that occur during the execution of tensor instructions and cache management operations. When the tensor coprocessor or the cache management coprocessor generates an exception, the exception is recorded in
+   the tensor_error register and execution does not trap. The tensor_error register is never cleared by the implementation. It is the
+   responsibility of the software to clear tensor_error
+   \return Tensor error value
+   \tensorops Implementation of get_tensor_error api
+*/
+inline unsigned long __attribute__((always_inline)) get_tensor_error() {
+    unsigned long error;
+
+    __asm__ __volatile__("csrr %0, 0x808" : "=r"(error));
+
+    return error;
+}
+
+/*! \fn inline uint64_t get_tensor_mask()
+   \brief This function returns tensor mask register value.
+   \return Tensor mask value
+   \tensorops Implementation of get_tensor_mask api
+*/
+inline uint64_t __attribute__((always_inline)) get_tensor_mask() {
+    uint64_t val;
+
+    __asm__ __volatile__("csrr %0, 0x805" : "=r"(val));
+
+    return val;
+}
+
+#define mask_set(msk, val)                                          \
+    do {                                                            \
+        __asm__ volatile("mov.m.x m" #msk ", zero, %0" ::"n"(val)); \
+    } while (0)
+
+#define flw_ps(fd, ptr)                                       \
+    do {                                                      \
+        __asm__ volatile("flw.ps f" #fd ", (%0)" ::"r"(ptr)); \
+    } while (0)
+
+#define fsw_ps(fd, ptr)                                                  \
+    do {                                                                 \
+        __asm__ volatile("fsw.ps f" #fd ", (%0)" ::"r"(ptr) : "memory"); \
+    } while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // ! __TENSORS_H

diff --git a/ggml/src/ggml-et/et-kernels/src/tri_f32.c b/ggml/src/ggml-et/et-kernels/src/tri_f32.c
new file mode 100644 (file)
index 0000000..e33e4a3
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/tri_f32.c
@@ -0,0 +1,244 @@
+//******************************************************************************
+// Tri F32 Kernel
+// Triangular masking: zero out elements outside the triangular region.
+//
+// tri_type (matches ggml_tri_type enum):
+//   0 = UPPER_DIAG:  keep where i0 >= i1
+//   1 = UPPER:       keep where i0 >  i1
+//   2 = LOWER_DIAG:  keep where i0 <= i1
+//   3 = LOWER:       keep where i0 <  i1
+//
+// Distribution: cache-line aligned chunks of the flat contiguous dst.
+// Each element is individually classified as keep or zero based on its
+// (i0, i1) coordinates. This avoids cache-line sharing between threads
+// when ne0 is not a multiple of 16.
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+#define TRI_TYPE_UPPER_DIAG 0
+#define TRI_TYPE_UPPER      1
+#define TRI_TYPE_LOWER_DIAG 2
+#define TRI_TYPE_LOWER      3
+
+struct ggml_et_tri_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+    int32_t            tri_type;
+};
+
+static inline int keep_element(int32_t tri_type, int64_t i0, int64_t i1) {
+    switch (tri_type) {
+        case TRI_TYPE_LOWER:
+            return i0 < i1;
+        case TRI_TYPE_LOWER_DIAG:
+            return i0 <= i1;
+        case TRI_TYPE_UPPER:
+            return i0 > i1;
+        case TRI_TYPE_UPPER_DIAG:
+            return i0 >= i1;
+        default:
+            return 0;
+    }
+}
+
+int entry_point(struct ggml_et_tri_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0     = &params->src0;
+    struct ggml_tensor * dst      = &params->dst;
+    int32_t              tri_type = params->tri_type;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    const int64_t ne0 = dst->ne[0];
+    const int64_t ne1 = dst->ne[1];
+    const int64_t ne2 = dst->ne[2];
+    const int64_t ne3 = dst->ne[3];
+
+    const size_t nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3];
+    const size_t nb1 = dst->nb[1], nb2 = dst->nb[2], nb3 = dst->nb[3];
+
+    const int64_t total_rows = ne1 * ne2 * ne3;
+
+    //==========================================================================
+    // Fast path: ne0 % 16 == 0 — rows are cache-line aligned, distribute rows
+    //==========================================================================
+    if (ne0 % 16 == 0) {
+        float zero = 0.0f;
+        __asm__ volatile("fbc.ps f10, %[z]\n" : : [z] "m"(zero) : "f10");
+
+        for (int64_t row = thread_id; row < total_rows; row += num_threads) {
+            const int64_t i1 = row % ne1;
+            const int64_t i2 = (row / ne1) % ne2;
+            const int64_t i3 = row / (ne1 * ne2);
+
+            const float * src_row = (const float *) ((const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03);
+            float *       dst_row = (float *) ((char *) dst_data + i1 * nb1 + i2 * nb2 + i3 * nb3);
+
+            int64_t keep_start, keep_end;
+            switch (tri_type) {
+                case TRI_TYPE_LOWER:
+                    keep_start = 0;
+                    keep_end   = i1;
+                    break;
+                case TRI_TYPE_LOWER_DIAG:
+                    keep_start = 0;
+                    keep_end   = i1 + 1;
+                    break;
+                case TRI_TYPE_UPPER:
+                    keep_start = i1 + 1;
+                    keep_end   = ne0;
+                    break;
+                case TRI_TYPE_UPPER_DIAG:
+                    keep_start = i1;
+                    keep_end   = ne0;
+                    break;
+                default:
+                    return -1;
+            }
+            if (keep_end > ne0) {
+                keep_end = ne0;
+            }
+
+            // Zero prefix [0, keep_start) — SIMD for aligned blocks, scalar tail
+            int64_t i0 = 0;
+            for (; i0 + 8 <= keep_start; i0 += 8) {
+                __asm__ volatile("fsw.ps f10, %[d]\n" : [d] "=m"(*(float (*)[8]) & dst_row[i0])::"f10");
+            }
+            for (; i0 < keep_start; i0++) {
+                dst_row[i0] = 0.0f;
+            }
+
+            // Copy kept region [keep_start, keep_end) — SIMD + scalar tail
+            for (; i0 + 8 <= keep_end; i0 += 8) {
+                __asm__ volatile(
+                    "flw.ps f11, %[s]\n"
+                    "fsw.ps f11, %[d]\n"
+                    : [d] "=m"(*(float (*)[8]) & dst_row[i0])
+                    : [s] "m"(*(const float (*)[8]) & src_row[i0])
+                    : "f11");
+            }
+            for (; i0 < keep_end; i0++) {
+                dst_row[i0] = src_row[i0];
+            }
+
+            // Zero suffix [keep_end, ne0) — SIMD + scalar tail
+            for (; i0 + 8 <= ne0; i0 += 8) {
+                __asm__ volatile("fsw.ps f10, %[d]\n" : [d] "=m"(*(float (*)[8]) & dst_row[i0])::"f10");
+            }
+            for (; i0 < ne0; i0++) {
+                dst_row[i0] = 0.0f;
+            }
+        }
+        return 0;
+    }
+
+    //==========================================================================
+    // Unaligned fallback: distribute by cache lines, scalar per element
+    //==========================================================================
+    {
+        const int64_t total_elements = ne0 * ne1 * ne2 * ne3;
+        const int64_t elems_per_cl   = 16;
+        const int64_t total_cl       = (total_elements + elems_per_cl - 1) / elems_per_cl;
+
+        const int64_t cl_per_thread = (total_cl + num_threads - 1) / num_threads;
+        const int64_t cl_start      = thread_id * cl_per_thread;
+        int64_t       cl_end        = cl_start + cl_per_thread;
+        if (cl_end > total_cl) {
+            cl_end = total_cl;
+        }
+        if (cl_start >= total_cl) {
+            return 0;
+        }
+
+        const int64_t es = cl_start * elems_per_cl;
+        int64_t       ee = cl_end * elems_per_cl;
+        if (ee > total_elements) {
+            ee = total_elements;
+        }
+
+        int64_t row_idx = es / ne0;
+        int64_t col     = es % ne0;
+
+        int64_t pos = es;
+        while (pos < ee) {
+            const int64_t i1 = row_idx % ne1;
+            const int64_t i2 = (row_idx / ne1) % ne2;
+            const int64_t i3 = row_idx / (ne1 * ne2);
+
+            const float * src_row = (const float *) ((const char *) src0_data + i1 * nb01 + i2 * nb02 + i3 * nb03);
+
+            int64_t row_remaining   = ne0 - col;
+            int64_t chunk_remaining = ee - pos;
+            int64_t n               = row_remaining < chunk_remaining ? row_remaining : chunk_remaining;
+
+            int64_t keep_start, keep_end;
+            switch (tri_type) {
+                case TRI_TYPE_LOWER:
+                    keep_start = 0;
+                    keep_end   = i1;
+                    break;
+                case TRI_TYPE_LOWER_DIAG:
+                    keep_start = 0;
+                    keep_end   = i1 + 1;
+                    break;
+                case TRI_TYPE_UPPER:
+                    keep_start = i1 + 1;
+                    keep_end   = ne0;
+                    break;
+                case TRI_TYPE_UPPER_DIAG:
+                    keep_start = i1;
+                    keep_end   = ne0;
+                    break;
+                default:
+                    return -1;
+            }
+            if (keep_end > ne0) {
+                keep_end = ne0;
+            }
+
+            int64_t end_col = col + n;
+            for (int64_t i0 = col; i0 < end_col; i0++) {
+                if (i0 >= keep_start && i0 < keep_end) {
+                    dst_data[pos + (i0 - col)] = src_row[i0];
+                } else {
+                    dst_data[pos + (i0 - col)] = 0.0f;
+                }
+            }
+
+            pos += n;
+            col = 0;
+            row_idx++;
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/uberkernel.c b/ggml/src/ggml-et/et-kernels/src/uberkernel.c
new file mode 100644 (file)
index 0000000..40d1cf9
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/uberkernel.c
@@ -0,0 +1,497 @@
+#include "ggml-et-uberkernel-common.h"
+#include "ggml-et-uberkernel-kernel-map.h"
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+struct ggml_et_glu_params;
+struct ggml_et_unary_params;
+struct ggml_et_rope_params;
+struct ggml_et_rms_norm_params;
+struct ggml_et_rms_norm_mul_params;
+struct ggml_et_softmax_params;
+struct ggml_et_set_rows_params;
+struct ggml_et_get_rows_params;
+struct ggml_et_cont_params;
+struct ggml_et_concat_params;
+struct ggml_et_cumsum_params;
+struct ggml_et_diag_params;
+struct ggml_et_fill_params;
+struct ggml_et_flash_attn_ext_params;
+struct ggml_et_gated_delta_net_params;
+struct ggml_et_group_norm_params;
+struct ggml_et_im2col_params;
+struct ggml_et_l2_norm_params;
+struct ggml_et_mul_mat_id_params;
+struct ggml_et_norm_params;
+struct ggml_et_pad_params;
+struct ggml_et_repeat_params;
+struct ggml_et_rwkv_wkv6_params;
+struct ggml_et_rwkv_wkv7_params;
+struct ggml_et_scale_params;
+struct ggml_et_set_params;
+struct ggml_et_solve_tri_params;
+struct ggml_et_sqr_params;
+struct ggml_et_ssm_conv_params;
+struct ggml_et_ssm_scan_params;
+struct ggml_et_sum_rows_params;
+struct ggml_et_tri_params;
+
+extern int el_map_f32_entry(struct ggml_et_binary_params *, void *);
+extern int glu_f32_entry(struct ggml_et_glu_params *, void *);
+extern int unary_f32_entry(struct ggml_et_unary_params *, void *);
+extern int rope_f32_entry(struct ggml_et_rope_params *, void *);
+extern int rms_norm_f32_entry(struct ggml_et_rms_norm_params *, void *);
+extern int rms_norm_mul_f32_entry(struct ggml_et_rms_norm_mul_params *, void *);
+extern int softmax_f32_entry(struct ggml_et_softmax_params *, void *);
+extern int set_rows_f32_entry(struct ggml_et_set_rows_params *, void *);
+extern int get_rows_f32_entry(struct ggml_et_get_rows_params *, void *);
+extern int cont_f32_entry(struct ggml_et_cont_params *, void *);
+extern int cont_f16_entry(struct ggml_et_cont_params *, void *);
+extern int cpy_f32_f16_entry(struct ggml_et_cont_params *, void *);
+extern int concat_f32_entry(struct ggml_et_concat_params *, void *);
+extern int cumsum_f32_entry(struct ggml_et_cumsum_params *, void *);
+extern int diag_f32_entry(struct ggml_et_diag_params *, void *);
+extern int fill_f32_entry(struct ggml_et_fill_params *, void *);
+extern int flash_attn_ext_f32_entry(struct ggml_et_flash_attn_ext_params *, void *);
+extern int flash_attn_ext_f16_me_entry(struct ggml_et_flash_attn_ext_params *, void *);
+extern int gated_delta_net_f32_entry(struct ggml_et_gated_delta_net_params *, void *);
+extern int group_norm_f32_entry(struct ggml_et_group_norm_params *, void *);
+extern int im2col_entry(struct ggml_et_im2col_params *, void *);
+extern int l2_norm_f32_entry(struct ggml_et_l2_norm_params *, void *);
+extern int mul_mat_id_f32_entry(struct ggml_et_mul_mat_id_params *, void *);
+extern int norm_f32_entry(struct ggml_et_norm_params *, void *);
+extern int pad_f32_entry(struct ggml_et_pad_params *, void *);
+extern int repeat_f32_entry(struct ggml_et_repeat_params *, void *);
+extern int rwkv_wkv6_f32_entry(struct ggml_et_rwkv_wkv6_params *, void *);
+extern int rwkv_wkv7_f32_entry(struct ggml_et_rwkv_wkv7_params *, void *);
+extern int scale_f32_entry(struct ggml_et_scale_params *, void *);
+extern int set_f32_entry(struct ggml_et_set_params *, void *);
+extern int solve_tri_f32_entry(struct ggml_et_solve_tri_params *, void *);
+extern int sqr_f32_entry(struct ggml_et_sqr_params *, void *);
+extern int ssm_conv_f32_entry(struct ggml_et_ssm_conv_params *, void *);
+extern int ssm_scan_f32_entry(struct ggml_et_ssm_scan_params *, void *);
+extern int sum_rows_f32_entry(struct ggml_et_sum_rows_params *, void *);
+extern int tri_f32_entry(struct ggml_et_tri_params *, void *);
+extern int mul_mat_f16_entry(struct ggml_et_binary_params *, void *);
+extern int mul_mat_f16_matrix_engine_entry(struct ggml_et_binary_params *, void *);
+extern int mul_mat_f32_entry(struct ggml_et_binary_params *, void *);
+extern int mul_mat_f32_matrix_engine_entry(struct ggml_et_binary_params *, void *);
+extern int mul_mat_Q8_0_entry(struct ggml_et_mm_q8_params *, void *);
+extern int mul_mat_Q4_0_entry(struct ggml_et_binary_params *, void *);
+
+static inline size_t tensor_bytes(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+struct uber_glu_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+    // trailing scalars omitted — not needed for eviction
+};
+
+struct uber_unary_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+};
+
+struct uber_rope_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor src2;
+    struct ggml_tensor dst;
+};
+
+struct uber_rms_norm_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+};
+
+struct uber_rms_norm_mul_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+struct uber_softmax_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor src2;
+    struct ggml_tensor dst;
+};
+
+struct uber_set_rows_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+struct uber_get_rows_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+struct uber_cont_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor dst;
+};
+
+// src0 + src1 + dst (no trailing scalars needed for eviction)
+struct uber_concat_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+struct uber_ssm_conv_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+struct uber_solve_tri_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor dst;
+};
+
+struct uber_mul_mat_id_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor src2;
+    struct ggml_tensor dst;
+};
+
+// flash_attn_ext: Q=src0, K=src1, V=src2, mask=src3, dst (mask optional)
+struct uber_flash_attn_ext_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor src2;
+    struct ggml_tensor mask;
+    struct ggml_tensor dst;
+};
+
+// ssm_scan: 7 source tensors + dst
+struct uber_ssm_scan_params {
+    struct ggml_tensor src0;
+    struct ggml_tensor src1;
+    struct ggml_tensor src2;
+    struct ggml_tensor src3;
+    struct ggml_tensor src4;
+    struct ggml_tensor src5;
+    struct ggml_tensor src6;
+    struct ggml_tensor dst;
+};
+
+// gated_delta_net: q,k,v,g,beta,state_in,dst
+struct uber_gated_delta_net_params {
+    struct ggml_tensor q;
+    struct ggml_tensor k;
+    struct ggml_tensor v;
+    struct ggml_tensor g;
+    struct ggml_tensor beta;
+    struct ggml_tensor state_in;
+    struct ggml_tensor dst;
+};
+
+static void copy_f32_to_f16_row(uint16_t * dst, const float * src, int64_t num_elements) {
+    for (int64_t i = 0; i < num_elements; i++) {
+        dst[i] = fp32_to_fp16(src[i]);
+    }
+}
+
+static void copy_f32_row(float * dst, const float * src, int64_t num_elements) {
+    for (int64_t i = 0; i < num_elements; i++) {
+        dst[i] = src[i];
+    }
+}
+
+static void evict_region_past_l2_local(const void * addr, size_t bytes) {
+    if (!addr || bytes == 0) {
+        return;
+    }
+
+    const uint64_t CL     = 64;
+    uint64_t       base   = (uint64_t) addr & ~(CL - 1);
+    uint64_t       end    = ((uint64_t) addr + bytes + CL - 1) & ~(CL - 1);
+    uint64_t       nlines = (end - base) / CL;
+    cache_ops_priv_evict_sw(0, /*to_L2*/ 3, 0, 0, CL);
+}
+
+int entry_point(struct ggml_et_uberkernel_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env || !params) {
+        return -1;
+    }
+
+    struct ggml_et_uberkernel_inst * insts       = (struct ggml_et_uberkernel_inst *) (uintptr_t) params->insts;
+    uint8_t *                        params_blob = (uint8_t *) (uintptr_t) params->params_blob;
+
+    if (!insts || !params_blob || params->inst_stride < sizeof(struct ggml_et_uberkernel_inst)) {
+        return -1;
+    }
+
+    for (uint32_t i = 0; i < params->num_insts; ++i) {
+        struct ggml_et_uberkernel_inst * inst =
+            (struct ggml_et_uberkernel_inst *) ((uint8_t *) insts + (i * params->inst_stride));
+        void * inst_params = params_blob + inst->params_offset;
+        int    rc          = -1;
+
+        et_barrier_global(32ULL);
+
+        switch (inst->kernel_id) {
+            case GGML_ET_UBERKERNEL_KERNEL_EL_MAP_F32:
+                {
+                    struct ggml_et_binary_params * p = (struct ggml_et_binary_params *) inst_params;
+                    rc                               = el_map_f32_entry(p, env);
+                    break;
+                }
+            // case GGML_ET_UBERKERNEL_KERNEL_UNARY_F32: {
+            //     // struct uber_unary_params *p = (struct uber_unary_params *) inst_params;
+            //     // et_barrier(ET_BARRIER_GLOBAL);
+            //     rc = unary_f32_entry((struct ggml_et_unary_params *) inst_params, env);
+            //     break;
+            // }
+            // case GGML_ET_UBERKERNEL_KERNEL_CPY_F32_F16: {
+            //     struct uber_unary_params *p = (struct uber_unary_params *) inst_params;
+            //     // evict_region_past_l2(p->src0.data, tensor_bytes(&p->src0));
+            //     rc = cpy_f32_f16_entry((struct ggml_et_cont_params *) inst_params, env);
+            //     break;
+            // }
+            // case GGML_ET_UBERKERNEL_KERNEL_GET_ROWS_F32: {
+            //     struct uber_get_rows_params *p = (struct uber_get_rows_params *) inst_params;
+            //     rc = get_rows_f32_entry((struct ggml_et_get_rows_params *) inst_params, env);
+            //     break;
+            // }
+            // case GGML_ET_UBERKERNEL_KERNEL_CONT_F32: {
+            //     struct uber_cont_params *p = (struct uber_cont_params *) inst_params;
+            //     // evict_region_past_l2_local(p->src0.data, tensor_bytes(&p->src0));
+            //     // evict_region_past_l2(p->dst.data, tensor_bytes(&p->dst));
+            //     rc = cont_f32_entry((struct ggml_et_cont_params *) inst_params, env);
+            //     break;
+            // }
+            case GGML_ET_UBERKERNEL_KERNEL_GLU_F32:
+                {
+                    rc = glu_f32_entry((struct ggml_et_glu_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_ROPE_F32:
+                {
+                    rc = rope_f32_entry((struct ggml_et_rope_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_RMS_NORM_F32:
+                {
+                    // struct ggml_et_rms_norm_params *p = (struct ggml_et_rms_norm_params *) inst_params;
+                    // evict_region_past_l2(p->src0.data, tensor_bytes(&p->src0));
+                    rc = rms_norm_f32_entry((struct ggml_et_rms_norm_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_RMS_NORM_MUL_F32:
+                {
+                    struct uber_rms_norm_mul_params * p = (struct uber_rms_norm_mul_params *) inst_params;
+                    evict_region_past_l2(p->src0.data, tensor_bytes(&p->src0));
+                    evict_region_past_l2(p->src1.data, tensor_bytes(&p->src1));
+                    rc = rms_norm_mul_f32_entry((struct ggml_et_rms_norm_mul_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_SOFTMAX_F32:
+                {
+                    rc = softmax_f32_entry((struct ggml_et_softmax_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_SET_ROWS_F32:
+                {
+                    rc = set_rows_f32_entry((struct ggml_et_set_rows_params *) inst_params, env);
+                    break;
+                }
+
+            // Single-source ops (src0 → dst)
+            case GGML_ET_UBERKERNEL_KERNEL_SQR_F32:
+                {
+                    rc = sqr_f32_entry((struct ggml_et_sqr_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_SCALE_F32:
+                {
+                    rc = scale_f32_entry((struct ggml_et_scale_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_SUM_ROWS_F32:
+                {
+                    rc = sum_rows_f32_entry((struct ggml_et_sum_rows_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_CUMSUM_F32:
+                {
+                    rc = cumsum_f32_entry((struct ggml_et_cumsum_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_NORM_F32:
+                {
+                    rc = norm_f32_entry((struct ggml_et_norm_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_L2_NORM_F32:
+                {
+                    rc = l2_norm_f32_entry((struct ggml_et_l2_norm_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_GROUP_NORM_F32:
+                {
+                    rc = group_norm_f32_entry((struct ggml_et_group_norm_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_REPEAT_F32:
+                {
+                    rc = repeat_f32_entry((struct ggml_et_repeat_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_DIAG_F32:
+                {
+                    rc = diag_f32_entry((struct ggml_et_diag_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_TRI_F32:
+                {
+                    rc = tri_f32_entry((struct ggml_et_tri_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_PAD_F32:
+                {
+                    rc = pad_f32_entry((struct ggml_et_pad_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_CONT_F16:
+                {
+                    rc = cont_f16_entry((struct ggml_et_cont_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_FILL_F32:
+                {
+                    rc = fill_f32_entry((struct ggml_et_fill_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_SET_F32:
+                {
+                    rc = set_f32_entry((struct ggml_et_set_params *) inst_params, env);
+                    break;
+                }
+
+            // Two-source ops
+            case GGML_ET_UBERKERNEL_KERNEL_CONCAT_F32:
+                {
+                    rc = concat_f32_entry((struct ggml_et_concat_params *) inst_params, env);
+                    break;
+                }
+            // case GGML_ET_UBERKERNEL_KERNEL_SSM_CONV_F32: {
+            //     rc = ssm_conv_f32_entry((struct ggml_et_ssm_conv_params *) inst_params, env);
+            //     break;
+            // }
+            case GGML_ET_UBERKERNEL_KERNEL_SOLVE_TRI_F32:
+                {
+                    rc = solve_tri_f32_entry((struct ggml_et_solve_tri_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_IM2COL:
+                {
+                    rc = im2col_entry((struct ggml_et_im2col_params *) inst_params, env);
+                    break;
+                }
+
+            // Three-source ops
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_ID_F32:
+                {
+                    rc = mul_mat_id_f32_entry((struct ggml_et_mul_mat_id_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_FLASH_ATTN_EXT_F32:
+                {
+                    rc = flash_attn_ext_f32_entry((struct ggml_et_flash_attn_ext_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_FLASH_ATTN_EXT_F16_ME:
+                {
+                    rc = flash_attn_ext_f16_me_entry((struct ggml_et_flash_attn_ext_params *) inst_params, env);
+                    break;
+                }
+
+            case GGML_ET_UBERKERNEL_KERNEL_GATED_DELTA_NET_F32:
+                {
+                    rc = gated_delta_net_f32_entry((struct ggml_et_gated_delta_net_params *) inst_params, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_SSM_SCAN_F32:
+                {
+                    rc = ssm_scan_f32_entry((struct ggml_et_ssm_scan_params *) inst_params, env);
+                    break;
+                }
+            // rwkv: raw float* params, no ggml_tensor fields to evict via
+            case GGML_ET_UBERKERNEL_KERNEL_RWKV_WKV6_F32:
+                {
+                    rc = rwkv_wkv6_f32_entry((struct ggml_et_rwkv_wkv6_params *) inst_params, env);
+                    break;
+                }
+
+            case GGML_ET_UBERKERNEL_KERNEL_RWKV_WKV7_F32:
+                {
+                    rc = rwkv_wkv7_f32_entry((struct ggml_et_rwkv_wkv7_params *) inst_params, env);
+                    break;
+                }
+
+            // MUL_MAT: evict src1 (activations); src0=weights is
+            //  read-only so never stale from a prior uberkernel op
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_F16:
+                {
+                    struct ggml_et_binary_params * p = (struct ggml_et_binary_params *) inst_params;
+                    rc                               = mul_mat_f16_entry(p, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_F16_MATRIX_ENGINE:
+                {
+                    struct ggml_et_binary_params * p = (struct ggml_et_binary_params *) inst_params;
+                    rc                               = mul_mat_f16_matrix_engine_entry(p, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_F32:
+                {
+                    struct ggml_et_binary_params * p = (struct ggml_et_binary_params *) inst_params;
+                    rc                               = mul_mat_f32_entry(p, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_F32_MATRIX_ENGINE:
+                {
+                    struct ggml_et_binary_params * p = (struct ggml_et_binary_params *) inst_params;
+                    rc                               = mul_mat_f32_matrix_engine_entry(p, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_Q8_0:
+                {
+                    struct ggml_et_mm_q8_params * p = (struct ggml_et_mm_q8_params *) inst_params;
+                    // evict_region_past_l2(p->src0.data, tensor_bytes(&p->src0));
+                    rc                              = mul_mat_Q8_0_entry(p, env);
+                    break;
+                }
+            case GGML_ET_UBERKERNEL_KERNEL_MUL_MAT_Q4_0:
+                {
+                    struct ggml_et_binary_params * p = (struct ggml_et_binary_params *) inst_params;
+                    rc                               = mul_mat_Q4_0_entry(p, env);
+                    break;
+                }
+
+            default:
+                return -1;
+        }
+
+        if (rc != 0) {
+            return rc;
+        }
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/et-kernels/src/unary_f32.c b/ggml/src/ggml-et/et-kernels/src/unary_f32.c
new file mode 100644 (file)
index 0000000..42282c0
--- /dev/null
+++ b/ggml/src/ggml-et/et-kernels/src/unary_f32.c
@@ -0,0 +1,705 @@
+//******************************************************************************
+// Unary F32 Kernel
+// Element-wise unary operations: dst[i] = f(src0[i])
+// All ops vectorized using 8-wide ET SIMD (fexp.ps, frcp.ps, flog.ps, etc.)
+//
+// Supports: ABS, SGN, NEG, STEP, TANH, ELU, RELU, SIGMOID, GELU, GELU_QUICK,
+//           SILU, HARDSWISH, HARDSIGMOID, EXP, EXPM1, SOFTPLUS, GELU_ERF
+//******************************************************************************
+
+#include "ggml_tensor.h"
+#include "math_fp.h"
+#include "platform.h"
+
+#include <stdint.h>
+
+// Unary kernel parameters structure
+struct ggml_et_unary_params {
+    struct ggml_tensor src0;      // F32 input tensor
+    struct ggml_tensor dst;       // F32 output tensor
+    int32_t            unary_op;  // ggml_unary_op enum value
+};
+
+//******************************************************************************
+// Vectorized 8-wide block operations
+// All process exactly 8 floats per call using ET vector instructions.
+// ne0 is guaranteed % 16 == 0, so the inner loop always calls with i0 += 8.
+//******************************************************************************
+
+// NEG: dst = -x  (zero - x)
+static inline void vec_neg(float * dst, const float * src, int32_t n) {
+    float zero = 0.0f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "fbc.ps  f10, %[z]\n"
+            "flw.ps  f11, %[x]\n"
+            "fsub.ps f12, f10, f11\n"
+            "fsw.ps  f12, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero)
+            : "f10", "f11", "f12");
+    }
+}
+
+// ABS: dst = |x|  (negate negative values: abs = x * sgn, or max(x, -x))
+// Uses: negate then fmax.ps
+static inline void vec_abs(float * dst, const float * src, int32_t n) {
+    float zero = 0.0f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "fbc.ps  f10, %[z]\n"
+            "flw.ps  f11, %[x]\n"
+            "fsub.ps f12, f10, f11\n"  // f12 = -x
+            "fmax.ps f13, f11, f12\n"  // f13 = max(x, -x) = |x|
+            "fsw.ps  f13, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero)
+            : "f10", "f11", "f12", "f13");
+    }
+}
+
+// RELU: dst = max(0, x)
+static inline void vec_relu(float * dst, const float * src, int32_t n) {
+    float zero = 0.0f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "fbc.ps  f10, %[z]\n"
+            "flw.ps  f11, %[x]\n"
+            "fmax.ps f12, f10, f11\n"  // max(0, x)
+            "fsw.ps  f12, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero)
+            : "f10", "f11", "f12");
+    }
+}
+
+// STEP: dst = x > 0 ? 1 : 0  (clamp to [0,1] via max then min-ish, or use sign bit)
+// Trick: relu(x) then frcp gives inf for 0 and finite for >0, but simpler:
+// step(x) = min(1, relu(x) * huge) ... too fragile.  Scalar is fine for step/sgn.
+static inline void vec_step(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        dst[i] = (src[i] > 0.0f) ? 1.0f : 0.0f;
+    }
+}
+
+// SGN: dst = sign(x) = x>0 ? 1 : (x<0 ? -1 : 0)
+static inline void vec_sgn(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        dst[i] = (src[i] > 0.0f) ? 1.0f : ((src[i] < 0.0f) ? -1.0f : 0.0f);
+    }
+}
+
+// EXP: dst = exp(x)
+// fexp.ps computes 2^x, so feed x * log2(e)
+static inline void vec_exp(float * dst, const float * src, int32_t n) {
+    float log2e = 1.4426950408889634f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f11, %[l2e]\n"
+            "fmul.ps f12, f10, f11\n"  // x * log2(e)
+            "fexp.ps f13, f12\n"       // 2^(x*log2e) = exp(x)
+            "fsw.ps  f13, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [l2e] "m"(log2e)
+            : "f10", "f11", "f12", "f13");
+    }
+}
+
+// EXPM1: dst = exp(x) - 1
+static inline void vec_expm1(float * dst, const float * src, int32_t n) {
+    float log2e = 1.4426950408889634f;
+    float one   = 1.0f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f11, %[l2e]\n"
+            "fbc.ps  f14, %[one]\n"
+            "fmul.ps f12, f10, f11\n"  // x * log2(e)
+            "fexp.ps f13, f12\n"       // exp(x)
+            "fsub.ps f13, f13, f14\n"  // exp(x) - 1
+            "fsw.ps  f13, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [l2e] "m"(log2e), [one] "m"(one)
+            : "f10", "f11", "f12", "f13", "f14");
+    }
+}
+
+// SIGMOID: dst = 1 / (1 + exp(-x))
+// Same pattern as SwiGLU: exp(-x) via fexp.ps, then frcp.ps
+static inline void vec_sigmoid(float * dst, const float * src, int32_t n) {
+    float zero  = 0.0f;
+    float one   = 1.0f;
+    float log2e = 1.4426950408889634f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[z]\n"
+            "fbc.ps  f21, %[one]\n"
+            "fbc.ps  f22, %[l2e]\n"
+            "fsub.ps f12, f20, f10\n"  // -x
+            "fmul.ps f13, f12, f22\n"  // -x * log2(e)
+            "fexp.ps f14, f13\n"       // exp(-x)
+            "fadd.ps f15, f14, f21\n"  // 1 + exp(-x)
+            "frcp.ps f16, f15\n"       // 1 / (1 + exp(-x))
+            "fsw.ps  f16, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero), [one] "m"(one), [l2e] "m"(log2e)
+            : "f10", "f12", "f13", "f14", "f15", "f16", "f20", "f21", "f22");
+    }
+}
+
+// TANH: dst = (exp(2x) - 1) / (exp(2x) + 1)
+// Rewrite as: 1 - 2/(exp(2x) + 1) to use frcp.ps
+// Or equivalently: 2*sigmoid(2x) - 1
+static inline void vec_tanh(float * dst, const float * src, int32_t n) {
+    float one       = 1.0f;
+    float two       = 2.0f;
+    float two_log2e = 2.8853900817779268f;  // 2 * log2(e)
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[one]\n"
+            "fbc.ps  f21, %[two]\n"
+            "fbc.ps  f22, %[tl2e]\n"
+            // exp(2x) via fexp.ps: feed 2x * log2(e)
+            "fmul.ps f12, f10, f22\n"  // 2x * log2(e)
+            "fexp.ps f13, f12\n"       // exp(2x)
+            "fadd.ps f14, f13, f20\n"  // exp(2x) + 1
+            "frcp.ps f15, f14\n"       // 1 / (exp(2x) + 1)
+            "fmul.ps f16, f21, f15\n"  // 2 / (exp(2x) + 1)
+            "fsub.ps f17, f20, f16\n"  // 1 - 2/(exp(2x)+1) = tanh(x)
+            "fsw.ps  f17, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [one] "m"(one), [two] "m"(two), [tl2e] "m"(two_log2e)
+            : "f10", "f12", "f13", "f14", "f15", "f16", "f17", "f20", "f21", "f22");
+    }
+}
+
+// SILU: dst = x / (1 + exp(-x)) = x * sigmoid(x)
+// Copied from SwiGLU pattern but without the gate multiply
+static inline void vec_silu(float * dst, const float * src, int32_t n) {
+    float zero  = 0.0f;
+    float one   = 1.0f;
+    float log2e = 1.4426950408889634f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[z]\n"
+            "fbc.ps  f21, %[one]\n"
+            "fbc.ps  f22, %[l2e]\n"
+            "fsub.ps f12, f20, f10\n"  // -x
+            "fmul.ps f13, f12, f22\n"  // -x * log2(e)
+            "fexp.ps f14, f13\n"       // exp(-x)
+            "fadd.ps f15, f14, f21\n"  // 1 + exp(-x)
+            "frcp.ps f16, f15\n"       // 1 / (1 + exp(-x))
+            "fmul.ps f17, f10, f16\n"  // x * sigmoid(x)
+            "fsw.ps  f17, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero), [one] "m"(one), [l2e] "m"(log2e)
+            : "f10", "f12", "f13", "f14", "f15", "f16", "f17", "f20", "f21", "f22");
+    }
+}
+
+// ELU: dst = x > 0 ? x : exp(x) - 1
+// Vector: compute exp(x)-1 for all lanes, then fmax(x, exp(x)-1)
+// Works because for x>0: x > exp(x)-1 is not always true...
+// Actually for x>0, exp(x)-1 > x (since exp(x) > x+1 for x>0).
+// So fmax won't work. Use: compute both, blend via comparison.
+// Simpler: exp(x)-1 for all, then for x>0 overwrite with x.
+// Without per-lane masking, do scalar for ELU.
+static inline void vec_elu(float * dst, const float * src, int32_t n) {
+    float log2e = 1.4426950408889634f;
+    float one   = 1.0f;
+    // Compute exp(x)-1 vectorized, then fixup positive elements
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f11, %[l2e]\n"
+            "fbc.ps  f14, %[one]\n"
+            "fmul.ps f12, f10, f11\n"  // x * log2(e)
+            "fexp.ps f13, f12\n"       // exp(x)
+            "fsub.ps f13, f13, f14\n"  // exp(x) - 1
+            "fsw.ps  f13, %[r]\n"      // store exp(x)-1
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [l2e] "m"(log2e), [one] "m"(one)
+            : "f10", "f11", "f12", "f13", "f14");
+        // Fixup: for x > 0, dst = x
+        for (int32_t j = 0; j < 8 && (i + j) < n; j++) {
+            if (src[i + j] > 0.0f) {
+                dst[i + j] = src[i + j];
+            }
+        }
+    }
+}
+
+// GELU: 0.5*x*(1 + tanh(sqrt(2/pi) * x * (1 + 0.044715*x^2)))
+// Reformulated as: x * (1 - 1/(exp(2z)+1)) where z = sqrt(2/pi)*x*(1+0.044715*x^2)
+// NaN-safe: avoids inf*0.  Copied from GeGLU block pattern.
+static inline void vec_gelu(float * dst, const float * src, int32_t n) {
+    float one       = 1.0f;
+    float half      = 0.5f;
+    float coef_a    = 0.044715f;
+    float sqrt2pi   = 0.79788456080286535587989211986876f;
+    float two_log2e = 2.8853900817779268f;  // 2 * log2(e)
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[one]\n"
+            "fbc.ps  f21, %[half]\n"
+            "fbc.ps  f22, %[coef]\n"
+            "fbc.ps  f23, %[s2pi]\n"
+            "fbc.ps  f24, %[tl2e]\n"
+            // inner = 1 + 0.044715 * x^2
+            "fmul.ps f12, f10, f10\n"        // x^2
+            "fmadd.ps f13, f22, f12, f20\n"  // 1 + 0.044715*x^2
+            // z = sqrt(2/pi) * x * inner
+            "fmul.ps f14, f23, f10\n"  // sqrt(2/pi) * x
+            "fmul.ps f14, f14, f13\n"  // z
+            // exp(2z) via fexp.ps
+            "fmul.ps f15, f14, f24\n"  // 2z * log2(e)
+            "fexp.ps f15, f15\n"       // exp(2z)
+            // gelu(x) = 0.5 * x * (1 + tanh(z))
+            //         = 0.5 * x * (1 + 1 - 2/(exp(2z)+1))
+            //         = x * (1 - 1/(exp(2z)+1))  ... wait, that's tanh-based
+            // Actually: 0.5*x*(1 + tanh) = 0.5*x*(1 + 1 - 2/(e2z+1)) = x*(1 - 1/(e2z+1))
+            // Hmm: tanh = (e2z-1)/(e2z+1) = 1 - 2/(e2z+1)
+            // So 0.5*(1+tanh) = 0.5*(2 - 2/(e2z+1)) = 1 - 1/(e2z+1)
+            // gelu = x * (1 - 1/(e2z+1))  -- matches GeGLU pattern exactly
+            "fadd.ps f16, f15, f20\n"  // exp(2z) + 1
+            "frcp.ps f16, f16\n"       // 1/(exp(2z) + 1)
+            "fsub.ps f16, f20, f16\n"  // 1 - 1/(exp(2z)+1) = sigmoid(2z)
+            "fmul.ps f17, f10, f16\n"  // x * sigmoid(2z) = gelu(x)
+            "fsw.ps  f17, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [one] "m"(one), [half] "m"(half), [coef] "m"(coef_a),
+              [s2pi] "m"(sqrt2pi), [tl2e] "m"(two_log2e)
+            : "f10", "f12", "f13", "f14", "f15", "f16", "f17", "f20", "f21", "f22", "f23", "f24");
+    }
+}
+
+// GELU_QUICK: x * sigmoid(1.702 * x) = x / (1 + exp(-1.702*x))
+static inline void vec_gelu_quick(float * dst, const float * src, int32_t n) {
+    float one            = 1.0f;
+    // -1.702 * log2(e) precomputed
+    float neg_coef_log2e = -1.702f * 1.4426950408889634f;  // ~ -2.4542
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[one]\n"
+            "fbc.ps  f21, %[ncl2e]\n"
+            // exp(-1.702*x): feed -1.702*x*log2(e) = x * (-1.702*log2(e))
+            "fmul.ps f12, f10, f21\n"  // x * (-1.702*log2(e))
+            "fexp.ps f13, f12\n"       // exp(-1.702*x)
+            "fadd.ps f14, f13, f20\n"  // 1 + exp(-1.702*x)
+            "frcp.ps f15, f14\n"       // sigmoid(1.702*x)
+            "fmul.ps f16, f10, f15\n"  // x * sigmoid(1.702*x)
+            "fsw.ps  f16, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [one] "m"(one), [ncl2e] "m"(neg_coef_log2e)
+            : "f10", "f12", "f13", "f14", "f15", "f16", "f20", "f21");
+    }
+}
+
+// GELU_ERF: 0.5 * x * (1 + erf(x / sqrt(2)))
+// erf approximation (Abramowitz & Stegun) is hard to vectorize cleanly, keep scalar
+// but use et_expf for the exp(-z^2) part
+static inline void vec_gelu_erf(float * dst, const float * src, int32_t n) {
+    const float SQRT_2_INV = 0.70710678118654752440084436210484f;
+    for (int32_t i = 0; i < n; i++) {
+        float x  = src[i];
+        float z  = x * SQRT_2_INV;
+        float az = z < 0.0f ? -z : z;
+
+        float t  = et_fdiv(1.0f, 1.0f + 0.3275911f * az);
+        float t2 = t * t;
+        float t3 = t2 * t;
+        float t4 = t3 * t;
+        float t5 = t4 * t;
+
+        float poly = 0.254829592f * t - 0.284496736f * t2 + 1.421413741f * t3 - 1.453152027f * t4 + 1.061405429f * t5;
+
+        float erf_pos = 1.0f - poly * et_expf(-(az * az));
+        float erf_val = (z < 0.0f) ? -erf_pos : erf_pos;
+        dst[i]        = 0.5f * x * (1.0f + erf_val);
+    }
+}
+
+// HARDSIGMOID: min(1, max(0, (x + 3) / 6))
+// Vector: compute (x+3)/6 via frcp, then clamp with fmax(0) and fmin(1)
+static inline void vec_hardsigmoid(float * dst, const float * src, int32_t n) {
+    float zero  = 0.0f;
+    float one   = 1.0f;
+    float three = 3.0f;
+    float inv6  = 0.16666666666666666f;  // 1/6
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[z]\n"
+            "fbc.ps  f21, %[one]\n"
+            "fbc.ps  f22, %[thr]\n"
+            "fbc.ps  f23, %[inv]\n"
+            "fadd.ps f12, f10, f22\n"  // x + 3
+            "fmul.ps f13, f12, f23\n"  // (x + 3) / 6
+            "fmax.ps f14, f13, f20\n"  // max(0, ...)
+            "fmin.ps f15, f14, f21\n"  // min(1, ...)
+            "fsw.ps  f15, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero), [one] "m"(one), [thr] "m"(three), [inv] "m"(inv6)
+            : "f10", "f12", "f13", "f14", "f15", "f20", "f21", "f22", "f23");
+    }
+}
+
+// HARDSWISH: x * hardsigmoid(x) = x * min(1, max(0, (x+3)/6))
+static inline void vec_hardswish(float * dst, const float * src, int32_t n) {
+    float zero  = 0.0f;
+    float one   = 1.0f;
+    float three = 3.0f;
+    float inv6  = 0.16666666666666666f;
+    for (int32_t i = 0; i < n; i += 8) {
+        __asm__ volatile(
+            "flw.ps  f10, %[x]\n"
+            "fbc.ps  f20, %[z]\n"
+            "fbc.ps  f21, %[one]\n"
+            "fbc.ps  f22, %[thr]\n"
+            "fbc.ps  f23, %[inv]\n"
+            "fadd.ps f12, f10, f22\n"  // x + 3
+            "fmul.ps f13, f12, f23\n"  // (x + 3) / 6
+            "fmax.ps f14, f13, f20\n"  // max(0, ...)
+            "fmin.ps f15, f14, f21\n"  // min(1, ...)
+            "fmul.ps f16, f10, f15\n"  // x * hardsigmoid(x)
+            "fsw.ps  f16, %[r]\n"
+            : [r] "=m"(*(float (*)[8]) & dst[i])
+            : [x] "m"(*(const float (*)[8]) & src[i]), [z] "m"(zero), [one] "m"(one), [thr] "m"(three), [inv] "m"(inv6)
+            : "f10", "f12", "f13", "f14", "f15", "f16", "f20", "f21", "f22", "f23");
+    }
+}
+
+// FLOOR: largest integer <= x
+static inline void vec_floor(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        float x = src[i];
+        float t = (float) (int32_t) x;
+        dst[i]  = (t > x) ? t - 1.0f : t;
+    }
+}
+
+// CEIL: smallest integer >= x
+static inline void vec_ceil(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        float x = src[i];
+        float t = (float) (int32_t) x;
+        dst[i]  = (t < x) ? t + 1.0f : t;
+    }
+}
+
+// TRUNC: round towards zero
+static inline void vec_trunc(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        dst[i] = (float) (int32_t) src[i];
+    }
+}
+
+// ROUND: round to nearest, ties to even (banker's rounding)
+static inline void vec_round(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        float x    = src[i];
+        float t    = (float) (int32_t) x;
+        float diff = x - t;
+        if (diff > 0.5f || (diff == 0.5f && ((int32_t) t & 1))) {
+            t += 1.0f;
+        } else if (diff < -0.5f || (diff == -0.5f && ((int32_t) t & 1))) {
+            t -= 1.0f;
+        }
+        dst[i] = t;
+    }
+}
+
+// SOFTPLUS: log(1 + exp(x))
+// For large x (>20), softplus(x) ~ x.  For moderate x, use fexp + flog.
+// Scalar fallback since flog.ps computes log2, need conversion, and overflow guard
+static inline void vec_softplus(float * dst, const float * src, int32_t n) {
+    for (int32_t i = 0; i < n; i++) {
+        float x = src[i];
+        dst[i]  = (x > 20.0f) ? x : et_logf(1.0f + et_expf(x));
+    }
+}
+
+static inline size_t tensor_bytes(const struct ggml_tensor * t) {
+    return (size_t) t->ne[0] * t->ne[1] * t->ne[2] * t->ne[3] * t->nb[0];
+}
+
+//******************************************************************************
+// Main entry point
+//******************************************************************************
+
+int entry_point(struct ggml_et_unary_params * params, void * env) {
+    kernel_environment_t * kernel_env = (kernel_environment_t *) env;
+
+    if (!kernel_env) {
+        return -1;
+    }
+
+    int thread_id   = get_relative_thread_id(kernel_env->shire_mask);
+    int num_threads = get_num_threads(kernel_env->shire_mask);
+
+    if (thread_id < 0) {
+        return 0;
+    }
+
+    if (params == 0 || ((uint64_t) params & 0x7) != 0) {
+        return -1;
+    }
+
+    struct ggml_tensor * src0 = &params->src0;
+    struct ggml_tensor * dst  = &params->dst;
+
+    // evict_region_past_l2(&params->unary_op, sizeof(int32_t));
+    // WAIT_CACHEOPS;
+    // FENCE;
+
+    int32_t unary_op = params->unary_op;
+
+    if (src0->type != GGML_TYPE_F32 || dst->type != GGML_TYPE_F32) {
+        return -1;
+    }
+
+    float * src0_data = (float *) src0->data;
+    float * dst_data  = (float *) dst->data;
+
+    if (!src0_data || !dst_data) {
+        return -1;
+    }
+
+    // evict_region_past_l2(src0_data, tensor_bytes(src0));
+    // evict_region_past_l2(dst_data, tensor_bytes(dst));
+    // WAIT_CACHEOPS;
+    // FENCE;
+    // et_barrier(ET_BARRIER_GLOBAL);
+
+    // Tensor layout: src and dst are F32 with at least dim-0 contiguity
+    //   - nb[0] == sizeof(float) (rows are dense; SIMD loads stay legal)
+    //   - nb[1], nb[2], nb[3] may all be arbitrary strides for 4D views
+    //
+    // We walk rows independently and decompose row index r into (i1,i2,i3),
+    // computing per-row byte offsets via nb[1..3] of each tensor.
+    const int64_t nc             = dst->ne[0];  // row width (logical)
+    const int64_t ne1            = dst->ne[1];
+    const int64_t ne2            = dst->ne[2];
+    const int64_t nr             = ne1 * ne2 * dst->ne[3];  // total rows
+    const int64_t total_elements = nr * nc;
+    const size_t  s_nb1 = src0->nb[1], s_nb2 = src0->nb[2], s_nb3 = src0->nb[3];
+    const size_t  d_nb1 = dst->nb[1], d_nb2 = dst->nb[2], d_nb3 = dst->nb[3];
+
+    // evict_region_past_l2(src0_data, tensor_bytes(src0));
+    // evict_region_past_l2(dst_data, tensor_bytes(dst));
+    // FENCE;
+    // WAIT_CACHEOPS;
+    // et_barrier(ET_BARRIER_GLOBAL);
+    const int64_t elements_per_cacheline = 16;  // 64 bytes / 4 bytes per float
+    const int64_t total_cachelines       = (total_elements + elements_per_cacheline - 1) / elements_per_cacheline;
+
+    const int64_t cl_per_thread = (total_cachelines + num_threads - 1) / num_threads;
+    const int64_t cl_start      = thread_id * cl_per_thread;
+    int64_t       cl_end        = cl_start + cl_per_thread;
+    if (cl_end > total_cachelines) {
+        cl_end = total_cachelines;
+    }
+
+    if (cl_start >= total_cachelines) {
+        return 0;
+    }
+
+    const int64_t elem_start = cl_start * elements_per_cacheline;
+    int64_t       elem_end   = cl_end * elements_per_cacheline;
+    if (elem_end > total_elements) {
+        elem_end = total_elements;
+    }
+
+    // Fast path: tensor is fully contiguous (no view), walk it as a flat array.
+    // This preserves perf for the common case and avoids the per-row dispatch loop.
+    const size_t row_bytes = (size_t) nc * sizeof(float);
+    // evict_region_past_l2((src0_data + elem_start), row_bytes);
+    // // evict_region_past_l2((dst_data + elem_start), row_bytes);
+    // FENCE;
+    // WAIT_CACHEOPS;
+    // et_barrier(ET_BARRIER_GLOBAL);
+
+    const int is_flat = s_nb1 == row_bytes && s_nb2 == s_nb1 * (size_t) ne1 && s_nb3 == s_nb2 * (size_t) ne2 &&
+                        d_nb1 == row_bytes && d_nb2 == d_nb1 * (size_t) ne1 && d_nb3 == d_nb2 * (size_t) ne2;
+
+    if (is_flat) {
+        float *       src_ptr = src0_data + elem_start;
+        // evict_region_past_l2(src_ptr, 1024);
+        float *       dst_ptr = dst_data + elem_start;
+        const int32_t count   = (int32_t) (elem_end - elem_start);
+        switch (unary_op) {
+            case GGML_UNARY_OP_NEG:
+                vec_neg(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_ABS:
+                vec_abs(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SGN:
+                vec_sgn(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_STEP:
+                vec_step(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_RELU:
+                vec_relu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_EXP:
+                vec_exp(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_EXPM1:
+                vec_expm1(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SIGMOID:
+                vec_sigmoid(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_TANH:
+                vec_tanh(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SILU:
+                vec_silu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_ELU:
+                vec_elu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_GELU:
+                vec_gelu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_GELU_QUICK:
+                vec_gelu_quick(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_GELU_ERF:
+                vec_gelu_erf(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_HARDSWISH:
+                vec_hardswish(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_HARDSIGMOID:
+                vec_hardsigmoid(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SOFTPLUS:
+                vec_softplus(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_FLOOR:
+                vec_floor(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_CEIL:
+                vec_ceil(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_ROUND:
+                vec_round(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_TRUNC:
+                vec_trunc(dst_ptr, src_ptr, count);
+                break;
+            default:
+                return -1;
+        }
+        return 0;
+    }
+
+    // Slow path: arbitrary 4D-strided view. Walk the assigned element range
+    // row-by-row, clipping each segment to a row boundary so we never cross
+    // nb[1]. For each row index r, decompose into (i1,i2,i3) and add the
+    // corresponding nb[*] byte offsets to the base pointers.
+    int64_t e = elem_start;
+    while (e < elem_end) {
+        int64_t row  = e / nc;
+        int64_t col  = e % nc;
+        int64_t take = nc - col;
+        if (take > elem_end - e) {
+            take = elem_end - e;
+        }
+
+        // Decompose row into (i3,i2,i1) using row-major linearization
+        const int64_t i1 = row % ne1;
+        const int64_t r2 = row / ne1;
+        const int64_t i2 = r2 % ne2;
+        const int64_t i3 = r2 / ne2;
+
+        float *       src_ptr = (float *) ((char *) src0_data + i3 * s_nb3 + i2 * s_nb2 + i1 * s_nb1) + col;
+        float *       dst_ptr = (float *) ((char *) dst_data + i3 * d_nb3 + i2 * d_nb2 + i1 * d_nb1) + col;
+        const int32_t count   = (int32_t) take;
+
+        // evict_region_past_l2(src_ptr, 1024);
+        // FENCE;
+        // et_barrier(ET_BARRIER_GLOBAL);
+
+        switch (unary_op) {
+            case GGML_UNARY_OP_NEG:
+                vec_neg(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_ABS:
+                vec_abs(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SGN:
+                vec_sgn(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_STEP:
+                vec_step(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_RELU:
+                vec_relu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_EXP:
+                vec_exp(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_EXPM1:
+                vec_expm1(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SIGMOID:
+                vec_sigmoid(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_TANH:
+                vec_tanh(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SILU:
+                vec_silu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_ELU:
+                vec_elu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_GELU:
+                vec_gelu(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_GELU_QUICK:
+                vec_gelu_quick(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_GELU_ERF:
+                vec_gelu_erf(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_HARDSWISH:
+                vec_hardswish(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_HARDSIGMOID:
+                vec_hardsigmoid(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_SOFTPLUS:
+                vec_softplus(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_FLOOR:
+                vec_floor(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_CEIL:
+                vec_ceil(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_ROUND:
+                vec_round(dst_ptr, src_ptr, count);
+                break;
+            case GGML_UNARY_OP_TRUNC:
+                vec_trunc(dst_ptr, src_ptr, count);
+                break;
+            default:
+                return -1;
+        }
+
+        e += take;
+    }
+
+    return 0;
+}

diff --git a/ggml/src/ggml-et/ggml-et-common.h b/ggml/src/ggml-et/ggml-et-common.h
new file mode 100644 (file)
index 0000000..a4132ee
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-common.h
@@ -0,0 +1,86 @@
+#pragma once
+
+#include "ggml-backend-impl.h"
+#include "ggml-et-uberkernel-common.h"
+
+#include <device-layer/IDeviceLayer.h>
+#include <runtime/IProfiler.h>
+#include <runtime/IRuntime.h>
+
+#include <cstdint>
+#include <fstream>
+#include <string>
+#include <unordered_map>
+#include <vector>
+
+std::shared_ptr<rt::IRuntime> ggml_et_runtime();
+
+struct ggml_backend_et_buffer_type_context {
+    int         devidx;
+    std::string name;
+};
+
+struct ggml_backend_et_buffer_context {
+    int          devidx;
+    void *       data;  // Device memory pointer
+    size_t       size;
+    rt::DeviceId rtid;
+};
+
+struct ggml_backend_et_context {
+    int devidx;
+};
+
+struct ggml_backend_et_device_context;
+
+// One slot in the uberkernel ring. The host vectors back the H2D copy and
+// must outlive the upload; the device buffers feed the kernel that consumes
+// them. pending_event lets us know when both have drained so the slot can
+// be recycled.
+struct ggml_backend_et_uberkernel_slot {
+    std::vector<ggml_et_uberkernel_inst> insts;
+    std::vector<std::byte>               params_blob;
+
+    std::byte * device_insts           = nullptr;
+    std::byte * device_params          = nullptr;
+    size_t      device_insts_capacity  = 0;
+    size_t      device_params_capacity = 0;
+
+    rt::EventId pending_event{};
+    bool        has_pending = false;
+};
+
+struct ggml_backend_et_uberkernel_context {
+    bool     failed     = false;
+    uint64_t shire_mask = 0;
+
+    // Ring of slots. We accumulate into slots[current_slot]; on segment
+    // commit we fire the H2D + launch and rotate to the next slot,
+    // waiting on its previous launch only if it hasn't drained yet.
+    static constexpr size_t         SLOT_COUNT = 4;
+    ggml_backend_et_uberkernel_slot slots[SLOT_COUNT];
+    size_t                          current_slot = 0;
+};
+
+struct ggml_backend_et_device_context {
+    int                        devidx;
+    rt::DeviceId               rtid;
+    std::string                name;
+    std::string                desc;
+    size_t                     total_mem;
+    ggml_backend_buffer_type_t buftype;
+
+    // Kernel management - default stream for ordered execution on this device
+    rt::StreamId                                  default_stream;
+    std::unordered_map<std::string, rt::KernelId> loaded_kernels;
+
+    // trace buffer - for printing support
+    std::byte * trace_buffer;
+
+    bool                               uberkernel_enabled = false;
+    ggml_backend_et_uberkernel_context uberkernel;
+};
+
+struct ggml_backend_et_reg_ctx {
+    std::vector<ggml_backend_dev_t> devices;
+};

diff --git a/ggml/src/ggml-et/ggml-et-cpu-compare.cpp b/ggml/src/ggml-et/ggml-et-cpu-compare.cpp
new file mode 100644 (file)
index 0000000..b37f6d2
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-cpu-compare.cpp
@@ -0,0 +1,497 @@
+#include "ggml-et-cpu-compare.h"
+
+#include "ggml-cpu/ggml-cpu-impl.h"
+#include "ggml-cpu/ops.h"
+
+#include <algorithm>
+#include <cmath>
+#include <cstdlib>
+#include <cstring>
+
+bool ggml_et_cpu_compare_init_pre(ggml_et_cpu_compare_ctx * ctx, const ggml_tensor * node, ggml_op op) {
+    if (!ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for CPU compare init\n");
+        return false;
+    }
+
+    // Clear context
+    memset(ctx, 0, sizeof(*ctx));
+
+    // Calculate actual buffer sizes - use backend buffer size for accurate copy
+    auto get_tensor_buffer_size = [](const ggml_tensor * tensor) -> size_t {
+        if (!tensor) {
+            return 0;
+        }
+
+        if (tensor->buffer) {
+            // Get actual backend buffer size
+            size_t buffer_size = ggml_backend_buffer_get_size(tensor->buffer);
+
+            // Use the full buffer size to avoid any truncation issues
+            return buffer_size;
+        } else {
+            // Fallback to logical size if no buffer
+            return ggml_nbytes(tensor);
+        }
+    };
+
+    ctx->src0_size = get_tensor_buffer_size(node->src[0]);
+    ctx->src1_size = get_tensor_buffer_size(node->src[1]);
+    ctx->src2_size = get_tensor_buffer_size(node->src[2]);
+    ctx->dst_size  = get_tensor_buffer_size(node);
+
+    // Allocate CPU buffers for all tensors
+    if (ctx->src0_size > 0) {
+        ctx->cpu_src0_data = malloc(ctx->src0_size);
+        if (!ctx->cpu_src0_data) {
+            GGML_LOG_ERROR("ET: Failed to allocate CPU src0 buffer\n");
+            goto cleanup;
+        }
+    }
+
+    if (ctx->src1_size > 0) {
+        ctx->cpu_src1_data = malloc(ctx->src1_size);
+        if (!ctx->cpu_src1_data) {
+            GGML_LOG_ERROR("ET: Failed to allocate CPU src1 buffer\n");
+            goto cleanup;
+        }
+    }
+
+    if (ctx->src2_size > 0) {
+        ctx->cpu_src2_data = malloc(ctx->src2_size);
+        if (!ctx->cpu_src2_data) {
+            GGML_LOG_ERROR("ET: Failed to allocate CPU src2 buffer\n");
+            goto cleanup;
+        }
+    }
+
+    ctx->cpu_dst_data = malloc(ctx->dst_size);
+    if (!ctx->cpu_dst_data) {
+        GGML_LOG_ERROR("ET: Failed to allocate CPU dst buffer\n");
+        goto cleanup;
+    }
+
+    ctx->et_dst_data = malloc(ctx->dst_size);
+    if (!ctx->et_dst_data) {
+        GGML_LOG_ERROR("ET: Failed to allocate ET dst buffer\n");
+        goto cleanup;
+    }
+
+    // Copy data from ET device buffers to CPU host buffers
+    if (ctx->src0_size > 0) {
+        // Copy logical tensor size - ggml_backend_tensor_get handles stride layout internally
+        size_t logical_size = ggml_nbytes(node->src[0]);
+        ggml_backend_tensor_get(node->src[0], ctx->cpu_src0_data, 0, logical_size);
+    }
+    if (ctx->src1_size > 0) {
+        size_t logical_size = ggml_nbytes(node->src[1]);
+        ggml_backend_tensor_get(node->src[1], ctx->cpu_src1_data, 0, logical_size);
+    }
+    if (ctx->src2_size > 0) {
+        size_t logical_size = ggml_nbytes(node->src[2]);
+        ggml_backend_tensor_get(node->src[2], ctx->cpu_src2_data, 0, logical_size);
+    }
+
+    // Copy destination data from device (for operations like SET_ROWS that modify existing data)
+    // Most ops create new tensors so this is unused, but SET_ROWS requires existing dst data
+    {
+        size_t logical_size = ggml_nbytes(node);
+        ggml_backend_tensor_get(node, ctx->cpu_dst_data, 0, logical_size);
+    }
+
+    // Create CPU backend for reference computation
+    GGML_LOG_DEBUG("ET: Creating CPU backend for reference computation\n");
+    ctx->cpu_backend = ggml_backend_cpu_init();
+    if (!ctx->cpu_backend) {
+        GGML_LOG_ERROR("ET: Failed to create CPU backend\n");
+        goto cleanup;
+    }
+
+    // Create GGML context for CPU tensors
+    GGML_LOG_DEBUG("ET: Creating GGML context for CPU computation\n");
+    ggml_init_params ctx_params;
+    ctx_params.mem_size   = ggml_tensor_overhead() * 4 + ggml_graph_overhead();  // up to 4 tensors + graph
+    ctx_params.mem_buffer = nullptr;
+    ctx_params.no_alloc   = true;                                                // We'll manage data ourselves
+    ctx->ggml_ctx         = ggml_init(ctx_params);
+    if (!ctx->ggml_ctx) {
+        GGML_LOG_ERROR("ET: Failed to create GGML context\n");
+        goto cleanup;
+    }
+
+    // Create CPU tensors with proper context
+    if (node->src[0]) {
+        ctx->cpu_src0 = ggml_new_tensor(ctx->ggml_ctx, node->src[0]->type, GGML_MAX_DIMS, node->src[0]->ne);
+        if (!ctx->cpu_src0) {
+            GGML_LOG_ERROR("ET: Failed to create CPU src0 tensor\n");
+            goto cleanup;
+        }
+        ctx->cpu_src0->data = ctx->cpu_src0_data;
+        // Copy stride array (nb) for correct memory layout
+        memcpy(ctx->cpu_src0->nb, node->src[0]->nb, sizeof(node->src[0]->nb));
+        // Copy op_params if present
+        memcpy(ctx->cpu_src0->op_params, node->src[0]->op_params, sizeof(node->src[0]->op_params));
+    }
+
+    if (node->src[1]) {
+        ctx->cpu_src1 = ggml_new_tensor(ctx->ggml_ctx, node->src[1]->type, GGML_MAX_DIMS, node->src[1]->ne);
+        if (!ctx->cpu_src1) {
+            GGML_LOG_ERROR("ET: Failed to create CPU src1 tensor\n");
+            goto cleanup;
+        }
+        ctx->cpu_src1->data = ctx->cpu_src1_data;
+        // Copy stride array (nb) for correct memory layout
+        memcpy(ctx->cpu_src1->nb, node->src[1]->nb, sizeof(node->src[1]->nb));
+        // Copy op_params if present
+        memcpy(ctx->cpu_src1->op_params, node->src[1]->op_params, sizeof(node->src[1]->op_params));
+    }
+
+    if (node->src[2]) {
+        ctx->cpu_src2 = ggml_new_tensor(ctx->ggml_ctx, node->src[2]->type, GGML_MAX_DIMS, node->src[2]->ne);
+        if (!ctx->cpu_src2) {
+            GGML_LOG_ERROR("ET: Failed to create CPU src2 tensor\n");
+            goto cleanup;
+        }
+        ctx->cpu_src2->data = ctx->cpu_src2_data;
+        // Copy stride array (nb) for correct memory layout
+        memcpy(ctx->cpu_src2->nb, node->src[2]->nb, sizeof(node->src[2]->nb));
+        // Copy op_params if present
+        memcpy(ctx->cpu_src2->op_params, node->src[2]->op_params, sizeof(node->src[2]->op_params));
+    }
+
+    return true;
+
+cleanup:
+    ggml_et_cpu_compare_free(ctx);
+    return false;
+}
+
+bool ggml_et_cpu_compare_compute_and_check(ggml_et_cpu_compare_ctx *          ctx,
+                                           const ggml_tensor *                node,
+                                           const ggml_et_cpu_compare_config * config) {
+    if (!ctx || !ctx->cpu_backend || !ctx->ggml_ctx || !node || !config) {
+        GGML_LOG_ERROR("ET: Invalid parameters for CPU compute and check\n");
+        return false;
+    }
+
+    // Create operation-specific CPU destination tensor based on the node's operation
+    ggml_op op = node->op;
+    switch (op) {
+        case GGML_OP_MUL:
+            ctx->cpu_dst = ggml_mul(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1);
+            break;
+        case GGML_OP_ADD:
+            ctx->cpu_dst = ggml_add(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1);
+            break;
+        case GGML_OP_MUL_MAT:
+            ctx->cpu_dst = ggml_mul_mat(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1);
+            break;
+        case GGML_OP_MUL_MAT_ID:
+            // MUL_MAT_ID: Mixture of Experts matrix multiplication
+            // src0 (as): expert weight matrices [K, M, n_expert]
+            // src1 (b):  activations [K, n_expert_used, batch]
+            // src2 (ids): expert selection indices [n_expert_used, batch]
+            ctx->cpu_dst = ggml_mul_mat_id(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1, ctx->cpu_src2);
+            break;
+        case GGML_OP_ROPE:
+            {
+                const int32_t * op_params  = (const int32_t *) node->op_params;
+                const int32_t   n_dims     = op_params[1];
+                const int32_t   mode       = op_params[2];
+                const int32_t   n_ctx_orig = op_params[4];
+                const float     freq_base  = *((const float *) (op_params + 5));
+                const float     freq_scale = *((const float *) (op_params + 6));
+                const float     ext_factor = *((const float *) (op_params + 7));
+                const float     attn_factor = *((const float *) (op_params + 8));
+                const float     beta_fast  = *((const float *) (op_params + 9));
+                const float     beta_slow  = *((const float *) (op_params + 10));
+
+                if (mode & GGML_ROPE_TYPE_MROPE) {
+                    int sections[GGML_MROPE_SECTIONS];
+                    memcpy(sections, op_params + 11, sizeof(sections));
+                    ctx->cpu_dst = ggml_rope_multi(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1, ctx->cpu_src2,
+                                                   n_dims, sections, mode, n_ctx_orig, freq_base, freq_scale,
+                                                   ext_factor, attn_factor, beta_fast, beta_slow);
+                } else {
+                    ctx->cpu_dst = ggml_rope_ext(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1, ctx->cpu_src2,
+                                                 n_dims, mode, n_ctx_orig, freq_base, freq_scale, ext_factor,
+                                                 attn_factor, beta_fast, beta_slow);
+                }
+            }
+            break;
+        case GGML_OP_RMS_NORM:
+            // Extract epsilon parameter from op_params (stored as float)
+            {
+                float eps;
+                memcpy(&eps, node->op_params, sizeof(float));
+                ctx->cpu_dst = ggml_rms_norm(ctx->ggml_ctx, ctx->cpu_src0, eps);
+            }
+            break;
+        case GGML_OP_SQR:
+            ctx->cpu_dst = ggml_sqr(ctx->ggml_ctx, ctx->cpu_src0);
+            break;
+        case GGML_OP_UNARY:
+            {
+                ggml_unary_op uop = (ggml_unary_op) ggml_get_op_params_i32(node, 0);
+                ctx->cpu_dst      = ggml_unary(ctx->ggml_ctx, ctx->cpu_src0, uop);
+            }
+            break;
+        case GGML_OP_SUM_ROWS:
+            ctx->cpu_dst = ggml_sum_rows(ctx->ggml_ctx, ctx->cpu_src0);
+            break;
+        case GGML_OP_MEAN:
+            ctx->cpu_dst = ggml_mean(ctx->ggml_ctx, ctx->cpu_src0);
+            break;
+        case GGML_OP_CLAMP:
+            {
+                float clamp_min, clamp_max;
+                memcpy(&clamp_min, (const float *) node->op_params + 0, sizeof(float));
+                memcpy(&clamp_max, (const float *) node->op_params + 1, sizeof(float));
+                ctx->cpu_dst = ggml_clamp(ctx->ggml_ctx, ctx->cpu_src0, clamp_min, clamp_max);
+            }
+            break;
+        case GGML_OP_GLU:
+            // Extract GLU parameters from op_params (split mode only)
+            {
+                int32_t     glu_op_type = ggml_get_op_params_i32(node, 0);  // GLU variant
+                ggml_glu_op glu_op      = (ggml_glu_op) glu_op_type;
+
+                // Only support split tensor mode
+                if (!ctx->cpu_src1) {
+                    GGML_LOG_ERROR("ET: GLU CPU comparison requires split tensor mode\n");
+                    return false;
+                }
+                ctx->cpu_dst = ggml_glu_split(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1, glu_op);
+            }
+            break;
+        case GGML_OP_SOFT_MAX:
+            {
+                // Extract scale and max_bias from op_params
+                float scale    = 1.0f;
+                float max_bias = 0.0f;
+                memcpy(&scale, (const float *) node->op_params + 0, sizeof(float));
+                memcpy(&max_bias, (const float *) node->op_params + 1, sizeof(float));
+
+                if (ctx->cpu_src1 || scale != 1.0f || max_bias != 0.0f) {
+                    // Use extended softmax when mask or non-default parameters are present
+                    ctx->cpu_dst = ggml_soft_max_ext(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1, scale, max_bias);
+                } else {
+                    // Use simple softmax when no mask and default parameters
+                    ctx->cpu_dst = ggml_soft_max(ctx->ggml_ctx, ctx->cpu_src0);
+                }
+
+                // Add sinks if present
+                if (ctx->cpu_src2) {
+                    ggml_soft_max_add_sinks(ctx->cpu_dst, ctx->cpu_src2);
+                }
+            }
+            break;
+        case GGML_OP_GET_ROWS:
+            ctx->cpu_dst = ggml_get_rows(ctx->ggml_ctx, ctx->cpu_src0, ctx->cpu_src1);
+            break;
+        case GGML_OP_CONT:
+            ctx->cpu_dst = ggml_cont(ctx->ggml_ctx, ctx->cpu_src0);
+            break;
+        case GGML_OP_SET_ROWS:
+            {
+                // SET_ROWS operation scatters src0 rows to dst[src1] positions
+                // Create destination tensor (this is the "view" that SET_ROWS returns)
+                ggml_tensor * cpu_dst_base = ggml_new_tensor(ctx->ggml_ctx, node->type, GGML_MAX_DIMS, node->ne);
+                if (!cpu_dst_base) {
+                    GGML_LOG_ERROR("ET: Failed to create CPU destination base tensor for SET_ROWS\n");
+                    return false;
+                }
+                cpu_dst_base->data = ctx->cpu_dst_data;
+                memcpy(cpu_dst_base->nb, node->nb, sizeof(node->nb));
+
+                // Note: cpu_dst_data already contains the pre-existing destination data from device
+                // SET_ROWS will update specific rows, leaving others unchanged
+
+                // Perform SET_ROWS operation: returns a view that scatters src0 rows to dst[src1] positions
+                ctx->cpu_dst = ggml_set_rows(ctx->ggml_ctx, cpu_dst_base, ctx->cpu_src0, ctx->cpu_src1);
+            }
+            break;
+        default:
+            GGML_LOG_ERROR("ET: Unsupported operation %s for CPU comparison\n", ggml_op_name(op));
+            return false;
+    }
+
+    if (!ctx->cpu_dst) {
+        GGML_LOG_ERROR("ET: Failed to create CPU destination tensor for operation %s\n", ggml_op_name(op));
+        return false;
+    }
+
+    ctx->cpu_dst->data = ctx->cpu_dst_data;
+    // Copy stride array (nb) for correct memory layout - except for CONT which should keep contiguous strides
+    if (op != GGML_OP_CONT) {
+        memcpy(ctx->cpu_dst->nb, node->nb, sizeof(node->nb));
+    }
+    // For CONT operations, keep the contiguous strides created by ggml_cont()
+
+    // Create minimal computation graph
+    ctx->cpu_graph = ggml_new_graph_custom(ctx->ggml_ctx, 1, false);
+    if (!ctx->cpu_graph) {
+        GGML_LOG_ERROR("ET: Failed to create CPU computation graph\n");
+        return false;
+    }
+    ctx->cpu_graph->nodes[0] = ctx->cpu_dst;
+    ctx->cpu_graph->n_nodes  = 1;
+
+    // Log input data for debugging if enabled
+    if (config && config->log_differences) {
+        if (ctx->cpu_src0_data && ctx->src0_size >= 4) {
+            GGML_LOG_DEBUG("ET: CPU src0 first few bytes: %02x %02x %02x %02x\n", ((uint8_t *) ctx->cpu_src0_data)[0],
+                           ((uint8_t *) ctx->cpu_src0_data)[1], ((uint8_t *) ctx->cpu_src0_data)[2],
+                           ((uint8_t *) ctx->cpu_src0_data)[3]);
+        }
+        if (ctx->cpu_src1_data && ctx->src1_size >= 16) {
+            GGML_LOG_DEBUG("ET: CPU src1 first few floats: %.6f %.6f %.6f %.6f\n", ((float *) ctx->cpu_src1_data)[0],
+                           ((float *) ctx->cpu_src1_data)[1], ((float *) ctx->cpu_src1_data)[2],
+                           ((float *) ctx->cpu_src1_data)[3]);
+        }
+    }
+
+    // Compute using CPU backend
+    ggml_status cpu_result = ggml_backend_graph_compute(ctx->cpu_backend, ctx->cpu_graph);
+
+    if (cpu_result != GGML_STATUS_SUCCESS) {
+        GGML_LOG_ERROR("ET: CPU reference computation failed with status %d\n", cpu_result);
+        return false;
+    }
+
+    // Log output data for debugging if enabled
+    if (config && config->log_differences && ctx->dst_size >= 16) {
+        GGML_LOG_DEBUG("ET: CPU dst first few floats after computation: %.6f %.6f %.6f %.6f\n",
+                       ((float *) ctx->cpu_dst_data)[0], ((float *) ctx->cpu_dst_data)[1],
+                       ((float *) ctx->cpu_dst_data)[2], ((float *) ctx->cpu_dst_data)[3]);
+    }
+
+    // Now copy ET device destination to host for comparison
+    size_t dst_logical_size = ggml_nbytes(node);
+    ggml_backend_tensor_get(node, ctx->et_dst_data, 0, dst_logical_size);
+
+    if (config->log_differences) {
+        size_t num_elements = ggml_nelements(node);
+        size_t max_log      = std::min(num_elements, config->max_log_elements);
+
+        // Check if this is an elementwise operation that can show src inputs
+        bool    is_elementwise = (op == GGML_OP_MUL || op == GGML_OP_ADD || op == GGML_OP_GLU);
+        float * cpu_src0_float = is_elementwise ? (float *) ctx->cpu_src0_data : nullptr;
+        float * cpu_src1_float = is_elementwise ? (float *) ctx->cpu_src1_data : nullptr;
+
+        // Helper to get float value from tensor data (handles f16 and f32)
+        auto get_float = [](const void * data, size_t idx, ggml_type type) -> float {
+            if (type == GGML_TYPE_F16) {
+                const ggml_fp16_t * fp16_data = (const ggml_fp16_t *) data;
+                return ggml_fp16_to_fp32(fp16_data[idx]);
+            }
+
+            const float * float_data = (const float *) data;
+            return float_data[idx];
+        };
+
+        // Compare all elements but log only the first max_log_elements
+        bool   matches          = true;
+        size_t total_mismatches = 0;
+
+        // First pass: check all elements for mismatches
+        for (size_t i = 0; i < num_elements; i++) {
+            float cpu_val  = get_float(ctx->cpu_dst_data, i, node->type);
+            float et_val   = get_float(ctx->et_dst_data, i, node->type);
+            float diff     = fabsf(cpu_val - et_val);
+            float rel_diff = diff / (fabsf(cpu_val) + 1e-8f);
+
+            if (rel_diff > config->tolerance) {
+                matches = false;
+                total_mismatches++;
+            }
+        }
+
+        // Second pass: log detailed info for first max_log elements only
+        for (size_t i = 0; i < max_log; i++) {
+            float cpu_val = get_float(ctx->cpu_dst_data, i, node->type);
+            float et_val  = get_float(ctx->et_dst_data, i, node->type);
+            float diff    = fabsf(cpu_val - et_val);
+
+            if (is_elementwise && cpu_src0_float && cpu_src1_float) {
+                GGML_LOG_DEBUG("ET: [%zu] src0=%.6f, src1=%.6f -> CPU=%.6f, ET=%.6f, diff=%.6f\n", i, cpu_src0_float[i],
+                               cpu_src1_float[i], cpu_val, et_val, diff);
+            } else if (is_elementwise && cpu_src0_float) {
+                GGML_LOG_DEBUG("ET: [%zu] src0=%.6f -> CPU=%.6f, ET=%.6f, diff=%.6f\n", i, cpu_src0_float[i], cpu_val,
+                               et_val, diff);
+            } else {
+                GGML_LOG_DEBUG("ET: [%zu] CPU=%.6f, ET=%.6f, diff=%.6f\n", i, cpu_val, et_val, diff);
+            }
+        }
+
+        // Check some elements from the middle and end for full coverage
+        if (num_elements > max_log) {
+            size_t mid     = num_elements / 2;
+            size_t end     = num_elements - 1;
+            float  cpu_mid = get_float(ctx->cpu_dst_data, mid, node->type);
+            float  et_mid  = get_float(ctx->et_dst_data, mid, node->type);
+            float  cpu_end = get_float(ctx->cpu_dst_data, end, node->type);
+            float  et_end  = get_float(ctx->et_dst_data, end, node->type);
+
+            GGML_LOG_DEBUG("ET: Middle element [%zu]: CPU=%.6f, ET=%.6f\n", mid, cpu_mid, et_mid);
+            GGML_LOG_DEBUG("ET: Last element [%zu]: CPU=%.6f, ET=%.6f\n", end, cpu_end, et_end);
+        }
+
+        GGML_LOG_DEBUG("ET: Results %s (%zu/%zu elements match within tolerance %.6f)\n", matches ? "MATCH" : "DIFFER",
+                       num_elements - total_mismatches, num_elements, config->tolerance);
+    }
+
+    // Copy CPU result to device if flag is set
+    if (config->use_cpu_result) {
+        GGML_LOG_DEBUG("ET: Overwriting ET device result with CPU result for correct inference\n");
+        size_t dst_logical_size = ggml_nbytes(node);
+        ggml_backend_tensor_set(const_cast<ggml_tensor *>(node), ctx->cpu_dst_data, 0, dst_logical_size);
+        GGML_LOG_DEBUG("ET: CPU result copied to ET device buffer\n");
+    }
+
+    return true;
+}
+
+void ggml_et_cpu_compare_free(ggml_et_cpu_compare_ctx * ctx) {
+    if (!ctx) {
+        return;
+    }
+
+    if (ctx->cpu_src0_data) {
+        free(ctx->cpu_src0_data);
+        ctx->cpu_src0_data = nullptr;
+    }
+    if (ctx->cpu_src1_data) {
+        free(ctx->cpu_src1_data);
+        ctx->cpu_src1_data = nullptr;
+    }
+    if (ctx->cpu_src2_data) {
+        free(ctx->cpu_src2_data);
+        ctx->cpu_src2_data = nullptr;
+    }
+    if (ctx->cpu_dst_data) {
+        free(ctx->cpu_dst_data);
+        ctx->cpu_dst_data = nullptr;
+    }
+    if (ctx->et_dst_data) {
+        free(ctx->et_dst_data);
+        ctx->et_dst_data = nullptr;
+    }
+
+    if (ctx->ggml_ctx) {
+        ggml_free(ctx->ggml_ctx);
+        ctx->ggml_ctx = nullptr;
+    }
+
+    if (ctx->cpu_backend) {
+        ggml_backend_free(ctx->cpu_backend);
+        ctx->cpu_backend = nullptr;
+    }
+
+    // Clear pointers
+    ctx->cpu_src0  = nullptr;
+    ctx->cpu_src1  = nullptr;
+    ctx->cpu_src2  = nullptr;
+    ctx->cpu_dst   = nullptr;
+    ctx->cpu_graph = nullptr;
+}

diff --git a/ggml/src/ggml-et/ggml-et-cpu-compare.h b/ggml/src/ggml-et/ggml-et-cpu-compare.h
new file mode 100644 (file)
index 0000000..da839fa
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-cpu-compare.h
@@ -0,0 +1,54 @@
+#pragma once
+
+#include "ggml-cpu.h"
+#include "ggml-et-common.h"
+#include "ggml-impl.h"
+
+// Configuration for CPU comparison
+struct ggml_et_cpu_compare_config {
+    bool   enabled;           // Whether to enable CPU comparison
+    bool   use_cpu_result;    // Whether to replace ET result with CPU result
+    bool   log_differences;   // Whether to log detailed element differences
+    float  tolerance;         // Relative tolerance for comparison (default: 1e-5f)
+    size_t max_log_elements;  // Maximum number of elements to log (default: 10)
+};
+
+// Default configuration
+static const ggml_et_cpu_compare_config ggml_et_cpu_compare_default_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 10
+};
+
+// CPU comparison context for a single operation
+struct ggml_et_cpu_compare_ctx {
+    ggml_backend_t cpu_backend;
+    ggml_context * ggml_ctx;
+    ggml_tensor *  cpu_src0;
+    ggml_tensor *  cpu_src1;
+    ggml_tensor *  cpu_src2;
+    ggml_tensor *  cpu_dst;
+    ggml_cgraph *  cpu_graph;
+    void *         cpu_src0_data;
+    void *         cpu_src1_data;
+    void *         cpu_src2_data;
+    void *         cpu_dst_data;
+    void *         et_dst_data;
+    size_t         src0_size;
+    size_t         src1_size;
+    size_t         src2_size;
+    size_t         dst_size;
+};
+
+// Phase 1: Initialize CPU comparison context and copy source buffers (call before ET kernel)
+bool ggml_et_cpu_compare_init_pre(ggml_et_cpu_compare_ctx * ctx, const ggml_tensor * node, ggml_op op);
+
+// Phase 2: Execute CPU computation and compare with ET result (call after ET kernel)
+bool ggml_et_cpu_compare_compute_and_check(ggml_et_cpu_compare_ctx *          ctx,
+                                           const ggml_tensor *                node,
+                                           const ggml_et_cpu_compare_config * config);
+
+// Free CPU comparison context resources
+void ggml_et_cpu_compare_free(ggml_et_cpu_compare_ctx * ctx);

diff --git a/ggml/src/ggml-et/ggml-et-kernels.cpp b/ggml/src/ggml-et/ggml-et-kernels.cpp
new file mode 100644 (file)
index 0000000..3e11928
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-kernels.cpp
@@ -0,0 +1,508 @@
+#include "ggml-et-kernels.h"
+
+#include "ggml-et-kernels-embed.hpp"
+#include "ggml-et-uberkernel-kernel-map.h"
+#include "ggml-impl.h"
+
+#include <cstdlib>
+#include <cstring>
+#include <fstream>
+
+#define ET_TRACE_DECODER_IMPL
+#include <et-trace/decoder.h>
+#include <et-trace/layout.h>
+
+static constexpr size_t GGML_ET_UBERKERNEL_PARAM_ALIGN = 64;
+
+static size_t ggml_et_align_up(size_t value, size_t alignment) {
+    return (value + alignment - 1) & ~(alignment - 1);
+}
+
+static size_t ggml_et_next_capacity(size_t current_capacity, size_t required_capacity) {
+    if (current_capacity == 0) {
+        return required_capacity;
+    }
+
+    size_t next_capacity = current_capacity;
+    while (next_capacity < required_capacity) {
+        next_capacity *= 2;
+    }
+
+    return next_capacity;
+}
+
+static ggml_backend_et_uberkernel_slot & ggml_et_uberkernel_current_slot(ggml_backend_et_uberkernel_context * uk_ctx) {
+    return uk_ctx->slots[uk_ctx->current_slot];
+}
+
+// Wait for any in-flight launch that previously used this slot to finish,
+// so the host vectors and device buffers are safe to mutate / free.
+static void ggml_et_uberkernel_slot_wait(ggml_backend_et_uberkernel_slot &     slot,
+                                         const std::shared_ptr<rt::IRuntime> & runtime) {
+    if (!slot.has_pending || !runtime) {
+        return;
+    }
+    runtime->waitForEvent(slot.pending_event);
+    slot.has_pending = false;
+}
+
+static void ggml_et_uberkernel_reset_segment(ggml_backend_et_uberkernel_context * uk_ctx) {
+    if (!uk_ctx) {
+        return;
+    }
+
+    uk_ctx->shire_mask = 0;
+    auto & slot        = ggml_et_uberkernel_current_slot(uk_ctx);
+    // Drain any prior launch on this slot before clearing its host buffers.
+    // begin_graph and abort_graph both come through here; in either case we
+    // must not yank the source memory out from under an in-flight DMA.
+    ggml_et_uberkernel_slot_wait(slot, ggml_et_runtime());
+    slot.insts.clear();
+    slot.params_blob.clear();
+}
+
+static bool ggml_et_uberkernel_ensure_slot_capacity(ggml_backend_et_uberkernel_slot & slot,
+                                                    ggml_backend_et_device_context *  dev_ctx,
+                                                    size_t                            insts_size,
+                                                    size_t                            params_size) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!dev_ctx || !runtime) {
+        return false;
+    }
+
+    try {
+        if (slot.device_insts == nullptr || insts_size > slot.device_insts_capacity) {
+            const size_t new_capacity = ggml_et_next_capacity(slot.device_insts_capacity, insts_size);
+            if (slot.device_insts) {
+                runtime->freeDevice(dev_ctx->rtid, slot.device_insts);
+            }
+            slot.device_insts          = runtime->mallocDevice(dev_ctx->rtid, new_capacity);
+            slot.device_insts_capacity = slot.device_insts ? new_capacity : 0;
+        }
+
+        if (slot.device_params == nullptr || params_size > slot.device_params_capacity) {
+            const size_t new_capacity = ggml_et_next_capacity(slot.device_params_capacity, params_size);
+            if (slot.device_params) {
+                runtime->freeDevice(dev_ctx->rtid, slot.device_params);
+            }
+            slot.device_params          = runtime->mallocDevice(dev_ctx->rtid, new_capacity);
+            slot.device_params_capacity = slot.device_params ? new_capacity : 0;
+        }
+    } catch (const std::exception & e) {
+        GGML_LOG_ERROR("ET: Failed to resize uberkernel buffers: %s\n", e.what());
+        return false;
+    }
+
+    return slot.device_insts != nullptr && slot.device_params != nullptr;
+}
+
+// Get embedded kernel data by name
+static std::vector<std::byte> ggml_et_get_embedded_kernel(const std::string & kernel_name) {
+    auto it = ggml_et_embedded_kernels.find(kernel_name);
+    if (it == ggml_et_embedded_kernels.end()) {
+        GGML_LOG_ERROR("ET: Unknown embedded kernel: %s\n", kernel_name.c_str());
+        return {};
+    }
+
+    const unsigned char * data = it->second.first;
+    uint64_t              size = it->second.second;
+
+    std::vector<std::byte> buffer(size);
+    std::memcpy(buffer.data(), data, size);
+
+    return buffer;
+}
+
+// Read kernel from file (for development/override)
+static std::vector<std::byte> ggml_et_read_kernel_file(const std::string & kernel_path) {
+    std::ifstream file(kernel_path, std::ios::binary | std::ios::ate);
+    if (!file) {
+        return {};
+    }
+
+    auto size = file.tellg();
+    file.seekg(0, std::ios::beg);
+
+    std::vector<std::byte> buffer(size);
+    file.read(reinterpret_cast<char *>(buffer.data()), size);
+
+    return buffer;
+}
+
+// Load kernel from file or embedded data
+bool ggml_et_load_kernel(ggml_backend_et_device_context * dev_ctx, const std::string & kernel_name) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        GGML_LOG_ERROR("ET: Runtime not available for kernel loading\n");
+        return false;
+    }
+
+    // Check if kernel already loaded
+    if (dev_ctx->loaded_kernels.find(kernel_name) != dev_ctx->loaded_kernels.end()) {
+        GGML_LOG_DEBUG("ET: Kernel %s already loaded on device %d\n", kernel_name.c_str(), dev_ctx->devidx);
+        return true;
+    }
+
+    std::vector<std::byte> kernel_data;
+    const char *           kernels_path = getenv("GGML_ET_KERNELS_PATH");
+
+    // If GGML_ET_KERNELS_PATH is set, try to load from file first
+    if (kernels_path) {
+        std::string kernel_file = std::string(kernels_path) + "/" + kernel_name + ".elf";
+        kernel_data             = ggml_et_read_kernel_file(kernel_file);
+
+        if (!kernel_data.empty()) {
+            GGML_LOG_INFO("ET: Loading kernel %s from file: %s\n", kernel_name.c_str(), kernel_file.c_str());
+        } else {
+            GGML_LOG_INFO("ET: Kernel file not found: %s, falling back to embedded\n", kernel_file.c_str());
+        }
+    }
+
+    // If no file data, use embedded kernel
+    if (kernel_data.empty()) {
+        kernel_data = ggml_et_get_embedded_kernel(kernel_name);
+        if (kernel_data.empty()) {
+            GGML_LOG_ERROR("ET: Failed to get kernel data for %s\n", kernel_name.c_str());
+            return false;
+        }
+    }
+
+    try {
+        // Load kernel code using device's default stream
+        auto load_result = runtime->loadCode(dev_ctx->default_stream, kernel_data.data(), kernel_data.size());
+        runtime->waitForEvent(load_result.event_);
+
+        // Store kernel handle
+        dev_ctx->loaded_kernels[kernel_name] = load_result.kernel_;
+        return true;
+
+    } catch (const std::exception & e) {
+        GGML_LOG_ERROR("ET: Failed to load kernel %s: %s\n", kernel_name.c_str(), e.what());
+        return false;
+    }
+}
+
+static bool ggml_et_launch_kernel_internal(ggml_backend_et_device_context * dev_ctx,
+                                           const std::string &              kernel_name,
+                                           void *                           params,
+                                           size_t                           params_size,
+                                           uint64_t                         shire_mask,
+                                           bool                             enable_print,
+                                           bool                             sync_error_check,
+                                           rt::EventId *                    out_event = nullptr) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        GGML_LOG_ERROR("ET: Runtime not available for kernel launch\n");
+        return false;
+    }
+
+    // Lazy loading: check if kernel is loaded, load if needed
+    auto kernel_it = dev_ctx->loaded_kernels.find(kernel_name);
+    if (kernel_it == dev_ctx->loaded_kernels.end()) {
+        // Kernel not loaded - load it
+        if (!ggml_et_load_kernel(dev_ctx, kernel_name)) {
+            GGML_LOG_ERROR("ET: Failed to lazy-load kernel %s\n", kernel_name.c_str());
+            return false;
+        }
+
+        // Update iterator after successful load
+        kernel_it = dev_ctx->loaded_kernels.find(kernel_name);
+        if (kernel_it == dev_ctx->loaded_kernels.end()) {
+            GGML_LOG_ERROR("ET: Kernel %s not found after loading\n", kernel_name.c_str());
+            return false;
+        }
+    }
+
+    rt::KernelId kernel_id = kernel_it->second;
+
+    try {
+        // Setup kernel launch options
+        rt::KernelLaunchOptions k_opts;
+        k_opts.setShireMask(shire_mask);  // Default: all shires (0xFFFFFFFF)
+        k_opts.setBarrier(true);          // Wait for completion
+        k_opts.setFlushL3(false);         // No L3 flush needed
+        if (enable_print) {
+            k_opts.setUserTracing(reinterpret_cast<uint64_t>(dev_ctx->trace_buffer),
+                                  static_cast<uint32_t>(ET_TRACE_BUFFER_SIZE),
+                                  0,                      // threshold
+                                  shire_mask,             // shire mask
+                                  0xFFFFFFFFFFFFFFFFULL,  // threadMask - all threads
+                                  0xFFFFFFFFU,            // eventMask - all events
+                                  0xFFFFFFFFU             // filterMask - all levels
+            );
+        }
+
+        if (sync_error_check) {
+            runtime->waitForStream(dev_ctx->default_stream);
+            auto errors = runtime->retrieveStreamErrors(dev_ctx->default_stream);
+            if (!errors.empty()) {
+                GGML_LOG_ERROR("ET: Errors detected before kernel \"%s\" launch\n", kernel_name.c_str());
+                for (const auto & error : errors) {
+                    GGML_LOG_ERROR("ET: Error code: %d\n", (int) error.errorCode_);
+                }
+                abort();
+            }
+        }
+
+        rt::EventId launch_event = runtime->kernelLaunch(dev_ctx->default_stream, kernel_id,
+                                                         reinterpret_cast<std::byte *>(params), params_size, k_opts);
+        if (out_event) {
+            *out_event = launch_event;
+        }
+
+        if (enable_print) {
+            std::vector<std::byte> host_trace_buf(ET_TRACE_BUFFER_SIZE);
+            runtime->memcpyDeviceToHost(dev_ctx->default_stream, dev_ctx->trace_buffer, host_trace_buf.data(),
+                                        ET_TRACE_BUFFER_SIZE);
+            runtime->waitForStream(dev_ctx->default_stream);
+            const auto * trace_header = reinterpret_cast<const trace_buffer_std_header_t *>(host_trace_buf.data());
+            const trace_entry_header_t * entry = nullptr;
+            while ((entry = Trace_Decode(trace_header, entry))) {
+                if (entry->type != TRACE_TYPE_STRING) {
+                    continue;
+                }
+                const auto * str_entry = reinterpret_cast<const trace_string_t *>(entry);
+                printf("[hart %d] %s", entry->hart_id, str_entry->string);
+            }
+        }
+
+        if (sync_error_check) {
+            // Already triggered. No need to retrigger
+            if (!enable_print) {
+                runtime->waitForStream(dev_ctx->default_stream);
+            }
+            auto errors = runtime->retrieveStreamErrors(dev_ctx->default_stream);
+            if (!errors.empty()) {
+                GGML_LOG_ERROR("ET: Errors detected during kernel \"%s\" execution\n", kernel_name.c_str());
+                for (const auto & error : errors) {
+                    GGML_LOG_ERROR("ET: Error code: %d\n", (int) error.errorCode_);
+                }
+                abort();
+            }
+        }
+
+        return true;
+    } catch (const std::exception & e) {
+        GGML_LOG_ERROR("ET: Failed to launch kernel %s: %s\n", kernel_name.c_str(), e.what());
+        return false;
+    }
+}
+
+void ggml_et_uberkernel_begin_graph(ggml_backend_et_uberkernel_context * uk_ctx) {
+    if (!uk_ctx) {
+        return;
+    }
+
+    uk_ctx->failed = false;
+    ggml_et_uberkernel_reset_segment(uk_ctx);
+}
+
+static bool ggml_et_launch_uberkernel_segment(ggml_backend_et_device_context *     dev_ctx,
+                                              ggml_backend_et_uberkernel_context * uk_ctx) {
+    if (!uk_ctx || !dev_ctx) {
+        return false;
+    }
+
+    auto & slot = ggml_et_uberkernel_current_slot(uk_ctx);
+    if (slot.insts.empty()) {
+        return true;
+    }
+
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        GGML_LOG_ERROR("ET: Runtime not available for uberkernel commit\n");
+        uk_ctx->failed = true;
+        return false;
+    }
+
+    const size_t   insts_size  = slot.insts.size() * sizeof(ggml_et_uberkernel_inst);
+    const size_t   params_size = slot.params_blob.size();
+    const uint64_t shire_mask  = uk_ctx->shire_mask;
+    bool           ok          = false;
+
+    try {
+        if (!ggml_et_uberkernel_ensure_slot_capacity(slot, dev_ctx, insts_size, params_size)) {
+            GGML_LOG_ERROR("ET: Failed to allocate uberkernel device buffers\n");
+            uk_ctx->failed = true;
+            // Drop this segment but keep the slot drained so we don't leak
+            // host vectors into the next graph.
+            slot.insts.clear();
+            slot.params_blob.clear();
+            uk_ctx->shire_mask = 0;
+            return false;
+        }
+
+        // Fire-and-forget H2D + launch on default_stream. In-stream FIFO
+        // ordering guarantees the kernel sees fully-uploaded buffers; the
+        // host source bytes (slot.insts / slot.params_blob) stay alive
+        // because we won't touch this slot again until pending_event fires.
+        runtime->memcpyHostToDevice(dev_ctx->default_stream, reinterpret_cast<const std::byte *>(slot.insts.data()),
+                                    slot.device_insts, insts_size, true);
+        runtime->memcpyHostToDevice(dev_ctx->default_stream, slot.params_blob.data(), slot.device_params, params_size,
+                                    true);
+
+        ggml_et_uberkernel_params params = {
+            static_cast<uint32_t>(slot.insts.size()),
+            static_cast<uint32_t>(sizeof(ggml_et_uberkernel_inst)),
+            reinterpret_cast<uint64_t>(slot.device_insts),
+            reinterpret_cast<uint64_t>(slot.device_params),
+        };
+
+        rt::EventId launch_event{};
+        ok = ggml_et_launch_kernel_internal(dev_ctx, "uberkernel", &params, sizeof(params), shire_mask, false, false,
+                                            &launch_event);
+        if (ok) {
+            // The kernelLaunch above is the last thing on default_stream
+            // that touches this slot's device buffers. Recording its event
+            // lets the next reuse of this slot wait on that one event
+            // instead of the whole stream.
+            slot.pending_event = launch_event;
+            slot.has_pending   = true;
+        }
+    } catch (const std::exception & e) {
+        GGML_LOG_ERROR("ET: Failed to commit uberkernel segment: %s\n", e.what());
+    }
+    uk_ctx->failed = !ok;
+
+    if (ok) {
+        uk_ctx->current_slot = (uk_ctx->current_slot + 1) % ggml_backend_et_uberkernel_context::SLOT_COUNT;
+        auto & next          = ggml_et_uberkernel_current_slot(uk_ctx);
+        ggml_et_uberkernel_slot_wait(next, runtime);
+        next.insts.clear();
+        next.params_blob.clear();
+    } else {
+        slot.insts.clear();
+        slot.params_blob.clear();
+    }
+    uk_ctx->shire_mask = 0;
+    return ok;
+}
+
+void ggml_et_uberkernel_abort_graph(ggml_backend_et_uberkernel_context * uk_ctx) {
+    if (!uk_ctx) {
+        return;
+    }
+
+    uk_ctx->failed = false;
+    ggml_et_uberkernel_reset_segment(uk_ctx);
+}
+
+bool ggml_et_uberkernel_failed(const ggml_backend_et_uberkernel_context * uk_ctx) {
+    return uk_ctx && uk_ctx->failed;
+}
+
+static bool ggml_et_launch_uberkernel(ggml_backend_et_device_context * dev_ctx,
+                                      const std::string &              kernel_name,
+                                      void *                           params,
+                                      size_t                           params_size,
+                                      uint64_t                         shire_mask,
+                                      bool                             enable_print,
+                                      bool                             sync_error_check) {
+    if (!dev_ctx) {
+        return false;
+    }
+
+    ggml_backend_et_uberkernel_context * uk_ctx        = &dev_ctx->uberkernel;
+    const uint16_t                       uberkernel_id = ggml_et_uberkernel_kernel_id_from_name(kernel_name.c_str());
+    if (uberkernel_id == GGML_ET_UBERKERNEL_KERNEL_INVALID) {
+        if (!ggml_et_launch_uberkernel_segment(dev_ctx, uk_ctx)) {
+            return false;
+        }
+        return ggml_et_launch_kernel_internal(dev_ctx, kernel_name, params, params_size, shire_mask, enable_print,
+                                              sync_error_check);
+    }
+
+    auto &       slot          = ggml_et_uberkernel_current_slot(uk_ctx);
+    const size_t params_offset = ggml_et_align_up(slot.params_blob.size(), GGML_ET_UBERKERNEL_PARAM_ALIGN);
+    if (params_offset > slot.params_blob.size()) {
+        slot.params_blob.resize(params_offset);
+    }
+
+    const std::byte * params_bytes = reinterpret_cast<const std::byte *>(params);
+    slot.params_blob.insert(slot.params_blob.end(), params_bytes, params_bytes + params_size);
+
+    ggml_et_uberkernel_inst inst = {
+        uberkernel_id,
+        0,
+        static_cast<uint32_t>(params_offset),
+        static_cast<uint32_t>(params_size),
+    };
+    slot.insts.push_back(inst);
+
+    if (slot.insts.size() == 1) {
+        uk_ctx->shire_mask = shire_mask;
+    }
+
+    return true;
+}
+
+bool ggml_et_uberkernel_end_graph(ggml_backend_et_device_context * dev_ctx) {
+    if (!dev_ctx || !dev_ctx->uberkernel_enabled) {
+        return true;
+    }
+
+    return ggml_et_launch_uberkernel_segment(dev_ctx, &dev_ctx->uberkernel);
+}
+
+bool ggml_et_launch_kernel(ggml_backend_et_device_context * dev_ctx,
+                           const std::string &              kernel_name,
+                           void *                           params,
+                           size_t                           params_size,
+                           uint64_t                         shire_mask,
+                           bool                             enable_print,
+                           bool                             sync_error_check) {
+    if (!dev_ctx) {
+        return false;
+    }
+
+    if (!dev_ctx->uberkernel_enabled) {
+        return ggml_et_launch_kernel_internal(dev_ctx, kernel_name, params, params_size, shire_mask, enable_print,
+                                              sync_error_check);
+    }
+
+    return ggml_et_launch_uberkernel(dev_ctx, kernel_name, params, params_size, shire_mask, enable_print,
+                                     sync_error_check);
+}
+
+void ggml_et_unload_kernel(ggml_backend_et_device_context * dev_ctx, const std::string & kernel_name) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        return;
+    }
+
+    auto kernel_it = dev_ctx->loaded_kernels.find(kernel_name);
+    if (kernel_it != dev_ctx->loaded_kernels.end()) {
+        try {
+            runtime->unloadCode(kernel_it->second);
+            dev_ctx->loaded_kernels.erase(kernel_it);
+        } catch (const std::exception & e) {
+            GGML_LOG_ERROR("ET: Failed to unload kernel %s: %s\n", kernel_name.c_str(), e.what());
+        }
+    }
+}
+
+void ggml_et_unload_all_kernels(ggml_backend_et_device_context * dev_ctx) {
+    if (!dev_ctx) {
+        return;
+    }
+
+    // Make a copy of kernel names since ggml_et_unload_kernel modifies the map
+    std::vector<std::string> kernel_names;
+    kernel_names.reserve(dev_ctx->loaded_kernels.size());
+    for (const auto & kernel_pair : dev_ctx->loaded_kernels) {
+        kernel_names.push_back(kernel_pair.first);
+    }
+
+    for (const auto & kernel_name : kernel_names) {
+        ggml_et_unload_kernel(dev_ctx, kernel_name);
+    }
+}
+
+std::vector<std::pair<std::string, rt::KernelId>> ggml_et_get_loaded_kernels(ggml_backend_et_device_context * dev_ctx) {
+    std::vector<std::pair<std::string, rt::KernelId>> loaded_kernels;
+    loaded_kernels.reserve(dev_ctx->loaded_kernels.size());
+    for (const auto & kernel_pair : dev_ctx->loaded_kernels) {
+        loaded_kernels.push_back(kernel_pair);
+    }
+    return loaded_kernels;
+}

diff --git a/ggml/src/ggml-et/ggml-et-kernels.h b/ggml/src/ggml-et/ggml-et-kernels.h
new file mode 100644 (file)
index 0000000..76819f5
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-kernels.h
@@ -0,0 +1,48 @@
+#pragma once
+
+#include "ggml-et-common.h"
+
+#include <string>
+#include <utility>
+#include <vector>
+
+#define ET_TRACE_BUFFER_SIZE (1024 * 1024 * 8UL)
+
+// Load kernel from file or embedded data and store handle in device context
+// Returns true on success, false on failure
+//
+// Loading strategy:
+// - If GGML_ET_KERNELS_PATH env var is set: tries to load from ${GGML_ET_KERNELS_PATH}/${kernel_name}.elf
+// - If file not found or env var not set: falls back to embedded kernel data
+// - Returns false if kernel cannot be loaded from either source
+//
+// Kernel is loaded using the device's default stream
+bool ggml_et_load_kernel(ggml_backend_et_device_context * dev_ctx, const std::string & kernel_name);
+
+// Launch kernel with parameters on device's default stream
+// Performs lazy loading: automatically loads kernel if not already loaded
+// Kernel path: ${GGML_ET_KERNELS_PATH}/${kernel_name}.elf (default: /opt/et/ggml/kernels/)
+// Returns true on success, false on failure
+// Execution is synchronous - waits for completion
+bool ggml_et_launch_kernel(ggml_backend_et_device_context * dev_ctx,
+                           const std::string &              kernel_name,
+                           void *                           params,
+                           size_t                           params_size,
+                           uint64_t                         shire_mask       = 0xFFFFFFFF,
+                           bool                             enable_print     = false,
+                           bool                             sync_error_check = false);
+
+void ggml_et_uberkernel_begin_graph(ggml_backend_et_uberkernel_context * uk_ctx);
+bool ggml_et_uberkernel_end_graph(ggml_backend_et_device_context * dev_ctx);
+void ggml_et_uberkernel_abort_graph(ggml_backend_et_uberkernel_context * uk_ctx);
+bool ggml_et_uberkernel_failed(const ggml_backend_et_uberkernel_context * uk_ctx);
+
+// Unload kernel from device and free resources
+// Safe to call even if kernel not loaded
+void ggml_et_unload_kernel(ggml_backend_et_device_context * dev_ctx, const std::string & kernel_name);
+
+// Unload all kernels from device context
+// Called during device cleanup
+void ggml_et_unload_all_kernels(ggml_backend_et_device_context * dev_ctx);
+
+std::vector<std::pair<std::string, rt::KernelId>> ggml_et_get_loaded_kernels(ggml_backend_et_device_context * dev_ctx);

diff --git a/ggml/src/ggml-et/ggml-et-memops.cpp b/ggml/src/ggml-et/ggml-et-memops.cpp
new file mode 100644 (file)
index 0000000..13242ab
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-memops.cpp
@@ -0,0 +1,36 @@
+#include "ggml-et-memops.h"
+
+#include "ggml-et-kernels.h"
+#include "ggml-impl.h"
+
+// Kernel parameter structure for memset operation
+struct memset_params {
+    uint32_t op_type;  // GGML_ET_MEMOP_MEMSET
+    uint32_t value;    // Value to set (extended to uint32_t for alignment)
+    void *   dst_ptr;  // Destination device pointer
+    size_t   size;     // Number of bytes to set
+};
+
+bool ggml_et_memset(ggml_backend_et_device_context * dev_ctx, void * dst_ptr, uint8_t value, size_t size) {
+    if (!dev_ctx || !dst_ptr || size == 0) {
+        GGML_LOG_ERROR("ET: Invalid memset parameters\n");
+        return false;
+    }
+
+    // Prepare kernel parameters
+    memset_params params;
+    params.op_type = GGML_ET_MEMOP_MEMSET;
+    params.value   = value;
+    params.dst_ptr = dst_ptr;
+    params.size    = size;
+
+    // Launch memops kernel (will lazy-load if not already loaded)
+    bool success = ggml_et_launch_kernel(dev_ctx, "memops", &params, sizeof(params));
+
+    if (!success) {
+        GGML_LOG_ERROR("ET: memset kernel launch failed\n");
+        return false;
+    }
+
+    return true;
+}

diff --git a/ggml/src/ggml-et/ggml-et-memops.h b/ggml/src/ggml-et/ggml-et-memops.h
new file mode 100644 (file)
index 0000000..37a4fd9
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-memops.h
@@ -0,0 +1,18 @@
+#pragma once
+
+#include "ggml-et-common.h"
+
+#include <cstddef>
+#include <cstdint>
+
+// Memory operations using device kernel (memops.elf)
+// Single kernel handles multiple operations via operation identifier
+
+// Operation identifiers for memops kernel
+enum ggml_et_memop_type : uint32_t {
+    GGML_ET_MEMOP_MEMSET = 0,
+};
+
+// Memset operation: fill device memory with a value
+// Returns true on success, false on failure
+bool ggml_et_memset(ggml_backend_et_device_context * dev_ctx, void * dst_ptr, uint8_t value, size_t size);

diff --git a/ggml/src/ggml-et/ggml-et-ops.cpp b/ggml/src/ggml-et/ggml-et-ops.cpp
new file mode 100644 (file)
index 0000000..6c80fe8
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-ops.cpp
@@ -0,0 +1,2580 @@
+#include "ggml-et-ops.h"
+
+#include "ggml-et-cpu-compare.h"
+#include "ggml-et-kernels.h"
+#include "ggml-impl.h"
+
+#include <stdio.h>
+
+#include <cstdint>
+
+// CPU comparison configuration - can be enabled for debugging
+static ggml_et_cpu_compare_config rope_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,  // Replace ET result with CPU result
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config rms_norm_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config norm_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config l2_norm_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config group_norm_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config im2col_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config unary_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-4f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config sum_rows_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config clamp_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config mean_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config sqr_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config elmap_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config glu_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config mul_mat_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 0.01,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config mul_mat_id_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 0.01,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config softmax_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-5f,
+    /* .max_log_elements = */ 1024
+};
+
+static ggml_et_cpu_compare_config get_rows_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 2048
+};
+
+static ggml_et_cpu_compare_config pad_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config cont_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config concat_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config cumsum_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config repeat_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config ssm_conv_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config rwkv_wkv6_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-4f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config rwkv_wkv7_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-4f,
+    /* .max_log_elements = */ 4096
+};
+
+static ggml_et_cpu_compare_config set_rows_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-6f,
+    /* .max_log_elements = */ 2048
+};
+
+bool ggml_et_op_rms_norm_mul(ggml_backend_et_device_context * dev_ctx,
+                             const ggml_tensor *              rms_norm_node,
+                             const ggml_tensor *              mul_node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !rms_norm_node || !mul_node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for fused RMS_NORM_MUL operation\n");
+        return false;
+    }
+
+    if (!rms_norm_node->src[0]) {
+        GGML_LOG_ERROR("ET: Fused RMS_NORM_MUL missing required input\n");
+        return false;
+    }
+
+    // Extract weights: the MUL operand that isn't the rms_norm output
+    const ggml_tensor * weights = (mul_node->src[0] == rms_norm_node) ? mul_node->src[1] : mul_node->src[0];
+
+    if (!weights) {
+        GGML_LOG_ERROR("ET: Fused RMS_NORM_MUL missing weights tensor\n");
+        return false;
+    }
+
+    float eps;
+    memcpy(&eps, rms_norm_node->op_params, sizeof(float));
+
+    ggml_et_rms_norm_mul_params params;
+    params.src0 = *rms_norm_node->src[0];  // input to normalize
+    params.src1 = *weights;                // normalization weights
+    params.dst  = *mul_node;               // final output
+    params.eps  = eps;
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "rms_norm_mul_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END_EXT("RMS_NORM_MUL", "rms_norm_mul_f32", mul_node, "eps=%.6f", (double) eps);
+    return kernel_result;
+}
+
+bool ggml_et_op_scale(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SCALE operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: SCALE operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: SCALE operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    float scale, bias;
+    memcpy(&scale, (const float *) node->op_params + 0, sizeof(float));
+    memcpy(&bias, (const float *) node->op_params + 1, sizeof(float));
+
+    ggml_et_scale_params params;
+    params.src0  = *node->src[0];
+    params.dst   = *node;
+    params.scale = scale;
+    params.bias  = bias;
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "scale_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END_EXT("SCALE", "scale_f32", node, "scale=%.6f|bias=%.6f", (double) scale, (double) bias);
+    return kernel_result;
+}
+
+bool ggml_et_op_sqr(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SQR operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: SQR operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: SQR operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    ggml_et_sqr_params params;
+    params.src0 = *node->src[0];  // F32 input tensor
+    params.dst  = *node;          // F32 output tensor
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (sqr_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_SQR)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for SQR operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "sqr_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &sqr_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for SQR operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("SQR", "sqr_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_sum_rows(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SUM_ROWS operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: SUM_ROWS operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: SUM_ROWS operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    ggml_et_sum_rows_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+
+    // Phase 1: Initialize CPU comparison context
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (sum_rows_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_SUM_ROWS)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for SUM_ROWS operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "sum_rows_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &sum_rows_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for SUM_ROWS operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("SUM_ROWS", "sum_rows_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_mean(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for MEAN operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: MEAN operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: MEAN operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    ggml_et_mean_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (mean_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_MEAN)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for MEAN operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "mean_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &mean_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for MEAN operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("MEAN", "mean_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_clamp(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for CLAMP operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: CLAMP operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: CLAMP operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    ggml_et_clamp_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+    // op_params layout per ggml.c::ggml_clamp: { min, max } as floats
+    memcpy(&params.min_val, (const float *) node->op_params + 0, sizeof(float));
+    memcpy(&params.max_val, (const float *) node->op_params + 1, sizeof(float));
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (clamp_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_CLAMP)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for CLAMP operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "clamp_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &clamp_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for CLAMP operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("CLAMP", "clamp_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_unary(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for UNARY operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: UNARY operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: UNARY operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    const ggml_unary_op uop     = ggml_get_unary_op(node);
+    const char *        op_name = ggml_unary_op_name(uop);
+
+    ggml_et_unary_params params;
+    params.src0     = *node->src[0];  // F32 input tensor
+    params.dst      = *node;          // F32 output tensor
+    params.unary_op = (int32_t) uop;
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (unary_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_UNARY)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for UNARY/%s operation\n", op_name);
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "unary_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &unary_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for UNARY/%s operation\n", op_name);
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("UNARY", "unary_f32", node, "op=%s", op_name);
+    return kernel_result;
+}
+
+bool ggml_et_op_mul(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    // Delegate to generic element map operation
+    return ggml_et_op_elmap(dev_ctx, node);
+}
+
+bool ggml_et_op_add(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    // Delegate to generic element map operation
+    return ggml_et_op_elmap(dev_ctx, node);
+}
+
+bool ggml_et_op_sub(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    // Delegate to generic element map operation
+    return ggml_et_op_elmap(dev_ctx, node);
+}
+
+bool ggml_et_op_elmap(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for element map operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: Element map operation missing required inputs\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32 || node->src[1]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: Element map operation with unsupported types: dst=%s src0=%s src1=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    const char * op_name = ggml_op_name(node->op);
+
+    ggml_et_elmap_params params;
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.dst  = *node;  // F32 output tensor (op type stored in dst.op)
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (elmap_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, node->op)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for %s operation\n", op_name);
+        }
+    }
+
+    // fprintf(stderr, "ET: el_map s0 [%ld, %ld, %ld, %ld] s1 [%ld, %ld, %ld, %ld]\n",
+    //     node->src[0]->ne[0], node->src[0]->ne[1], node->src[0]->ne[2], node->src[0]->ne[3],
+    //     node->src[1]->ne[0], node->src[1]->ne[1], node->src[1]->ne[2], node->src[1]->ne[3]);
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "el_map_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &elmap_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for %s operation\n", op_name);
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END(op_name, "el_map_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_glu(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    // Validate inputs
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for GLU operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: GLU operation missing required input\n");
+        return false;
+    }
+
+    const bool is_split_mode = node->src[1] != nullptr;
+
+    // Only support F32 (as validated by supports_op)
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32 ||
+        (is_split_mode && node->src[1]->type != GGML_TYPE_F32)) {
+        return false;
+    }
+
+    // Extract GLU operation parameters from op_params
+    int32_t glu_op_type = ggml_get_op_params_i32(node, 0);  // GLU variant (REGLU, GEGLU, SWIGLU, etc.)
+    int32_t swapped     = ggml_get_op_params_i32(node, 1);  // Whether gate/value are swapped
+
+    // Supported variants
+    switch (glu_op_type) {
+        case GGML_GLU_OP_REGLU:
+        case GGML_GLU_OP_GEGLU:
+        case GGML_GLU_OP_SWIGLU:
+        case GGML_GLU_OP_SWIGLU_OAI:
+        case GGML_GLU_OP_GEGLU_ERF:
+        case GGML_GLU_OP_GEGLU_QUICK:
+            break;
+        default:
+            GGML_LOG_ERROR("ET: GLU operation with unsupported variant: %s\n",
+                           ggml_glu_op_name((ggml_glu_op) glu_op_type));
+            return false;
+    }
+
+    // Get GLU operation name for logging
+    const char * glu_op_name = ggml_glu_op_name((ggml_glu_op) glu_op_type);
+
+    // Pack parameters. Single-tensor mode is encoded by zeroing src1.
+    ggml_et_glu_params params = {};
+    params.src0               = *node->src[0];
+    if (is_split_mode) {
+        params.src1 = *node->src[1];
+    }
+    params.dst         = *node;
+    params.glu_op_type = glu_op_type;
+    params.swapped     = swapped;
+    params.alpha       = 0.0f;
+    params.limit       = 0.0f;
+    if (glu_op_type == GGML_GLU_OP_SWIGLU_OAI) {
+        params.alpha = ggml_get_op_params_f32(node, 2);
+        params.limit = ggml_get_op_params_f32(node, 3);
+    }
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (glu_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_GLU)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for %s operation\n", glu_op_name);
+        }
+    }
+
+    // Launch ET kernel
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "glu_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &glu_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for %s operation\n", glu_op_name);
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("GLU", "glu_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_mul_mat(ggml_backend_et_device_context * dev_ctx,
+                        const ggml_tensor *              node,
+                        const ggml_tensor *              add_node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for MUL_MAT operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: MUL_MAT operation missing required inputs\n");
+        return false;
+    }
+
+    // Fused MM+ADD: when add_node is non-NULL the caller has already validated
+    // (Q8_0 weights, F32 acts, exact-shape ADD with stride parity to dst) via
+    // ggml_et_can_fuse({MUL_MAT, ADD}). The kernel writes dst = mm + bias and
+    // the ADD's output replaces MM's as the actual dst.
+    const ggml_tensor * fused_dst   = add_node ? add_node : node;
+    const ggml_tensor * bias_tensor = nullptr;
+    if (add_node) {
+        bias_tensor = (add_node->src[0] == node) ? add_node->src[1] : add_node->src[0];
+    }
+
+    const char * kernel_name;
+    const char * src0_type_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_Q4_0 && node->src[1]->type == GGML_TYPE_F32 &&
+        node->src[1]->ne[1] >= 53 &&      // N >= 53
+        node->src[0]->ne[1] % 16 == 0 &&  // M % TILE_M
+        node->src[0]->ne[0] % 32 == 0) {  // K % BLOCK_K (Q4_0 block)
+
+        // Matrix engine for N >= 53; partial N (via n_cur-1) and errata padding are handled in-kernel.
+        kernel_name    = "mul_mat_Q4_0_matrix_engine";
+        src0_type_name = "Q4_0";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_Q4_0 &&
+               node->src[1]->type == GGML_TYPE_F32) {
+        kernel_name    = "mul_mat_Q4_0";  // N < 53, or M % 16 != 0 or K % 32 != 0
+        src0_type_name = "Q4_0";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_Q8_0 &&
+               node->src[1]->type == GGML_TYPE_F32) {
+        kernel_name    = "mul_mat_Q8_0";
+        src0_type_name = "Q8_0";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F16 &&
+               node->src[1]->type == GGML_TYPE_F16 && node->ne[0] % 16 == 0 && node->src[0]->ne[0] % 16 == 0 &&
+               node->src[0]->ne[1] % 16 == 0 && node->src[1]->ne[0] != 1) {
+        kernel_name    = "mul_mat_f16_matrix_engine";
+        src0_type_name = "F16";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F16 &&
+               (node->src[1]->type == GGML_TYPE_F16 || node->src[1]->type == GGML_TYPE_F32)) {
+        kernel_name    = "mul_mat_f16";
+        src0_type_name = "F16";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32 &&
+               node->src[1]->type == GGML_TYPE_F32 && node->ne[0] % 16 == 0 && node->src[0]->ne[0] % 16 == 0 &&
+               node->src[0]->ne[1] % 16 == 0 && node->src[1]->ne[0] != 1) {  // GEMV is faster with the generic path
+
+        kernel_name    = "mul_mat_f32_matrix_engine";
+        src0_type_name = "F32";
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32 &&
+               (node->src[1]->type == GGML_TYPE_F16 || node->src[1]->type == GGML_TYPE_F32)) {
+        kernel_name    = "mul_mat_f32";
+        src0_type_name = "F32";
+    } else {
+        GGML_LOG_ERROR("ET: MUL_MAT operation with unsupported types: dst=%s src0=%s src1=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    ggml_et_binary_params params;
+    params.src0 = *node->src[0];  // weight matrix
+    params.src1 = *node->src[1];  // activation matrix
+    params.dst  = *fused_dst;     // output (= add_node when fused, else node)
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (mul_mat_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, fused_dst, GGML_OP_MUL_MAT)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for MUL_MAT operation\n");
+        }
+    }
+
+    bool kernel_result;
+    if (node->src[0]->type == GGML_TYPE_Q8_0) {
+        // Q8_0 kernel always takes the extended struct. bias.data is non-NULL
+        // only on the fused path; otherwise the kernel skips the add entirely.
+        ggml_et_mm_q8_params q8_params = {};
+        q8_params.src0                 = params.src0;
+        q8_params.src1                 = params.src1;
+        q8_params.dst                  = params.dst;
+        if (bias_tensor) {
+            q8_params.bias = *bias_tensor;
+        }
+        kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &q8_params, sizeof(q8_params), 0xFFFFFFFF);
+    } else {
+        // Non-Q8 MM kernels don't yet support fused-add; the graph fuse check
+        // already rejects non-Q8 pairs, so add_node is always nullptr here.
+        kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+    }
+
+    // printf("Tensor error:");
+    // if (params.src0.data != NULL)
+    // {
+    //     printf("Ptr OK\n");
+    //     printf("node->data ptr = %p\n", node->data);
+    //     // if (once < 100){
+    //     //     // uint64_t * host_data = (uint64_t *) node->data;
+    //     //     // printf("Tensor error: %lu\n", host_data[0]);
+
+    //     //     // printf("Tensor error:");
+    //     //     once++;
+    //     // }
+    // }
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, fused_dst, &mul_mat_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for MUL_MAT operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    {
+        // Calculate actual FLOPs including batch/sequence dimensions
+        // dst shape: [M, N, ne2, ne3] where M=ne[1], N=ne[0]
+        int64_t m   = node->ne[1];
+        int64_t n   = node->ne[0];
+        int64_t k   = node->src[0]->ne[0];
+        int64_t ne2 = node->ne[2];
+        int64_t ne3 = node->ne[3];
+
+        // Total FLOPs = (batch_size) * M * N * (2*K - 1)
+        // Each MxN matrix-matrix multiply does M*N*(2*K-1) FLOPs
+        // Broadcasting is handled by repeating computation, so count actual operations
+        int64_t batch_size  = ne2 * ne3;
+        int64_t total_flops = batch_size * m * n * (2 * k - 1);
+
+        char kernel_variant[64];
+        snprintf(kernel_variant, sizeof(kernel_variant), "%s_%sx%s", kernel_name, src0_type_name,
+                 ggml_type_name(node->src[1]->type));
+        ET_PERF_END_EXT("MUL_MAT", kernel_variant, node, "flops=%" PRId64, total_flops);
+    }
+    return kernel_result;
+}
+
+bool ggml_et_op_mul_mat_id(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for MUL_MAT_ID operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1] || !node->src[2]) {
+        GGML_LOG_ERROR("ET: MUL_MAT_ID operation missing required inputs\n");
+        return false;
+    }
+
+    const char * kernel_name;
+    const char * src0_type_name;
+
+    // Support Q8_0/Q4_0/F16/F32 x F32 -> F32 matrix multiplication with expert selection
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_Q8_0 && node->src[1]->type == GGML_TYPE_F32 &&
+        node->src[2]->type == GGML_TYPE_I32) {
+        kernel_name    = "mul_mat_id_Q8_0";
+        src0_type_name = "Q8_0";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_Q4_0 &&
+               node->src[1]->type == GGML_TYPE_F32 && node->src[2]->type == GGML_TYPE_I32) {
+        kernel_name    = "mul_mat_id_Q4_0";
+        src0_type_name = "Q4_0";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F16 &&
+               node->src[1]->type == GGML_TYPE_F32 && node->src[2]->type == GGML_TYPE_I32) {
+        kernel_name    = "mul_mat_id_f32";
+        src0_type_name = "F16";
+
+    } else if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32 &&
+               node->src[1]->type == GGML_TYPE_F32 && node->src[2]->type == GGML_TYPE_I32) {
+        kernel_name    = "mul_mat_id_f32";
+        src0_type_name = "F32";
+
+    } else {
+        GGML_LOG_ERROR("ET: MUL_MAT_ID operation with unsupported types: dst=%s src0=%s src1=%s src2=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type), ggml_type_name(node->src[2]->type));
+        return false;
+    }
+
+    // Pack parameters - copy full tensor structures
+    ggml_et_mul_mat_id_params params;
+    params.src0 = *node->src[0];  // Expert weight matrices (Q8_0/F16/F32)
+    params.src1 = *node->src[1];  // Activation matrix (F32)
+    params.src2 = *node->src[2];  // Expert indices (I32)
+    params.dst  = *node;          // Output matrix (F32)
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (mul_mat_id_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_MUL_MAT_ID)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for MUL_MAT_ID operation\n");
+        }
+    }
+
+    // Launch ET kernel
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &mul_mat_id_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for MUL_MAT_ID operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    // Calculate FLOPs (approximate - similar to MUL_MAT but with expert routing overhead)
+    // Each expert computation is similar to a MUL_MAT, but we only compute for selected experts
+    int64_t K             = node->src[0]->ne[0];
+    int64_t M             = node->src[0]->ne[1];
+    int64_t n_expert_used = node->src[2]->ne[0];
+    int64_t batch         = node->src[2]->ne[1];
+
+    int64_t total_flops = batch * n_expert_used * M * (2 * K - 1);
+
+    char kernel_variant[64];
+    snprintf(kernel_variant, sizeof(kernel_variant), "%s_%sx%s", kernel_name, src0_type_name,
+             ggml_type_name(node->src[1]->type));
+    ET_PERF_END_EXT("MUL_MAT_ID", kernel_variant, node, "flops=%" PRId64 "|n_expert=%lld|n_expert_used=%lld",
+                    total_flops, (long long) node->src[0]->ne[2], (long long) n_expert_used);
+
+    return kernel_result;
+}
+
+bool ggml_et_op_rope(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for ROPE operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: ROPE operation missing required inputs\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32 && node->src[1]->type == GGML_TYPE_I32) {
+        kernel_name = "rope_f32";
+    } else {
+        return false;
+    }
+
+    // Pack parameters - copy full tensor structures and op_params
+    ggml_et_rope_params params;
+    params.src0 = *node->src[0];                       // F32 input tensor
+    params.src1 = *node->src[1];                       // I32 position tensor
+    if (node->src[2]) {
+        params.src2 = *node->src[2];                   // F32 frequency factors (optional)
+    } else {
+        memset(&params.src2, 0, sizeof(params.src2));  // Zero if not provided
+    }
+    params.dst = *node;                                // F32 output tensor
+
+    params.rope_params.n_past     = ((const int32_t *) node->op_params)[0];
+    params.rope_params.n_dims     = ((const int32_t *) node->op_params)[1];
+    params.rope_params.mode       = ((const int32_t *) node->op_params)[2];
+    params.rope_params.n_ctx      = ((const int32_t *) node->op_params)[3];
+    params.rope_params.n_ctx_orig = ((const int32_t *) node->op_params)[4];
+    memcpy(&params.rope_params.freq_base, (const int32_t *) node->op_params + 5, sizeof(float));
+    memcpy(&params.rope_params.freq_scale, (const int32_t *) node->op_params + 6, sizeof(float));
+    memcpy(&params.rope_params.ext_factor, (const int32_t *) node->op_params + 7, sizeof(float));
+    memcpy(&params.rope_params.attn_factor, (const int32_t *) node->op_params + 8, sizeof(float));
+    memcpy(&params.rope_params.beta_fast, (const int32_t *) node->op_params + 9, sizeof(float));
+    memcpy(&params.rope_params.beta_slow, (const int32_t *) node->op_params + 10, sizeof(float));
+    if (params.rope_params.mode & GGML_ROPE_TYPE_MROPE) {
+        memcpy(params.rope_params.sections, (const int32_t *) node->op_params + 11, sizeof(int32_t) * 4);
+    } else {
+        memset(params.rope_params.sections, 0, sizeof(params.rope_params.sections));
+    }
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (rope_cpu_compare_config.enabled) {
+        GGML_LOG_DEBUG("ET: Initializing CPU comparison for ROPE operation\n");
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_ROPE)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for ROPE operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &rope_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for ROPE operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("ROPE", kernel_name, node, "mode=0x%x|n_dims=%d|freq_base=%.2f|freq_scale=%.2f",
+                    params.rope_params.mode, params.rope_params.n_dims, (double) params.rope_params.freq_base,
+                    (double) params.rope_params.freq_scale);
+    return kernel_result;
+}
+
+bool ggml_et_op_rms_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for RMS_NORM operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: RMS_NORM operation missing required input\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32) {
+        kernel_name = "rms_norm_f32";
+
+    } else {
+        GGML_LOG_ERROR("ET: RMS_NORM operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    float eps;
+    memcpy(&eps, node->op_params, sizeof(float));
+
+    ggml_et_rms_norm_params params;
+    params.src0 = *node->src[0];  // F32 input tensor
+    params.dst  = *node;          // F32 output tensor
+    params.eps  = eps;            // Epsilon parameter for numerical stability
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (rms_norm_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_RMS_NORM)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for RMS_NORM operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &rms_norm_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for RMS_NORM operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("RMS_NORM", kernel_name, node, "eps=%.6f", (double) eps);
+    return kernel_result;
+}
+
+bool ggml_et_op_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for NORM operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: NORM operation missing required input\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32) {
+        kernel_name = "norm_f32";
+
+    } else {
+        GGML_LOG_ERROR("ET: NORM operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    float eps;
+    memcpy(&eps, node->op_params, sizeof(float));
+
+    ggml_et_norm_params params;
+    params.src0 = *node->src[0];  // F32 input tensor
+    params.dst  = *node;          // F32 output tensor
+    params.eps  = eps;            // Epsilon parameter for numerical stability
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (norm_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_NORM)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for NORM operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &norm_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for NORM operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("NORM", kernel_name, node, "eps=%.6f", (double) eps);
+    return kernel_result;
+}
+
+bool ggml_et_op_l2_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for L2_NORM operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: L2_NORM operation missing required input\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32) {
+        kernel_name = "l2_norm_f32";
+
+    } else {
+        GGML_LOG_ERROR("ET: L2_NORM operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    float eps;
+    memcpy(&eps, node->op_params, sizeof(float));
+
+    ggml_et_l2_norm_params params;
+    params.src0 = *node->src[0];  // F32 input tensor
+    params.dst  = *node;          // F32 output tensor
+    params.eps  = eps;            // Epsilon parameter for numerical stability
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (l2_norm_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_L2_NORM)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for L2_NORM operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &l2_norm_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for L2_NORM operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("L2_NORM", kernel_name, node, "eps=%.6f", (double) eps);
+    return kernel_result;
+}
+
+bool ggml_et_op_group_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for GROUP_NORM operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: GROUP_NORM operation missing required input\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: GROUP_NORM operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    const int32_t n_groups = ggml_get_op_params_i32(node, 0);
+    float         eps;
+    memcpy(&eps, (const float *) node->op_params + 1, sizeof(float));
+
+    ggml_et_group_norm_params params;
+    params.src0     = *node->src[0];
+    params.dst      = *node;
+    params.n_groups = n_groups;
+    params.eps      = eps;
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (group_norm_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_GROUP_NORM)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for GROUP_NORM operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "group_norm_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &group_norm_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for GROUP_NORM operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("GROUP_NORM", "group_norm_f32", node, "eps=%.6f|n_groups=%d", (double) eps, n_groups);
+    return kernel_result;
+}
+
+bool ggml_et_op_im2col(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for IM2COL operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: IM2COL operation missing required inputs\n");
+        return false;
+    }
+
+    const bool supported_types =
+        (node->type == GGML_TYPE_F32 && node->src[1]->type == GGML_TYPE_F32) ||
+        (node->type == GGML_TYPE_F16 && (node->src[1]->type == GGML_TYPE_F16 || node->src[1]->type == GGML_TYPE_F32));
+
+    if (!supported_types) {
+        GGML_LOG_ERROR("ET: IM2COL operation with unsupported types: dst=%s src1=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    ggml_et_im2col_params params;
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.dst  = *node;
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (im2col_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_IM2COL)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for IM2COL operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "im2col", &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &im2col_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for IM2COL operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("IM2COL", "im2col", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_conv_2d(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        return false;
+    }
+    if (!node->src[0] || !node->src[1]) {
+        return false;
+    }
+    if (!node->data || !node->src[0]->data || !node->src[1]->data) {
+        return false;
+    }
+
+    // Kernel constraints (mirror supports_op; recheck here as a guard).
+    const ggml_tensor * flt = node->src[0];  // [Kw, Kh, Cin, Cout]
+    const ggml_tensor * in  = node->src[1];  // [W,  H,  Cin, N]
+    if (node->type != GGML_TYPE_F32 || flt->type != GGML_TYPE_F32 || in->type != GGML_TYPE_F32) {
+        return false;
+    }
+
+    const int32_t s0 = ggml_get_op_params_i32(node, 0);
+    const int32_t s1 = ggml_get_op_params_i32(node, 1);
+    const int32_t p0 = ggml_get_op_params_i32(node, 2);
+    const int32_t p1 = ggml_get_op_params_i32(node, 3);
+    const int32_t d0 = ggml_get_op_params_i32(node, 4);
+    const int32_t d1 = ggml_get_op_params_i32(node, 5);
+
+    if (s0 < 1 || s1 < 1) {
+        return false;
+    }
+    if (d0 != 1 || d1 != 1) {
+        return false;
+    }
+    if (flt->ne[2] % 16 != 0 || flt->ne[3] % 16 != 0) {
+        return false;
+    }
+    if (in->ne[3] != 1) {
+        return false;
+    }
+    if (node->ne[0] <= 0) {
+        return false;  // OW > 0 (any width OK; staging path handles non-16)
+    }
+    (void) p0;
+    (void) p1;
+
+    ggml_et_binary_params params;
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.dst  = *node;
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "conv_2d_f32_me", &params, sizeof(params), 0xFFFFFFFFu);
+
+    ET_PERF_END("CONV_2D", "conv_2d_f32_me", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_softmax(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SOFTMAX operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: SOFTMAX operation missing required input\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32) {
+        kernel_name = "softmax_f32";
+
+    } else {
+        GGML_LOG_ERROR("ET: SOFTMAX operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    // Validate contiguity requirements
+    if (!ggml_is_contiguous(node)) {
+        GGML_LOG_ERROR("ET: SOFTMAX operation requires contiguous destination tensor\n");
+        return false;
+    }
+
+    if (!ggml_is_contiguous(node->src[0])) {
+        GGML_LOG_ERROR("ET: SOFTMAX operation requires contiguous source tensor\n");
+        return false;
+    }
+
+    // Check optional mask tensor
+    if (node->src[1]) {
+        if (node->src[1]->type != GGML_TYPE_F32) {
+            GGML_LOG_ERROR("ET: SOFTMAX operation with unsupported mask type: %s (F32 required)\n",
+                           ggml_type_name(node->src[1]->type));
+            return false;
+        }
+        if (!ggml_is_contiguous(node->src[1])) {
+            GGML_LOG_ERROR("ET: SOFTMAX operation requires contiguous mask tensor\n");
+            return false;
+        }
+    }
+
+    // Check optional sinks tensor
+    if (node->src[2]) {
+        if (node->src[2]->type != GGML_TYPE_F32) {
+            GGML_LOG_ERROR("ET: SOFTMAX operation with unsupported sinks type: %s (F32 required)\n",
+                           ggml_type_name(node->src[2]->type));
+            return false;
+        }
+        if (!ggml_is_contiguous(node->src[2])) {
+            GGML_LOG_ERROR("ET: SOFTMAX operation requires contiguous sinks tensor\n");
+            return false;
+        }
+    }
+
+    // Extract scale and max_bias from op_params
+    float scale    = 1.0f;
+    float max_bias = 0.0f;
+    if (node->op_params) {
+        memcpy(&scale, (const float *) node->op_params + 0, sizeof(float));
+        memcpy(&max_bias, (const float *) node->op_params + 1, sizeof(float));
+    }
+
+    ggml_et_softmax_params params;
+    params.src0 = *node->src[0];                       // F32 input tensor
+    if (node->src[1]) {
+        params.src1 = *node->src[1];                   // F32 mask tensor
+    } else {
+        memset(&params.src1, 0, sizeof(params.src1));  // Zero if no mask
+    }
+    if (node->src[2]) {
+        params.src2 = *node->src[2];                   // F32 sinks tensor
+    } else {
+        memset(&params.src2, 0, sizeof(params.src2));  // Zero if no sinks
+    }
+    params.dst      = *node;                           // F32 output tensor
+    params.scale    = scale;                           // Scale factor
+    params.max_bias = max_bias;                        // ALiBi bias
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (softmax_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_SOFT_MAX)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for SOFTMAX operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &softmax_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for SOFTMAX operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("SOFTMAX", kernel_name, node, "scale=%.6f|max_bias=%.6f|has_mask=%s", (double) scale,
+                    (double) max_bias, node->src[1] ? "yes" : "no");
+    return kernel_result;
+}
+
+bool ggml_et_op_flash_attn_ext(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for FLASH_ATTN_EXT operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1] || !node->src[2]) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT operation missing required inputs\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT requires F32 Q and dst, got dst=%s q=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    // K and V can be F16 or F32
+    if ((node->src[1]->type != GGML_TYPE_F32 && node->src[1]->type != GGML_TYPE_F16) ||
+        (node->src[2]->type != GGML_TYPE_F32 && node->src[2]->type != GGML_TYPE_F16)) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT K/V must be F16 or F32, got k=%s v=%s\n", ggml_type_name(node->src[1]->type),
+                       ggml_type_name(node->src[2]->type));
+        return false;
+    }
+
+    if (node->src[4] != nullptr) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT baseline kernel does not support sinks\n");
+        return false;
+    }
+
+    // Mask is optional; if present must be F16 or F32
+    if (node->src[3] != nullptr && node->src[3]->type != GGML_TYPE_F32 && node->src[3]->type != GGML_TYPE_F16) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT mask must be F16 or F32, got %s\n", ggml_type_name(node->src[3]->type));
+        return false;
+    }
+
+    // Q and dst must be row-contiguous F32
+    if (!ggml_is_contiguous_rows(node) || !ggml_is_contiguous_rows(node->src[0])) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT requires row-contiguous Q and dst\n");
+        return false;
+    }
+
+    if (node->nb[0] != sizeof(float) || node->src[0]->nb[0] != sizeof(float)) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT requires contiguous F32 rows for Q and dst\n");
+        return false;
+    }
+
+    // K/V must have element-sized stride in dim 0
+    const size_t k_elem = node->src[1]->type == GGML_TYPE_F16 ? 2 : 4;
+    const size_t v_elem = node->src[2]->type == GGML_TYPE_F16 ? 2 : 4;
+    if (node->src[1]->nb[0] != k_elem || node->src[2]->nb[0] != v_elem) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT K/V must have element-sized stride in dim 0\n");
+        return false;
+    }
+
+    float scale         = 1.0f;
+    float max_bias      = 0.0f;
+    float logit_softcap = 0.0f;
+    memcpy(&scale, (const float *) node->op_params + 0, sizeof(scale));
+    memcpy(&max_bias, (const float *) node->op_params + 1, sizeof(max_bias));
+    memcpy(&logit_softcap, (const float *) node->op_params + 2, sizeof(logit_softcap));
+
+    if (max_bias != 0.0f || logit_softcap != 0.0f) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT baseline kernel does not support max_bias or logit_softcap\n");
+        return false;
+    }
+
+    const ggml_prec prec = ggml_flash_attn_ext_get_prec(node);
+    if (prec != GGML_PREC_F32 && prec != GGML_PREC_DEFAULT) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT baseline kernel only supports F32 precision\n");
+        return false;
+    }
+
+    // dk must match between Q and K; dv must match between V and dst
+    if (node->src[0]->ne[0] != node->src[1]->ne[0]) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT dk mismatch: Q=%lld K=%lld\n", (long long) node->src[0]->ne[0],
+                       (long long) node->src[1]->ne[0]);
+        return false;
+    }
+
+    if (node->src[2]->ne[0] != node->ne[0]) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT dv mismatch: V=%lld dst=%lld\n", (long long) node->src[2]->ne[0],
+                       (long long) node->ne[0]);
+        return false;
+    }
+
+    if (node->src[2]->ne[0] > 512) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT dv=%lld exceeds maximum 512\n", (long long) node->src[2]->ne[0]);
+        return false;
+    }
+
+    if (node->src[0]->ne[0] > 512) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT dk=%lld exceeds maximum 512\n", (long long) node->src[0]->ne[0]);
+        return false;
+    }
+
+    // GQA: n_head_q must be a multiple of n_head_kv
+    const int64_t nhq = node->src[0]->ne[2];
+    const int64_t nhk = node->src[1]->ne[2];
+    if (nhq % nhk != 0) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT n_head_q (%lld) not divisible by n_head_kv (%lld)\n", (long long) nhq,
+                       (long long) nhk);
+        return false;
+    }
+
+    // K and V must have matching sequence length, heads, and batch dims
+    if (node->src[1]->ne[1] != node->src[2]->ne[1] || node->src[1]->ne[2] != node->src[2]->ne[2] ||
+        node->src[1]->ne[3] != node->src[2]->ne[3]) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT K/V shape mismatch\n");
+        return false;
+    }
+
+    // dst layout checks: [dv, nhq, nq, no]
+    if (node->src[0]->ne[1] != node->ne[2] || node->src[0]->ne[2] != node->ne[1] ||
+        node->src[0]->ne[3] != node->ne[3]) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT dst shape mismatch\n");
+        return false;
+    }
+
+    // Batch dims: Q batch must match K batch
+    if (node->src[0]->ne[3] != node->src[1]->ne[3]) {
+        GGML_LOG_ERROR("ET: FLASH_ATTN_EXT batch dimension mismatch\n");
+        return false;
+    }
+
+    ggml_et_flash_attn_ext_params params;
+    memset(&params, 0, sizeof(params));
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.src2 = *node->src[2];
+    if (node->src[3] != nullptr) {
+        params.mask     = *node->src[3];
+        params.has_mask = 1;
+    }
+    params.dst   = *node;
+    params.scale = scale;
+
+    // Use matrix engine kernel when K/V are F16 and dk is a multiple of 32
+    const char * kernel_name;
+    if (node->src[1]->type == GGML_TYPE_F16 && node->src[2]->type == GGML_TYPE_F16 && (node->src[0]->ne[0] % 32) == 0) {
+        kernel_name = "flash_attn_ext_f16_me";
+    } else {
+        kernel_name = "flash_attn_ext_f32";
+    }
+
+    const bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END_EXT("FLASH_ATTN_EXT", kernel_name, node, "scale=%.6f", (double) scale);
+    return kernel_result;
+}
+
+bool ggml_et_op_get_rows(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for GET_ROWS operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: GET_ROWS operation missing required inputs\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[1]->type == GGML_TYPE_I32 &&
+        (node->src[0]->type == GGML_TYPE_F32 || node->src[0]->type == GGML_TYPE_F16 ||
+         node->src[0]->type == GGML_TYPE_Q4_0 || node->src[0]->type == GGML_TYPE_Q8_0 ||
+         node->src[0]->type == GGML_TYPE_Q4_K)) {
+        kernel_name = "get_rows_f32";
+
+    } else {
+        GGML_LOG_ERROR("ET: GET_ROWS operation with unsupported types: dst=%s src0=%s src1=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    // Validate contiguity requirements
+    if (!ggml_is_contiguous(node)) {
+        GGML_LOG_ERROR("ET: GET_ROWS operation requires contiguous destination tensor\n");
+        return false;
+    }
+
+    if (!ggml_is_contiguous(node->src[0])) {
+        GGML_LOG_ERROR("ET: GET_ROWS operation requires contiguous data tensor\n");
+        return false;
+    }
+
+    if (!ggml_is_contiguous(node->src[1])) {
+        GGML_LOG_ERROR("ET: GET_ROWS operation requires contiguous indices tensor\n");
+        return false;
+    }
+
+    // Validate dimension constraints from ggml implementation
+    if (node->src[0]->ne[2] != node->src[1]->ne[1] || node->src[1]->ne[3] != 1) {
+        GGML_LOG_ERROR(
+            "ET: GET_ROWS operation dimension constraint failed: src0.ne[2]=%lld != src1.ne[1]=%lld or src1.ne[3]=%lld "
+            "!= 1\n",
+            (long long) node->src[0]->ne[2], (long long) node->src[1]->ne[1], (long long) node->src[1]->ne[3]);
+        return false;
+    }
+
+    ggml_et_get_rows_params params;
+    params.src0 = *node->src[0];  // Data tensor (F32 or Q8_0)
+    params.src1 = *node->src[1];  // Indices tensor (I32)
+    params.dst  = *node;          // Output tensor (F32)
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (get_rows_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_GET_ROWS)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for GET_ROWS operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &get_rows_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for GET_ROWS operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("GET_ROWS", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_cont(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    // Validate source tensor exists
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: CONT operation missing source tensor\n");
+        return false;
+    }
+
+    // Validate types match (input and output must be same type)
+    if (node->type != node->src[0]->type) {
+        GGML_LOG_ERROR("ET: CONT operation type mismatch: src=%s dst=%s\n", ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->type));
+        return false;
+    }
+
+    // Validate supported types
+    if (node->type != GGML_TYPE_F32 && node->type != GGML_TYPE_F16) {
+        GGML_LOG_ERROR("ET: CONT operation unsupported type: %s (only F32 and F16 supported)\n",
+                       ggml_type_name(node->type));
+        return false;
+    }
+
+    // Validate contiguity - output must be contiguous, input can be non-contiguous
+    if (!ggml_is_contiguous(node)) {
+        GGML_LOG_ERROR("ET: CONT operation requires contiguous output tensor\n");
+        return false;
+    }
+
+    // Select kernel based on type
+    const char * kernel_name;
+    if (node->type == GGML_TYPE_F32) {
+        kernel_name = "cont_f32";
+    } else if (node->type == GGML_TYPE_F16) {
+        kernel_name = "cont_f16";
+    } else {
+        GGML_LOG_ERROR("ET: CONT operation with unsupported type: %s\n", ggml_type_name(node->type));
+        return false;
+    }
+
+    ggml_et_cont_params params;
+    params.src0 = *node->src[0];  // Input tensor (potentially non-contiguous)
+    params.dst  = *node;          // Output tensor (contiguous)
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (cont_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_CONT)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for CONT operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &cont_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for CONT operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("CONT", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_cumsum(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node || !node->src[0]) {
+        GGML_LOG_ERROR("ET: Invalid parameters for CUMSUM operation\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: CUMSUM operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    const char * kernel_name = "cumsum_f32";
+
+    ggml_et_cumsum_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (cumsum_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_CUMSUM)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for CUMSUM operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &cumsum_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for CUMSUM operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("CUMSUM", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_cpy(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    // CPY copies data from src[0] into the layout of dst (which matches src[1])
+    // For same-type with contiguous dst, this is identical to CONT
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: CPY operation missing source tensor\n");
+        return false;
+    }
+
+    // Scalar / zero-element special path: if any dimension is 0, nothing to copy
+    const int64_t nelements = node->ne[0] * node->ne[1] * node->ne[2] * node->ne[3];
+    if (nelements == 0) {
+        GGML_LOG_DEBUG("ET: CPY no-op (zero elements): ne=[%" PRId64 ",%" PRId64 ",%" PRId64 ",%" PRId64 "]\n",
+                       node->ne[0], node->ne[1], node->ne[2], node->ne[3]);
+        ET_PERF_END("CPY", "noop", node);
+        return true;
+    }
+
+    // Only F32 and F16 supported for dst
+    if (node->type != GGML_TYPE_F32 && node->type != GGML_TYPE_F16) {
+        GGML_LOG_ERROR("ET: CPY unsupported dst type: %s\n", ggml_type_name(node->type));
+        return false;
+    }
+
+    // Select kernel based on src/dst type combination
+    const char * kernel_name;
+    if (node->src[0]->type == GGML_TYPE_F32 && node->type == GGML_TYPE_F32) {
+        kernel_name = "cont_f32";
+    } else if (node->src[0]->type == GGML_TYPE_F16 && node->type == GGML_TYPE_F16) {
+        kernel_name = "cont_f16";
+    } else if (node->src[0]->type == GGML_TYPE_F32 && node->type == GGML_TYPE_F16) {
+        kernel_name = "cpy_f32_f16";
+    } else {
+        GGML_LOG_ERROR("ET: CPY unsupported type combination: src=%s dst=%s\n", ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->type));
+        return false;
+    }
+
+    ggml_et_cont_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+
+    // CPU comparison for debugging
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (cont_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_CPY)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for CPY operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &cont_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for CPY operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("CPY", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_concat(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for CONCAT operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: CONCAT operation missing required inputs\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32 && node->src[1]->type == GGML_TYPE_F32) {
+        kernel_name = "concat_f32";
+
+    } else {
+        GGML_LOG_ERROR("ET: CONCAT operation with unsupported types: dst=%s src0=%s src1=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    int32_t dim;
+    memcpy(&dim, node->op_params, sizeof(int32_t));
+
+    ggml_et_concat_params params;
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.dst  = *node;
+    params.dim  = dim;
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (concat_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_CONCAT)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for CONCAT operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &concat_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for CONCAT operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("CONCAT", kernel_name, node, "dim=%d", dim);
+    return kernel_result;
+}
+
+bool ggml_et_op_repeat(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for REPEAT operation\n");
+        return false;
+    }
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: REPEAT operation missing required input\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    if (node->type == GGML_TYPE_F32 && node->src[0]->type == GGML_TYPE_F32) {
+        // No-op REPEAT (every repeat factor is 1): the output is just a copy
+        // of the input. Route to cont_f32, whose contiguous fast path handles
+        // arbitrary sizes (including those rejected by repeat_f32's gate,
+        // e.g. ne[0]=1).
+        if (ggml_are_same_shape(node->src[0], node)) {
+            kernel_name = "cont_f32";
+        } else {
+            kernel_name = "repeat_f32";
+        }
+
+    } else {
+        GGML_LOG_ERROR("ET: REPEAT operation with unsupported types: dst=%s src0=%s\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type));
+        return false;
+    }
+
+    // ggml_et_cont_params and ggml_et_repeat_params have identical layouts
+    // (just src0 + dst), so the same payload works for either kernel.
+    ggml_et_repeat_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (repeat_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_REPEAT)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for REPEAT operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &repeat_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for REPEAT operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("REPEAT", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_ssm_conv(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node || !node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SSM_CONV operation\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32 || node->src[1]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: SSM_CONV operation with unsupported types: dst=%s src0=%s src1=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    const char * kernel_name = "ssm_conv_f32";
+
+    ggml_et_ssm_conv_params params;
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.dst  = *node;
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (ssm_conv_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_SSM_CONV)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for SSM_CONV operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &ssm_conv_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for SSM_CONV operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("SSM_CONV", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_ssm_scan(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SSM_SCAN operation\n");
+        return false;
+    }
+
+    for (int i = 0; i < 7; ++i) {
+        if (!node->src[i]) {
+            GGML_LOG_ERROR("ET: SSM_SCAN missing required input %d\n", i);
+            return false;
+        }
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32 || node->src[1]->type != GGML_TYPE_F32 ||
+        node->src[2]->type != GGML_TYPE_F32 || node->src[3]->type != GGML_TYPE_F32 ||
+        node->src[4]->type != GGML_TYPE_F32 || node->src[5]->type != GGML_TYPE_F32 ||
+        node->src[6]->type != GGML_TYPE_I32) {
+        GGML_LOG_ERROR("ET: SSM_SCAN operation with unsupported types\n");
+        return false;
+    }
+
+    ggml_et_ssm_scan_params params;
+    params.src0 = *node->src[0];
+    params.src1 = *node->src[1];
+    params.src2 = *node->src[2];
+    params.src3 = *node->src[3];
+    params.src4 = *node->src[4];
+    params.src5 = *node->src[5];
+    params.src6 = *node->src[6];
+    params.dst  = *node;
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "ssm_scan_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END("SSM_SCAN", "ssm_scan_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_rwkv_wkv6(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for RWKV_WKV6 operation\n");
+        return false;
+    }
+
+    // Validate all 6 source tensors exist
+    for (int i = 0; i <= 5; i++) {
+        if (!node->src[i]) {
+            GGML_LOG_ERROR("ET: RWKV_WKV6 operation missing src[%d]\n", i);
+            return false;
+        }
+    }
+
+    if (node->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: RWKV_WKV6 only supports F32, got %s\n", ggml_type_name(node->type));
+        return false;
+    }
+
+    const char * kernel_name = "rwkv_wkv6_f32";
+
+    const int64_t S      = node->src[0]->ne[0];  // head_size
+    const int64_t H      = node->src[0]->ne[1];  // num heads
+    const int64_t T      = node->src[1]->ne[2];  // num tokens
+    const int64_t n_seqs = node->src[5]->ne[1];  // num sequences
+    const int64_t C      = S * H;
+
+    ggml_et_rwkv_wkv6_params params;
+    params.k        = (float *) node->src[0]->data;
+    params.v        = (float *) node->src[1]->data;
+    params.r        = (float *) node->src[2]->data;
+    params.tf       = (float *) node->src[3]->data;
+    params.td       = (float *) node->src[4]->data;
+    params.state_in = (float *) node->src[5]->data;
+    params.dst      = (float *) node->data;
+    params.C        = (int32_t) C;
+    params.H        = (int32_t) H;
+    params.S        = (int32_t) S;
+    params.T        = (int32_t) T;
+    params.n_seqs   = (int32_t) n_seqs;
+
+    // Phase 1: Initialize CPU comparison context
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (rwkv_wkv6_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_RWKV_WKV6)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for RWKV_WKV6 operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &rwkv_wkv6_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for RWKV_WKV6 operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("RWKV_WKV6", kernel_name, node, "S=%d H=%d T=%d n_seqs=%d", (int) S, (int) H, (int) T,
+                    (int) n_seqs);
+    return kernel_result;
+}
+
+bool ggml_et_op_rwkv_wkv7(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for RWKV_WKV7 operation\n");
+        return false;
+    }
+
+    // Validate all 7 source tensors exist
+    for (int i = 0; i <= 6; i++) {
+        if (!node->src[i]) {
+            GGML_LOG_ERROR("ET: RWKV_WKV7 operation missing src[%d]\n", i);
+            return false;
+        }
+    }
+
+    if (node->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: RWKV_WKV7 only supports F32, got %s\n", ggml_type_name(node->type));
+        return false;
+    }
+
+    const char * kernel_name = "rwkv_wkv7_f32";
+
+    const int64_t S      = node->src[2]->ne[0];  // head_size
+    const int64_t H      = node->src[2]->ne[1];  // num heads
+    const int64_t T      = node->src[1]->ne[2];  // num tokens
+    const int64_t n_seqs = node->src[6]->ne[1];  // num sequences
+    const int64_t C      = S * H;
+
+    ggml_et_rwkv_wkv7_params params;
+    params.r        = (float *) node->src[0]->data;
+    params.w        = (float *) node->src[1]->data;
+    params.k        = (float *) node->src[2]->data;
+    params.v        = (float *) node->src[3]->data;
+    params.a        = (float *) node->src[4]->data;
+    params.b        = (float *) node->src[5]->data;
+    params.state_in = (float *) node->src[6]->data;
+    params.dst      = (float *) node->data;
+    params.C        = (int32_t) C;
+    params.H        = (int32_t) H;
+    params.S        = (int32_t) S;
+    params.T        = (int32_t) T;
+    params.n_seqs   = (int32_t) n_seqs;
+
+    // Phase 1: Initialize CPU comparison context
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (rwkv_wkv7_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_RWKV_WKV7)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for RWKV_WKV7 operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &rwkv_wkv7_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for RWKV_WKV7 operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("RWKV_WKV7", kernel_name, node, "S=%d H=%d T=%d n_seqs=%d", (int) S, (int) H, (int) T,
+                    (int) n_seqs);
+    return kernel_result;
+}
+
+static ggml_et_cpu_compare_config gated_delta_net_cpu_compare_config = {
+    /* .enabled = */ false,
+    /* .use_cpu_result = */ false,
+    /* .log_differences = */ true,
+    /* .tolerance = */ 1e-4f,
+    /* .max_log_elements = */ 4096
+};
+
+bool ggml_et_op_gated_delta_net(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for GATED_DELTA_NET operation\n");
+        return false;
+    }
+
+    // Validate all 6 source tensors exist
+    for (int i = 0; i <= 5; i++) {
+        if (!node->src[i]) {
+            GGML_LOG_ERROR("ET: GATED_DELTA_NET operation missing src[%d]\n", i);
+            return false;
+        }
+    }
+
+    if (node->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: GATED_DELTA_NET only supports F32, got %s\n", ggml_type_name(node->type));
+        return false;
+    }
+
+    const char * kernel_name = "gated_delta_net_f32";
+
+    const ggml_tensor * src_q     = node->src[0];
+    const ggml_tensor * src_k     = node->src[1];
+    const ggml_tensor * src_v     = node->src[2];
+    const ggml_tensor * src_g     = node->src[3];
+    const ggml_tensor * src_beta  = node->src[4];
+    const ggml_tensor * src_state = node->src[5];
+
+    const int64_t S_v      = src_v->ne[0];
+    const int64_t H        = src_v->ne[1];
+    const int64_t n_tokens = src_v->ne[2];
+    const int64_t n_seqs   = src_v->ne[3];
+    const int64_t H_q      = src_q->ne[1];
+    const int64_t H_k      = src_k->ne[1];
+    const int64_t n_seqs_q = src_q->ne[3];
+    const int64_t n_seqs_k = src_k->ne[3];
+
+    ggml_et_gated_delta_net_params params;
+    params.q        = *src_q;
+    params.k        = *src_k;
+    params.v        = *src_v;
+    params.g        = *src_g;
+    params.beta     = *src_beta;
+    params.state_in = *src_state;
+    params.dst      = *node;
+    params.S_v      = (int32_t) S_v;
+    params.H        = (int32_t) H;
+    params.H_q      = (int32_t) H_q;
+    params.H_k      = (int32_t) H_k;
+    params.n_tokens = (int32_t) n_tokens;
+    params.n_seqs   = (int32_t) n_seqs;
+    params.n_seqs_q = (int32_t) n_seqs_q;
+    params.n_seqs_k = (int32_t) n_seqs_k;
+    params.kda      = (src_g->ne[0] == S_v) ? 1 : 0;
+    params.K        = ggml_get_op_params_i32(node, 0);
+    params.scale    = 1.0f / sqrtf((float) S_v);
+
+    // CPU comparison for debugging
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (gated_delta_net_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_GATED_DELTA_NET)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for GATED_DELTA_NET operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &gated_delta_net_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for GATED_DELTA_NET operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END_EXT("GATED_DELTA_NET", kernel_name, node, "S_v=%d H=%d n_tokens=%d n_seqs=%d kda=%d", (int) S_v,
+                    (int) H, (int) n_tokens, (int) n_seqs, params.kda);
+    return kernel_result;
+}
+
+bool ggml_et_op_set_rows(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!dev_ctx || !node) {
+        GGML_LOG_ERROR("ET: Invalid parameters for SET_ROWS operation\n");
+        return false;
+    }
+
+    if (!node->src[0] || !node->src[1] || !node->src[2]) {
+        GGML_LOG_ERROR(
+            "ET: SET_ROWS operation missing required inputs (needs src[0]=base, src[1]=indices, src[2]=data)\n");
+        return false;
+    }
+
+    const char * kernel_name;
+
+    // Support F32 data with I64 indices -> F32/F16 output (scatter operation)
+    if (node->src[0]->type == GGML_TYPE_F32 && node->src[1]->type == GGML_TYPE_I64 &&
+        (node->type == GGML_TYPE_F32 || node->type == GGML_TYPE_F16)) {
+        if (node->type == GGML_TYPE_F32 || node->type == GGML_TYPE_F16) {
+            kernel_name = "set_rows_f32";
+        } else {
+            GGML_LOG_ERROR("ET: SET_ROWS unsupported output type: %s\n", ggml_type_name(node->type));
+            return false;
+        }
+
+    } else {
+        GGML_LOG_ERROR("ET: SET_ROWS operation with unsupported types: dst=%s src0=%s src1=%s\n",
+                       ggml_type_name(node->type), ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    // Validate contiguity requirements
+    if (!ggml_is_contiguous_rows(node)) {
+        GGML_LOG_ERROR("ET: SET_ROWS operation requires contiguous-rows destination tensor\n");
+        return false;
+    }
+
+    if (!ggml_is_contiguous_rows(node->src[0])) {
+        GGML_LOG_ERROR("ET: SET_ROWS operation requires contiguous-rows source tensor\n");
+        return false;
+    }
+
+    if (!ggml_is_contiguous(node->src[1])) {
+        GGML_LOG_ERROR("ET: SET_ROWS operation requires contiguous indices tensor\n");
+        return false;
+    }
+
+    // Validate dimension constraints from ggml implementation
+    if (!(node->ne[0] == node->src[0]->ne[0] &&              // same number of columns
+          node->ne[2] == node->src[0]->ne[2] &&              // same batch size
+          node->ne[3] == node->src[0]->ne[3] &&              // same outer dimension
+          node->src[0]->ne[1] == node->src[1]->ne[0] &&      // src rows = index count
+          node->src[0]->ne[2] % node->src[1]->ne[1] == 0 &&  // batch constraint
+          node->src[0]->ne[3] % node->src[1]->ne[2] == 0 &&  // outer constraint
+          node->src[1]->ne[3] == 1)) {                       // indices constraint
+        GGML_LOG_ERROR("ET: SET_ROWS operation dimension constraint failed\n");
+        return false;
+    }
+
+    ggml_et_set_rows_params params;
+    params.src0 = *node->src[0];  // F32 source data tensor
+    params.src1 = *node->src[1];  // I64 indices tensor
+    params.dst  = *node;          // F32/F16 destination tensor
+
+    // Phase 1: Initialize CPU comparison context and copy source buffers (before ET kernel)
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (set_rows_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_SET_ROWS)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for SET_ROWS operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, kernel_name, &params, sizeof(params), 0xFFFFFFFF);
+
+    // Phase 2: Execute CPU computation and compare with ET result (after ET kernel)
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &set_rows_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for SET_ROWS operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("SET_ROWS", kernel_name, node);
+    return kernel_result;
+}
+
+bool ggml_et_op_fill(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    ggml_et_fill_params params;
+    params.dst = *node;
+    memcpy(&params.c, node->op_params, sizeof(float));
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "fill_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END("FILL", "fill_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_diag(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: DIAG operation missing source tensor\n");
+        return false;
+    }
+
+    ggml_et_diag_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "diag_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END("DIAG", "diag_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_tri(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: TRI operation missing source tensor\n");
+        return false;
+    }
+
+    ggml_et_tri_params params;
+    params.src0 = *node->src[0];
+    params.dst  = *node;
+    memcpy(&params.tri_type, node->op_params, sizeof(int32_t));
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "tri_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END("TRI", "tri_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_solve_tri(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: SOLVE_TRI operation missing source tensor(s)\n");
+        return false;
+    }
+
+    ggml_et_solve_tri_params params;
+    params.src0 = *node->src[0];  // A (lower-triangular)
+    params.src1 = *node->src[1];  // B (RHS)
+    params.dst  = *node;          // X (solution)
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "solve_tri_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END("SOLVE_TRI", "solve_tri_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_set(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!node->src[0] || !node->src[1]) {
+        GGML_LOG_ERROR("ET: SET operation missing source tensor(s)\n");
+        return false;
+    }
+
+    const bool   inplace = (bool) ((const int32_t *) node->op_params)[4];
+    const size_t offset  = ((const int32_t *) node->op_params)[3];
+    const size_t nb1     = ((const int32_t *) node->op_params)[0];
+    const size_t nb2     = ((const int32_t *) node->op_params)[1];
+    const size_t nb3     = ((const int32_t *) node->op_params)[2];
+
+    if (!inplace) {
+        GGML_LOG_ERROR("ET: SET only supports inplace (inplace=%d)\n", inplace);
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32 || node->src[1]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: SET only supports F32 (dst=%s src0=%s src1=%s)\n", ggml_type_name(node->type),
+                       ggml_type_name(node->src[0]->type), ggml_type_name(node->src[1]->type));
+        return false;
+    }
+
+    if (!ggml_are_same_shape(node, node->src[0])) {
+        GGML_LOG_ERROR("ET: SET requires same-shape src0 and dst\n");
+        return false;
+    }
+
+    if (!ggml_is_contiguous(node) || !ggml_is_contiguous(node->src[0]) || !ggml_is_contiguous(node->src[1])) {
+        GGML_LOG_ERROR("ET: SET requires contiguous dst, src0, and src1\n");
+        return false;
+    }
+
+    ggml_et_set_params params;
+    params.src1   = *node->src[1];
+    params.dst    = *node;
+    params.nb1    = (int32_t) nb1;
+    params.nb2    = (int32_t) nb2;
+    params.nb3    = (int32_t) nb3;
+    params.offset = (int32_t) offset;
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "set_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    ET_PERF_END("SET", "set_f32", node);
+    return kernel_result;
+}
+
+bool ggml_et_op_pad(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node) {
+    ET_PERF_START();
+
+    if (!node->src[0]) {
+        GGML_LOG_ERROR("ET: PAD operation missing source tensor\n");
+        return false;
+    }
+
+    if (node->type != GGML_TYPE_F32 || node->src[0]->type != GGML_TYPE_F32) {
+        GGML_LOG_ERROR("ET: PAD only supports F32 (src=%s dst=%s)\n", ggml_type_name(node->src[0]->type),
+                       ggml_type_name(node->type));
+        return false;
+    }
+
+    if (!ggml_is_contiguous(node)) {
+        GGML_LOG_ERROR("ET: PAD requires contiguous output tensor\n");
+        return false;
+    }
+
+    if (node->src[0]->nb[0] != sizeof(float)) {
+        GGML_LOG_ERROR("ET: PAD requires element-contiguous src dim0 (nb[0]=%zu)\n", (size_t) node->src[0]->nb[0]);
+        return false;
+    }
+
+    // Extract padding parameters from op_params
+    const int32_t * op_params = (const int32_t *) node->op_params;
+
+    ggml_et_pad_params params;
+    params.src0  = *node->src[0];
+    params.dst   = *node;
+    params.lp[0] = op_params[0];
+    params.rp[0] = op_params[1];
+    params.lp[1] = op_params[2];
+    params.rp[1] = op_params[3];
+    params.lp[2] = op_params[4];
+    params.rp[2] = op_params[5];
+    params.lp[3] = op_params[6];
+    params.rp[3] = op_params[7];
+
+    // v1: no dim0 padding
+    if (params.lp[0] != 0 || params.rp[0] != 0) {
+        GGML_LOG_ERROR("ET: PAD dim0 padding not supported (lp0=%d rp0=%d)\n", params.lp[0], params.rp[0]);
+        return false;
+    }
+
+    ggml_et_cpu_compare_ctx cpu_cmp_ctx;
+    bool                    cpu_comparison_active = false;
+    if (pad_cpu_compare_config.enabled) {
+        if (ggml_et_cpu_compare_init_pre(&cpu_cmp_ctx, node, GGML_OP_PAD)) {
+            cpu_comparison_active = true;
+        } else {
+            GGML_LOG_WARN("ET: Failed to initialize CPU comparison for PAD operation\n");
+        }
+    }
+
+    bool kernel_result = ggml_et_launch_kernel(dev_ctx, "pad_f32", &params, sizeof(params), 0xFFFFFFFF);
+
+    if (cpu_comparison_active) {
+        if (!ggml_et_cpu_compare_compute_and_check(&cpu_cmp_ctx, node, &pad_cpu_compare_config)) {
+            GGML_LOG_WARN("ET: CPU comparison failed for PAD operation\n");
+        }
+        ggml_et_cpu_compare_free(&cpu_cmp_ctx);
+    }
+
+    ET_PERF_END("PAD", "pad_f32", node);
+    return kernel_result;
+}

diff --git a/ggml/src/ggml-et/ggml-et-ops.h b/ggml/src/ggml-et/ggml-et-ops.h
new file mode 100644 (file)
index 0000000..2c7ca7e
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-ops.h
@@ -0,0 +1,392 @@
+#pragma once
+
+#include "ggml-et-common.h"
+#include "ggml.h"
+
+#include <inttypes.h>
+
+// Performance logging macros for ET ops
+// Logs in machine-parseable pipe-delimited format: ET_PERF|field=value|...
+#ifdef ET_PERF_RECORD
+#    define ET_PERF_START() int64_t _et_perf_start = ggml_time_us()
+
+#    define ET_PERF_END(op_name, kernel_name, node)                                                                \
+        do {                                                                                                       \
+            int64_t _et_perf_end      = ggml_time_us();                                                            \
+            int64_t _et_perf_duration = _et_perf_end - _et_perf_start;                                             \
+            GGML_LOG_DEBUG("ET_PERF|op=%s|kernel=%s|duration_us=%" PRId64 "|tensor=%s|shape=[%" PRId64 ",%" PRId64 \
+                           ",%" PRId64 ",%" PRId64 "]|start_us=%" PRId64 "|end_us=%" PRId64 "\n",                  \
+                           op_name, kernel_name, _et_perf_duration, (node)->name, (node)->ne[0], (node)->ne[1],    \
+                           (node)->ne[2], (node)->ne[3], _et_perf_start, _et_perf_end);                            \
+        } while (0)
+
+#    define ET_PERF_END_EXT(op_name, kernel_name, node, fmt, ...)                                                  \
+        do {                                                                                                       \
+            int64_t _et_perf_end      = ggml_time_us();                                                            \
+            int64_t _et_perf_duration = _et_perf_end - _et_perf_start;                                             \
+            GGML_LOG_DEBUG("ET_PERF|op=%s|kernel=%s|duration_us=%" PRId64 "|tensor=%s|shape=[%" PRId64 ",%" PRId64 \
+                           ",%" PRId64 ",%" PRId64 "]|start_us=%" PRId64 "|end_us=%" PRId64 "|" fmt "\n",          \
+                           op_name, kernel_name, _et_perf_duration, (node)->name, (node)->ne[0], (node)->ne[1],    \
+                           (node)->ne[2], (node)->ne[3], _et_perf_start, _et_perf_end, ##__VA_ARGS__);             \
+        } while (0)
+#else
+
+#    define ET_PERF_START() \
+        do {                \
+        } while (0)
+#    define ET_PERF_END_EXT(op_name, kernel_name, node, fmt, ...) \
+        do {                                                      \
+            (void) (node);                                        \
+        } while (0)
+#    define ET_PERF_END(op_name, kernel_name, node) \
+        do {                                        \
+            (void) (node);                          \
+        } while (0)
+
+#endif  // ET_PERF_RECORD
+
+struct ggml_et_binary_params {
+    ggml_tensor src0;
+    ggml_tensor src1;
+    ggml_tensor dst;
+};
+
+// Q8_0 mul_mat with optional residual bias.
+// bias.data == NULL means "no bias" - kernel skips the add.
+// When non-NULL, bias must have the same shape and strides as dst.
+struct ggml_et_mm_q8_params {
+    ggml_tensor src0;
+    ggml_tensor src1;
+    ggml_tensor dst;
+    ggml_tensor bias;
+};
+
+struct ggml_et_im2col_params {
+    ggml_tensor src0;
+    ggml_tensor src1;
+    ggml_tensor dst;
+};
+
+// Element map parameters for embarrassingly parallel binary operations (MUL, ADD, etc.)
+// Operation type is determined by dst->op (GGML_OP_MUL, GGML_OP_ADD, etc.)
+struct ggml_et_elmap_params {
+    ggml_tensor src0;
+    ggml_tensor src1;
+    ggml_tensor dst;
+};
+
+struct ggml_et_rope_settings {
+    int32_t n_past;
+    int32_t n_dims;  // Number of dimensions to apply ROPE to (must be even)
+    int32_t mode;    // ROPE mode, GGML_ROPE_TYPE_*
+    int32_t n_ctx;
+    int32_t n_ctx_orig;
+    float   freq_base;    // Base frequency (usually 10000.0f)
+    float   freq_scale;   // Frequency scaling factor
+    float   ext_factor;   // Extension factor for YaRN
+    float   attn_factor;  // Attention factor for YaRN
+    float   beta_fast;    // Fast beta for YaRN
+    float   beta_slow;    // Slow beta for YaRN
+    int32_t sections[4];  // Sections for multi-modal ROPE
+};
+
+struct ggml_et_rope_params {
+    ggml_tensor           src0;
+    ggml_tensor           src1;
+    ggml_tensor           src2;
+    ggml_tensor           dst;
+    ggml_et_rope_settings rope_params;
+};
+
+struct ggml_et_rms_norm_params {
+    ggml_tensor src0;  // F32 input tensor
+    ggml_tensor dst;   // F32 output tensor
+    float       eps;   // Epsilon parameter for numerical stability
+};
+
+struct ggml_et_norm_params {
+    ggml_tensor src0;  // F32 input tensor
+    ggml_tensor dst;   // F32 output tensor
+    float       eps;   // Epsilon parameter for numerical stability
+};
+
+struct ggml_et_l2_norm_params {
+    ggml_tensor src0;  // F32 input tensor
+    ggml_tensor dst;   // F32 output tensor
+    float       eps;   // Epsilon parameter for numerical stability
+};
+
+struct ggml_et_group_norm_params {
+    ggml_tensor src0;      // F32 input tensor
+    ggml_tensor dst;       // F32 output tensor
+    int32_t     n_groups;  // Number of channel groups
+    float       eps;       // Epsilon parameter for numerical stability
+};
+
+struct ggml_et_glu_params {
+    ggml_tensor src0;         // F32 input tensor A (or combined tensor if src1 is null)
+    ggml_tensor src1;         // F32 input tensor B (null for single tensor mode)
+    ggml_tensor dst;          // F32 output tensor (n/2 columns)
+    int32_t     glu_op_type;  // GLU operation type (REGLU=0, GEGLU=1, SWIGLU=2, etc.)
+    int32_t     swapped;      // Whether gate and value are swapped
+    float       alpha;        // SWIGLU_OAI: sigmoid scaling factor (unused for other variants)
+    float       limit;        // SWIGLU_OAI: clamp limit (unused for other variants)
+};
+
+struct ggml_et_softmax_params {
+    ggml_tensor src0;      // F32 input tensor
+    ggml_tensor src1;      // F32 mask tensor (optional, may be zeroed if not used)
+    ggml_tensor src2;      // F32 sinks tensor (optional, may be zeroed if not used)
+    ggml_tensor dst;       // F32 output tensor
+    float       scale;     // Scale factor
+    float       max_bias;  // Max bias for ALiBi (0.0f if not used)
+};
+
+struct ggml_et_flash_attn_ext_params {
+    ggml_tensor src0;      // Q tensor (F32)
+    ggml_tensor src1;      // K tensor (F32)
+    ggml_tensor src2;      // V tensor (F32)
+    ggml_tensor mask;      // mask tensor (F16 or F32), zeroed when absent
+    ggml_tensor dst;       // Output tensor (F32)
+    float       scale;     // Scale factor applied to QK
+    int32_t     has_mask;  // nonzero if mask is present
+};
+
+struct ggml_et_get_rows_params {
+    ggml_tensor src0;  // Data tensor (F32 or Q8_0)
+    ggml_tensor src1;  // Row indices tensor (I32)
+    ggml_tensor dst;   // Output tensor (F32)
+};
+
+struct ggml_et_cont_params {
+    ggml_tensor src0;  // F32 input tensor (non-contiguous)
+    ggml_tensor dst;   // F32 output tensor (contiguous)
+};
+
+struct ggml_et_concat_params {
+    ggml_tensor src0;  // F32 input tensor 0
+    ggml_tensor src1;  // F32 input tensor 1
+    ggml_tensor dst;   // F32 output tensor
+    int32_t     dim;   // Concatenation dimension
+};
+
+struct ggml_et_repeat_params {
+    ggml_tensor src0;  // F32 input tensor (tile)
+    ggml_tensor dst;   // F32 output tensor (tiled result)
+};
+
+struct ggml_et_fill_params {
+    ggml_tensor dst;  // F32 output tensor (contiguous)
+    float       c;    // Constant value to fill
+};
+
+struct ggml_et_tri_params {
+    ggml_tensor src0;      // F32 input tensor
+    ggml_tensor dst;       // F32 output tensor
+    int32_t     tri_type;  // ggml_tri_type enum value
+};
+
+struct ggml_et_solve_tri_params {
+    ggml_tensor src0;  // A: lower-triangular [n, n, B1, B2]
+    ggml_tensor src1;  // B: RHS [k, n, B1, B2]
+    ggml_tensor dst;   // X: solution [k, n, B1, B2]
+};
+
+struct ggml_et_pad_params {
+    ggml_tensor src0;   // F32 input (may be non-contiguous, nb[0] must == 4)
+    ggml_tensor dst;    // F32 output (contiguous, ne[0] % 16 == 0)
+    int32_t     lp[4];  // left padding per dimension
+    int32_t     rp[4];  // right padding per dimension
+};
+
+struct ggml_et_diag_params {
+    ggml_tensor src0;  // F32 input vector
+    ggml_tensor dst;   // F32 output diagonal matrix
+};
+
+struct ggml_et_ssm_conv_params {
+    ggml_tensor src0;  // conv_x: [d_conv - 1 + n_t, d_inner, n_seqs]
+    ggml_tensor src1;  // conv1d.weight: [d_conv, d_inner]
+    ggml_tensor dst;   // output: [d_inner, n_t, n_seqs]
+};
+
+struct ggml_et_ssm_scan_params {
+    ggml_tensor src0;  // s:   [d_state, head_dim, n_head, n_seqs]
+    ggml_tensor src1;  // x:   [head_dim, n_head, n_seq_tokens, n_seqs]
+    ggml_tensor src2;  // dt:  [n_head, n_seq_tokens, n_seqs]
+    ggml_tensor src3;  // A:   [d_state, n_head] or [1, n_head]
+    ggml_tensor src4;  // B:   [d_state, n_group, n_seq_tokens, n_seqs]
+    ggml_tensor src5;  // C:   [d_state, n_group, n_seq_tokens, n_seqs]
+    ggml_tensor src6;  // ids: [n_seqs] i32
+    ggml_tensor dst;   // [y, final_state] packed output from ggml_ssm_scan()
+};
+
+struct ggml_et_rwkv_wkv6_params {
+    float * k;         // src[0]: [S, H, T]  key
+    float * v;         // src[1]: [S, H, T]  value
+    float * r;         // src[2]: [S, H, T]  receptance
+    float * tf;        // src[3]: [S, H]     time_faaaa (per-head)
+    float * td;        // src[4]: [S, H, T]  time_decay
+    float * state_in;  // src[5]: [S*S*H, n_seqs]  initial state
+    float * dst;       // [C, T + S*n_seqs]  output + state_out
+    int32_t C;         // total channels (S * H)
+    int32_t H;         // number of heads
+    int32_t S;         // head size
+    int32_t T;         // number of tokens
+    int32_t n_seqs;    // number of sequences
+};
+
+struct ggml_et_rwkv_wkv7_params {
+    float * r;         // [S, H, T]  receptance
+    float * w;         // [S, H, T]  decay
+    float * k;         // [S, H, T]  key
+    float * v;         // [S, H, T]  value
+    float * a;         // [S, H, T]  bonus gate
+    float * b;         // [S, H, T]  bonus key
+    float * state_in;  // [S*S*H, n_seqs]  initial state
+    float * dst;       // [C, T + S*n_seqs]  output + state_out
+    int32_t C;         // total channels (S * H)
+    int32_t H;         // number of heads
+    int32_t S;         // head size
+    int32_t T;         // number of tokens
+    int32_t n_seqs;    // number of sequences
+};
+
+struct ggml_et_gated_delta_net_params {
+    ggml_tensor q;         // [S_v, H_q, n_tokens, n_seqs_q]
+    ggml_tensor k;         // [S_v, H_k, n_tokens, n_seqs_k]
+    ggml_tensor v;         // [S_v, H, n_tokens, n_seqs]
+    ggml_tensor g;         // [1 or S_v, H, n_tokens, n_seqs]
+    ggml_tensor beta;      // [1, H, n_tokens, n_seqs]
+    ggml_tensor state_in;  // [S_v*S_v*H, K, n_seqs]
+    ggml_tensor dst;       // [S_v*H, n_tokens*n_seqs + S_v*n_seqs*K]
+    int32_t     S_v;       // head dimension (value size)
+    int32_t     H;         // number of value heads
+    int32_t     H_q;       // number of Q heads
+    int32_t     H_k;       // number of K heads
+    int32_t     n_tokens;  // total tokens
+    int32_t     n_seqs;    // number of sequences (from V)
+    int32_t     n_seqs_q;  // Q sequence count
+    int32_t     n_seqs_k;  // K sequence count
+    int32_t     kda;       // 1 if per-element gate (g_ne0 == S_v), 0 if scalar
+    int32_t     K;         // snapshot slot count
+    float       scale;     // 1/sqrt(S_v)
+};
+
+struct ggml_et_set_rows_params {
+    ggml_tensor src0;  // F32 source data tensor
+    ggml_tensor src1;  // I64 row indices tensor
+    ggml_tensor dst;   // F32/F16 destination tensor
+};
+
+struct ggml_et_set_params {
+    ggml_tensor src1;    // F32 source view to write into dst
+    ggml_tensor dst;     // F32 destination/base tensor
+    int32_t     nb1;     // destination view stride for dim 1
+    int32_t     nb2;     // destination view stride for dim 2
+    int32_t     nb3;     // destination view stride for dim 3
+    int32_t     offset;  // byte offset into destination
+};
+
+struct ggml_et_rms_norm_mul_params {
+    ggml_tensor src0;  // F32 input tensor (to be normalized)
+    ggml_tensor src1;  // F32 weights tensor (element-wise multiply)
+    ggml_tensor dst;   // F32 output tensor
+    float       eps;   // Epsilon for numerical stability
+};
+
+struct ggml_et_mul_mat_id_params {
+    ggml_tensor src0;  // Expert weight matrices (Q8_0/F16/F32) [K, M, n_expert]
+    ggml_tensor src1;  // Activations (F32) [K, n_expert_used, batch]
+    ggml_tensor src2;  // Expert indices (I32) [n_expert_used, batch]
+    ggml_tensor dst;   // Output (F32) [M, n_expert_used, batch, 1]
+};
+
+struct ggml_et_sqr_params {
+    ggml_tensor src0;  // F32 input tensor
+    ggml_tensor dst;   // F32 output tensor
+};
+
+struct ggml_et_unary_params {
+    ggml_tensor src0;      // F32 input tensor
+    ggml_tensor dst;       // F32 output tensor
+    int32_t     unary_op;  // ggml_unary_op enum value
+};
+
+struct ggml_et_sum_rows_params {
+    ggml_tensor src0;  // F32 input tensor [ne00, ne01, ne02, ne03]
+    ggml_tensor dst;   // F32 output tensor [1, ne01, ne02, ne03]
+};
+
+struct ggml_et_mean_params {
+    ggml_tensor src0;  // F32 input tensor [ne00, ne01, ne02, ne03]
+    ggml_tensor dst;   // F32 output tensor [1, ne01, ne02, ne03]
+};
+
+struct ggml_et_clamp_params {
+    ggml_tensor src0;  // F32 input tensor (contiguous)
+    ggml_tensor dst;   // F32 output tensor (contiguous; may alias src0)
+    float       min_val;
+    float       max_val;
+};
+
+struct ggml_et_cumsum_params {
+    ggml_tensor src0;  // F32 input tensor [ne00, ne01, ne02, ne03]
+    ggml_tensor dst;   // F32 output tensor [ne00, ne01, ne02, ne03]
+};
+
+struct ggml_et_scale_params {
+    ggml_tensor src0;   // F32 input tensor
+    ggml_tensor dst;    // F32 output tensor
+    float       scale;  // Scale factor
+    float       bias;   // Bias (additive offset)
+};
+
+bool ggml_et_op_cumsum(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_sqr(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_unary(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_sum_rows(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_mean(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_clamp(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_scale(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_mul(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_add(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_sub(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+// add_node is optional: when non-NULL and the pair (node, add_node) was
+// validated by ggml_et_can_fuse({MUL_MAT, ADD}), the Q8_0 path writes
+// dst = mm(...) + add_node's "other" operand (the bias) in one launch.
+bool ggml_et_op_mul_mat(ggml_backend_et_device_context * dev_ctx,
+                        const ggml_tensor *              node,
+                        const ggml_tensor *              add_node = nullptr);
+bool ggml_et_op_mul_mat_id(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_rope(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_rms_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_l2_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_group_norm(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_glu(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_softmax(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_im2col(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_conv_2d(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_flash_attn_ext(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_get_rows(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_set_rows(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_cont(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_concat(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_repeat(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_rwkv_wkv6(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_rwkv_wkv7(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_cpy(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_gated_delta_net(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_elmap(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_fill(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_diag(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_tri(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_solve_tri(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_pad(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_set(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_ssm_conv(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_ssm_scan(ggml_backend_et_device_context * dev_ctx, const ggml_tensor * node);
+bool ggml_et_op_rms_norm_mul(ggml_backend_et_device_context * dev_ctx,
+                             const ggml_tensor *              rms_norm_node,
+                             const ggml_tensor *              mul_node);

diff --git a/ggml/src/ggml-et/ggml-et-uberkernel-common.h b/ggml/src/ggml-et/ggml-et-uberkernel-common.h
new file mode 100644 (file)
index 0000000..6044473
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et-uberkernel-common.h
@@ -0,0 +1,17 @@
+#pragma once
+
+#include <stdint.h>
+
+struct ggml_et_uberkernel_inst {
+    uint16_t kernel_id;
+    uint16_t flags;
+    uint32_t params_offset;
+    uint32_t params_size;
+};
+
+struct ggml_et_uberkernel_params {
+    uint32_t num_insts;
+    uint32_t inst_stride;
+    uint64_t insts;
+    uint64_t params_blob;
+};

diff --git a/ggml/src/ggml-et/ggml-et.cpp b/ggml/src/ggml-et/ggml-et.cpp
new file mode 100644 (file)
index 0000000..b302090
--- /dev/null
+++ b/ggml/src/ggml-et/ggml-et.cpp
@@ -0,0 +1,1876 @@
+#include "ggml-et.h"
+
+#include "ggml-backend-impl.h"
+#include "ggml-backend.h"
+#include "ggml-et-common.h"
+#include "ggml-et-kernels.h"
+#include "ggml-et-memops.h"
+#include "ggml-et-ops.h"
+#include "ggml-impl.h"
+#include "ggml.h"
+
+#include <stdarg.h>
+
+#include <cstdarg>
+#include <cstdio>
+#include <cstdlib>
+#include <cstring>
+#include <vector>
+
+#if __has_include(<filesystem>)
+#    include <filesystem>
+namespace fs = std::filesystem;
+#elif __has_include(<experimental/filesystem>)
+#    include <experimental/filesystem>
+namespace fs = std::experimental::filesystem;
+#else
+#    error "cannot include the filesystem library"
+#endif
+
+/*
+ * ggml_et_dump_tensor_metadata
+ * @brief prints the metadata of a single tensorf
+ */
+static void ggml_et_dump_tensor_metadata(const ggml_tensor * ggtensor, size_t indent_level, const char * title) {
+    char * spaces = (char *) alloca(indent_level + 1);
+    memset(spaces, ' ', indent_level);
+    spaces[indent_level] = '\0';
+    fprintf(stderr,
+            "%s%s: %s\n"
+            "%s  type: %s\n"
+            "%s  ne: %lld %lld %lld %lld\n"
+            "%s  nb: %zu %zu %zu %zu\n"
+            "%s  op: %s\n"
+            "%s  data: %p\n"
+            "%s  src0: %p\n",
+            spaces, title, ggtensor->name, spaces, ggml_type_name(ggtensor->type), spaces, (long long) ggtensor->ne[0],
+            (long long) ggtensor->ne[1], (long long) ggtensor->ne[2], (long long) ggtensor->ne[3], spaces,
+            ggtensor->nb[0], ggtensor->nb[1], ggtensor->nb[2], ggtensor->nb[3], spaces, ggml_op_name(ggtensor->op),
+            spaces, ggtensor->data, spaces, (void *) ggtensor->src[0]);
+}
+
+/*
+ * ggml_et_dump_operator_metadata
+ * @brief prints the metadata of a single tensor (or operator) including it's input and views
+ */
+static void ggml_et_dump_operator_metadata(const ggml_tensor * ggtensor) {
+    GGML_ASSERT(ggtensor != NULL);
+    ggml_et_dump_tensor_metadata(ggtensor, 0, "GGML tensor");
+    for (int i = 0; i < GGML_MAX_SRC && ggtensor->src[i]; i++) {
+        char arr[16];
+        int  n = snprintf(arr, sizeof(arr), "src[%i]->name", i);
+        GGML_ASSERT((unsigned) n < sizeof(arr) && "printed too much data to stack buffer");
+        ggml_et_dump_tensor_metadata(ggtensor->src[i], 2, arr);
+    }
+    if (ggtensor->view_src) {
+        ggml_et_dump_tensor_metadata(ggtensor, 2, "view_src");
+    }
+}
+
+static struct ggml_et_driver {
+    std::shared_ptr<dev::IDeviceLayer>                device_layer;
+    std::shared_ptr<rt::IRuntime>                     runtime;
+    std::unique_ptr<std::ofstream>                    profile_stream;
+    std::unique_ptr<std::ofstream>                    kernel_id_stream;
+    std::vector<std::pair<std::string, rt::KernelId>> kernel_map;
+    bool                                              profiling_enabled = false;
+} _drv;
+
+// Check at runtime environment variables for paths likely holding ET toolchain with sysemu elf files
+static std::string ggml_et_get_default_et_path() {
+    // List of environment variables to check in order of preference
+    const char * const env_vars[] = { "ET_TOOLCHAIN", "TOOLCHAIN_ROOT" };
+
+    for (const char * var : env_vars) {
+        if (const char * et_path = std::getenv(var)) {
+            if (et_path && *et_path != '\0') {
+                return fs::path(et_path).string();
+            }
+        }
+    }
+
+    // Otherwise assume default
+    return fs::path("/opt/et").string();
+}
+
+// config when using sysemu instead of PCIe hardware device
+// adapted from `ainekko/et-platform/esperanto-tools-libs/tools/src/bench.cpp`
+static inline auto ggml_et_get_default_sysemu_options() {
+    constexpr uint64_t kSysEmuMaxCycles        = std::numeric_limits<uint64_t>::max();
+    constexpr uint64_t kSysEmuMinionShiresMask = 0x1FFFFFFFFu;
+    const std::string  et_path                 = ggml_et_get_default_et_path() + "/";
+
+    emu::SysEmuOptions sysEmuOptions;
+
+    // Construct all paths
+    sysEmuOptions.bootromTrampolineToBL2ElfPath =
+        et_path + "lib/esperanto-fw/BootromTrampolineToBL2/BootromTrampolineToBL2.elf";
+    sysEmuOptions.spBL2ElfPath =
+        et_path + "lib/esperanto-fw/ServiceProcessorBL2/fast-boot/ServiceProcessorBL2_fast-boot.elf";
+    sysEmuOptions.machineMinionElfPath = et_path + "lib/esperanto-fw/MachineMinion/MachineMinion.elf";
+    sysEmuOptions.masterMinionElfPath  = et_path + "lib/esperanto-fw/MasterMinion/MasterMinion.elf";
+    sysEmuOptions.workerMinionElfPath  = et_path + "lib/esperanto-fw/WorkerMinion/WorkerMinion.elf";
+    sysEmuOptions.executablePath       = et_path + "bin/sys_emu";
+
+    // Check that each path has a valid existing non-zero file otherwise emulator just silently hangs
+    const std::vector<std::string> required_files = {
+        sysEmuOptions.bootromTrampolineToBL2ElfPath, sysEmuOptions.spBL2ElfPath,
+        sysEmuOptions.machineMinionElfPath,          sysEmuOptions.masterMinionElfPath,
+        sysEmuOptions.workerMinionElfPath,           sysEmuOptions.executablePath,
+    };
+
+    for (const auto & file : required_files) {
+        if (!fs::exists(file) || fs::file_size(file) == 0) {
+            // Check that each path has a valid existing non-zero file otherwise emulator just silently hangs
+            GGML_LOG_ERROR("ET: Unable to find required sysemu file: %s", file.c_str());
+            GGML_LOG_ERROR("ET: Confirm et-platform is correctly installed at configured path.");
+            abort();
+        }
+    }
+
+    sysEmuOptions.runDir           = (fs::current_path().string() + "/");
+    sysEmuOptions.maxCycles        = kSysEmuMaxCycles;
+    sysEmuOptions.minionShiresMask = kSysEmuMinionShiresMask;
+    sysEmuOptions.puUart0Path      = sysEmuOptions.runDir + "pu_uart0_tx.log";
+    sysEmuOptions.puUart1Path      = sysEmuOptions.runDir + "pu_uart1_tx.log";
+    sysEmuOptions.spUart0Path      = sysEmuOptions.runDir + "spio_uart0_tx.log";
+    sysEmuOptions.spUart1Path      = sysEmuOptions.runDir + "spio_uart1_tx.log";
+    sysEmuOptions.startGdb         = false;
+    sysEmuOptions.memcheck         = false;
+
+    return sysEmuOptions;
+}
+
+// Forward declaration
+static void ggml_et_driver_cleanup();
+
+static bool ggml_et_driver_init() {
+    if (_drv.runtime != nullptr) {
+        assert(_drv.device_layer != nullptr);
+    } else {
+        try {
+#if defined GGML_ET_SYSEMU && GGML_ET_SYSEMU
+            // For emulator device using sysEmuOptions provided by function above enabled compiling with `-DGGML_ET_SYSEMU=ON`
+            _drv.device_layer = dev::IDeviceLayer::createSysEmuDeviceLayer(ggml_et_get_default_sysemu_options());
+#else
+            // For physical PCIe device
+            _drv.device_layer = dev::IDeviceLayer::createPcieDeviceLayer();
+#endif  // GGML_ET_SYSEMU
+
+            _drv.runtime = rt::IRuntime::create(_drv.device_layer);
+
+            // Initialize profiler if requested via environment variable
+            const char * profile_path = getenv("GGML_ET_PROFILE");
+            if (profile_path) {
+                std::string output_path    = std::string(profile_path) + "/et_runtime_trace.json";
+                std::string kernel_id_path = std::string(profile_path) + "/kernel_id.json";
+
+                _drv.profile_stream   = std::make_unique<std::ofstream>(output_path);
+                _drv.kernel_id_stream = std::make_unique<std::ofstream>(kernel_id_path);
+                if (!_drv.profile_stream->is_open()) {
+                    GGML_LOG_ERROR("ET: Failed to open profiling output file: %s", output_path.c_str());
+                    abort();
+                }
+                if (!_drv.kernel_id_stream->is_open()) {
+                    GGML_LOG_ERROR("ET: Failed to open profiling kernel map: %s", kernel_id_path.c_str());
+                    abort();
+                }
+
+                auto * profiler = _drv.runtime->getProfiler();
+                profiler->start(*_drv.profile_stream, rt::IProfiler::OutputType::Json);
+                _drv.profiling_enabled = true;
+                GGML_LOG_INFO("ET: Runtime profiler started (JSON format)");
+
+                // Register cleanup at program exit
+                std::atexit(ggml_et_driver_cleanup);
+            }
+        } catch (const std::exception & e) {
+            GGML_LOG_ERROR("ggml_et: %s", e.what());
+            if (_drv.device_layer != nullptr) {
+                _drv.device_layer.reset();
+            }
+            if (_drv.runtime != nullptr) {
+                _drv.runtime.reset();
+            }
+            return false;
+        }
+    }
+    return true;
+}
+
+static std::shared_ptr<dev::IDeviceLayer> ggml_et_devicelayer() {
+    return _drv.device_layer;
+}
+
+std::shared_ptr<rt::IRuntime> ggml_et_runtime() {
+    return _drv.runtime;
+}
+
+static void ggml_et_driver_cleanup() {
+    if (_drv.profiling_enabled && _drv.runtime) {
+        GGML_LOG_INFO("ET: Stopping runtime profiler");
+        auto * profiler = _drv.runtime->getProfiler();
+        profiler->stop();
+        _drv.profiling_enabled = false;
+
+        if (_drv.profile_stream) {
+            _drv.profile_stream->close();
+            _drv.profile_stream.reset();
+        }
+
+        // Save kernel map
+        if (_drv.kernel_id_stream && !_drv.kernel_map.empty()) {
+            auto & os = *_drv.kernel_id_stream;
+            // XXX: Manual JSON construction. Not pretty but removes dependency
+            os << "{\n";
+            for (size_t i = 0; i < _drv.kernel_map.size(); i++) {
+                os << "  \"" << _drv.kernel_map[i].first << "\": " << (int) _drv.kernel_map[i].second;
+                if (i + 1 < _drv.kernel_map.size()) {
+                    os << ",";
+                }
+                os << "\n";
+            }
+            os << "}\n";
+            _drv.kernel_id_stream->close();
+            _drv.kernel_id_stream.reset();
+        }
+    }
+}
+
+static ggml_backend_dev_t ggml_backend_et_reg_get_device(ggml_backend_reg_t reg, size_t devidx);
+
+static void ggml_backend_et_buffer_free_buffer(ggml_backend_buffer_t buffer) {
+    ggml_backend_et_buffer_context * ctx = (ggml_backend_et_buffer_context *) buffer->context;
+    if (ctx->data != nullptr) {
+        std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+        if (runtime) {
+            runtime->freeDevice(ctx->rtid, static_cast<std::byte *>(ctx->data));
+        }
+    }
+    delete ctx;
+}
+
+static void * ggml_backend_et_buffer_get_base(ggml_backend_buffer_t buffer) {
+    ggml_backend_et_buffer_context * ctx = (ggml_backend_et_buffer_context *) buffer->context;
+    return ctx->data;
+}
+
+static ggml_status ggml_backend_et_buffer_init_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor) {
+    // View tensors share buffer with their view_src, no additional initialization needed
+    if (tensor->view_src != NULL) {
+        return GGML_STATUS_SUCCESS;
+    }
+
+    const size_t original_size = ggml_nbytes(tensor);
+    const size_t padded_size   = ggml_backend_buft_get_alloc_size(buffer->buft, tensor);
+
+    // Clear padding bytes to avoid NaN values
+    // XXX: Martin - do we need this?
+    if (padded_size > original_size) {
+        const size_t padding_size = padded_size - original_size;
+
+        // Get device context to access memops kernel
+        ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) buffer->buft->device->context;
+        if (!dev_ctx) {
+            GGML_LOG_ERROR("ET: Failed to get device context for padding clear");
+            return GGML_STATUS_FAILED;
+        }
+
+        // Use device-side memset kernel for efficient padding clear
+        std::byte * padding_ptr = static_cast<std::byte *>(tensor->data) + original_size;
+        if (!ggml_et_memset(dev_ctx, padding_ptr, 0, padding_size)) {
+            GGML_LOG_ERROR("ET: Failed to clear padding using memset kernel for tensor %s", tensor->name);
+            return GGML_STATUS_FAILED;
+        }
+    }
+
+    return GGML_STATUS_SUCCESS;
+}
+
+static void ggml_backend_et_buffer_set_tensor(ggml_backend_buffer_t buffer,
+                                              ggml_tensor *         tensor,
+                                              const void *          data,
+                                              size_t                offset,
+                                              size_t                size) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        return;
+    }
+
+    // Create short-lived stream for this transfer
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) buffer->buft->device->context;
+    rt::StreamId                     stream  = dev_ctx->default_stream;
+
+    std::byte *       dst_ptr = static_cast<std::byte *>(tensor->data) + offset;
+    const std::byte * src_ptr = static_cast<const std::byte *>(data);
+
+    rt::EventId event = runtime->memcpyHostToDevice(stream, src_ptr, dst_ptr, size, true /*barrier*/);
+
+    runtime->waitForEvent(event);
+}
+
+static void ggml_backend_et_buffer_get_tensor(ggml_backend_buffer_t buffer,
+                                              const ggml_tensor *   tensor,
+                                              void *                data,
+                                              size_t                offset,
+                                              size_t                size) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        return;
+    }
+
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) buffer->buft->device->context;
+    rt::StreamId                     stream  = dev_ctx->default_stream;
+
+    const std::byte * src_ptr = static_cast<const std::byte *>(tensor->data) + offset;
+    std::byte *       dst_ptr = static_cast<std::byte *>(data);
+
+    rt::EventId event = runtime->memcpyDeviceToHost(stream, src_ptr, dst_ptr, size, true /*barrier*/);
+
+    runtime->waitForEvent(event);
+}
+
+static bool ggml_backend_et_buffer_cpy_tensor(ggml_backend_buffer_t buffer,
+                                              const ggml_tensor *   src,
+                                              ggml_tensor *         dst) {
+    GGML_UNUSED(buffer);
+    GGML_UNUSED(src);
+    GGML_UNUSED(dst);
+    return false;
+}
+
+static void ggml_backend_et_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) {
+    ggml_backend_et_buffer_context * ctx = (ggml_backend_et_buffer_context *) buffer->context;
+
+    if (ctx->size == 0 || ctx->data == nullptr) {
+        return;
+    }
+
+    // Get device context to access memops kernel
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) buffer->buft->device->context;
+    if (!dev_ctx) {
+        GGML_LOG_ERROR("ET: Failed to get device context for buffer clear");
+        return;
+    }
+
+    // Use device-side memset kernel for efficient clearing
+    if (!ggml_et_memset(dev_ctx, ctx->data, value, ctx->size)) {
+        GGML_LOG_ERROR("ET: buffer_clear failed using memset kernel");
+        return;
+    }
+
+    GGML_LOG_DEBUG("ET: Buffer cleared successfully using memops kernel");
+}
+
+static const struct ggml_backend_buffer_i ggml_backend_et_buffer_i = {
+    /* .free_buffer     = */ ggml_backend_et_buffer_free_buffer,
+    /* .get_base        = */ ggml_backend_et_buffer_get_base,
+    /* .init_tensor     = */ ggml_backend_et_buffer_init_tensor,
+    /* .memset_tensor   = */ NULL,
+    /* .set_tensor      = */ ggml_backend_et_buffer_set_tensor,
+    /* .get_tensor      = */ ggml_backend_et_buffer_get_tensor,
+    /* .set_tensor_2d   = */ NULL,
+    /* .get_tensor_2d   = */ NULL,
+    /* .cpy_tensor      = */ ggml_backend_et_buffer_cpy_tensor,
+    /* .clear           = */ ggml_backend_et_buffer_clear,
+    /* .reset           = */ NULL,
+};
+
+static const char * ggml_backend_et_buffer_type_get_name(ggml_backend_buffer_type_t buft) {
+    GGML_UNUSED(buft);
+    return GGML_ET_NAME;
+}
+
+static ggml_backend_buffer_t ggml_backend_et_buffer_type_alloc_buffer(ggml_backend_buffer_type_t buft, size_t size) {
+    ggml_backend_et_buffer_type_context * btctx = (ggml_backend_et_buffer_type_context *) buft->context;
+
+    ggml_backend_et_buffer_context * ctx = new ggml_backend_et_buffer_context;
+    ctx->devidx                          = btctx->devidx;
+    ctx->size                            = size;
+
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        delete ctx;
+        return nullptr;
+    }
+
+    std::vector<rt::DeviceId> rtids = runtime->getDevices();
+    if (static_cast<size_t>(btctx->devidx) >= rtids.size()) {
+        delete ctx;
+        return nullptr;
+    }
+    ctx->rtid = rtids[btctx->devidx];
+
+    ctx->data = runtime->mallocDevice(ctx->rtid, size);
+    if (ctx->data == nullptr) {
+        delete ctx;
+        return nullptr;
+    }
+
+    return ggml_backend_buffer_init(buft, ggml_backend_et_buffer_i, ctx, size);
+}
+
+static size_t ggml_backend_et_buffer_type_get_alignment(ggml_backend_buffer_type_t buft) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime || !buft->device) {
+        return GGML_MEM_ALIGN;
+    }
+
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) buft->device->context;
+    rt::DeviceProperties             prop    = runtime->getDeviceProperties(dev_ctx->rtid);
+    return prop.cacheLineSize_;
+}
+
+static size_t ggml_backend_et_buffer_type_get_max_size(ggml_backend_buffer_type_t buft) {
+    if (buft->device) {
+        ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) buft->device->context;
+        return dev_ctx->total_mem;
+    }
+    return SIZE_MAX;
+}
+
+static size_t ggml_backend_et_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) {
+    GGML_UNUSED(buft);
+    return ggml_nbytes_pad(tensor);
+}
+
+static bool ggml_backend_et_buffer_type_is_host(ggml_backend_buffer_type_t buft) {
+    GGML_UNUSED(buft);
+    return false;
+}
+
+static const struct ggml_backend_buffer_type_i ggml_backend_et_buffer_type_i = {
+    /* .get_name         = */ ggml_backend_et_buffer_type_get_name,
+    /* .alloc_buffer     = */ ggml_backend_et_buffer_type_alloc_buffer,
+    /* .get_alignment    = */ ggml_backend_et_buffer_type_get_alignment,
+    /* .get_max_size     = */ ggml_backend_et_buffer_type_get_max_size,
+    /* .get_alloc_size   = */ ggml_backend_et_buffer_type_get_alloc_size,
+    /* .is_host          = */ ggml_backend_et_buffer_type_is_host,
+};
+
+static const char * ggml_backend_et_get_name(ggml_backend_t backend) {
+    GGML_UNUSED(backend);
+    return GGML_ET_NAME;
+}
+
+static void ggml_backend_et_free(ggml_backend_t backend) {
+    ggml_backend_et_context *     et_ctx  = (ggml_backend_et_context *) backend->context;
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+
+    // Clean up kernels on this device before freeing backend
+    ggml_backend_dev_t dev = ggml_backend_et_reg_get_device(ggml_backend_et_reg(), et_ctx->devidx);
+    if (dev && dev->context) {
+        ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+
+        if (_drv.profiling_enabled) {
+            auto kernels = ggml_et_get_loaded_kernels(dev_ctx);
+            _drv.kernel_map.insert(_drv.kernel_map.end(), kernels.begin(), kernels.end());
+        }
+
+        ggml_et_unload_all_kernels(dev_ctx);
+
+        if (runtime) {
+            if (dev_ctx->trace_buffer) {
+                runtime->freeDevice(dev_ctx->rtid, dev_ctx->trace_buffer);
+                dev_ctx->trace_buffer = nullptr;
+            }
+            // Drain any in-flight uberkernel launches before freeing the
+            // device buffers they read from.
+            runtime->waitForStream(dev_ctx->default_stream);
+            for (auto & slot : dev_ctx->uberkernel.slots) {
+                if (slot.device_insts) {
+                    runtime->freeDevice(dev_ctx->rtid, slot.device_insts);
+                    slot.device_insts = nullptr;
+                }
+                if (slot.device_params) {
+                    runtime->freeDevice(dev_ctx->rtid, slot.device_params);
+                    slot.device_params = nullptr;
+                }
+                slot.has_pending = false;
+            }
+        }
+    }
+
+    delete et_ctx;
+    delete backend;
+}
+
+static ggml_backend_buffer_type_t ggml_backend_et_get_default_buffer_type(ggml_backend_t backend) {
+    ggml_backend_et_context * et_ctx = (ggml_backend_et_context *) backend->context;
+
+    return ggml_backend_et_buffer_type(et_ctx->devidx);
+}
+
+static void ggml_backend_et_set_tensor_async(ggml_backend_t backend,
+                                             ggml_tensor *  tensor,
+                                             const void *   data,
+                                             size_t         offset,
+                                             size_t         size) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        return;
+    }
+
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) backend->device->context;
+    rt::StreamId                     stream  = dev_ctx->default_stream;
+
+    std::byte *       dst_ptr = static_cast<std::byte *>(tensor->data) + offset;
+    const std::byte * src_ptr = static_cast<const std::byte *>(data);
+
+    runtime->memcpyHostToDevice(stream, src_ptr, dst_ptr, size, true /*barrier*/);
+}
+
+static void ggml_backend_et_get_tensor_async(ggml_backend_t      backend,
+                                             const ggml_tensor * tensor,
+                                             void *              data,
+                                             size_t              offset,
+                                             size_t              size) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        return;
+    }
+
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) backend->device->context;
+    rt::StreamId                     stream  = dev_ctx->default_stream;
+
+    const std::byte * src_ptr = static_cast<const std::byte *>(tensor->data) + offset;
+    std::byte *       dst_ptr = static_cast<std::byte *>(data);
+
+    runtime->memcpyDeviceToHost(stream, src_ptr, dst_ptr, size, true /*barrier*/);
+}
+
+static bool ggml_backend_et_cpy_tensor_async(ggml_backend_t      backend_src,
+                                             ggml_backend_t      backend_dst,
+                                             const ggml_tensor * src,
+                                             ggml_tensor *       dst) {
+    GGML_UNUSED(backend_src);
+    GGML_UNUSED(backend_dst);
+    GGML_UNUSED(src);
+    GGML_UNUSED(dst);
+    return false;
+}
+
+static void ggml_backend_et_synchronize(ggml_backend_t backend) {
+    std::shared_ptr<rt::IRuntime> runtime = ggml_et_runtime();
+    if (!runtime) {
+        return;
+    }
+
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) backend->device->context;
+    runtime->waitForStream(dev_ctx->default_stream);
+
+    auto errors = runtime->retrieveStreamErrors(dev_ctx->default_stream);
+    if (errors.empty()) {
+        return;
+    }
+    for (const auto & err : errors) {
+        GGML_LOG_ERROR("ET: stream error detected at synchronization point. Code: %d,Type: %d\n", (int) err.errorCode_,
+                       (int) err.errorContext_.value()[0].type_);
+    }
+    abort();
+}
+
+static bool ggml_et_can_fuse(const ggml_cgraph * cgraph, int node_idx, std::initializer_list<ggml_op> ops) {
+    if (!ggml_can_fuse(cgraph, node_idx, ops)) {
+        return false;
+    }
+
+    if (ops.size() == 2 && ops.begin()[0] == GGML_OP_MUL_MAT && ops.begin()[1] == GGML_OP_ADD) {
+        const ggml_tensor * mm  = cgraph->nodes[node_idx];
+        const ggml_tensor * add = cgraph->nodes[node_idx + 1];
+
+        // Only Q8_0 weights x F32 activations -> F32 (the kernel that has
+        // the bias path).  Other MM variants must wait for their own kernel
+        // bias support.
+        if (mm->type != GGML_TYPE_F32 || mm->src[0]->type != GGML_TYPE_Q8_0 || mm->src[1]->type != GGML_TYPE_F32) {
+            return false;
+        }
+
+        // ADD must be F32 and one of its operands must be the MM output.
+        if (add->type != GGML_TYPE_F32) {
+            return false;
+        }
+        if (add->src[0] != mm && add->src[1] != mm) {
+            return false;
+        }
+
+        const ggml_tensor * bias = (add->src[0] == mm) ? add->src[1] : add->src[0];
+
+        if (bias->type != GGML_TYPE_F32) {
+            return false;
+        }
+
+        // No broadcasting: bias shape must equal MM output shape.
+        for (int i = 0; i < GGML_MAX_DIMS; ++i) {
+            if (bias->ne[i] != mm->ne[i]) {
+                return false;
+            }
+        }
+
+        // Bias and dst must be contiguous and have identical strides - the
+        // kernel uses dst-style offset arithmetic against bias's nb[].
+        if (!ggml_is_contiguous(bias) || !ggml_is_contiguous(mm)) {
+            return false;
+        }
+        for (int i = 0; i < GGML_MAX_DIMS; ++i) {
+            if ((int64_t) bias->nb[i] != (int64_t) add->nb[i]) {
+                return false;
+            }
+        }
+    }
+
+    if (ops.size() == 2 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) {
+        const ggml_tensor * rms_norm = cgraph->nodes[node_idx];
+        const ggml_tensor * mul      = cgraph->nodes[node_idx + 1];
+
+        // ET only supports F32
+        if (rms_norm->src[0]->type != GGML_TYPE_F32 || mul->type != GGML_TYPE_F32) {
+            return false;
+        }
+
+        // Identify the weights tensor (the MUL operand that isn't rms_norm output)
+        const ggml_tensor * weights = (mul->src[0] == rms_norm) ? mul->src[1] : mul->src[0];
+
+        if (weights->type != GGML_TYPE_F32) {
+            return false;
+        }
+
+        // Both inputs must be contiguous (ET hardware requirement)
+        if (!ggml_is_contiguous(rms_norm->src[0]) || !ggml_is_contiguous_rows(weights)) {
+            return false;
+        }
+
+        // ET requires cache-aligned rows (ne[0] % 16 == 0)
+        if (rms_norm->src[0]->ne[0] % 16 != 0 || weights->ne[0] % 16 != 0) {
+            return false;
+        }
+
+        // Fused kernel doesn't handle dim-0 broadcasting
+        if (weights->ne[0] != rms_norm->src[0]->ne[0]) {
+            return false;
+        }
+    }
+
+    return true;
+}
+
+static ggml_status ggml_backend_et_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) {
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) backend->device->context;
+    ggml_et_uberkernel_begin_graph(&dev_ctx->uberkernel);
+
+    for (int i = 0; i < cgraph->n_nodes; i++) {
+        ggml_tensor * node = cgraph->nodes[i];
+
+        if (node->op == GGML_OP_NONE || node->op == GGML_OP_VIEW || node->op == GGML_OP_RESHAPE ||
+            node->op == GGML_OP_PERMUTE || node->op == GGML_OP_TRANSPOSE) {
+            continue;
+        }
+
+        // --- Fusion checks (before regular dispatch) ---
+        if (ggml_et_can_fuse(cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL })) {
+            ggml_et_op_rms_norm_mul(dev_ctx, node, cgraph->nodes[i + 1]);
+            i++;  // skip the MUL node
+            continue;
+        }
+        if (ggml_et_can_fuse(cgraph, i, { GGML_OP_MUL_MAT, GGML_OP_ADD })) {
+            ggml_et_op_mul_mat(dev_ctx, node, cgraph->nodes[i + 1]);
+            i++;  // skip the ADD node
+            continue;
+        }
+
+        switch (node->op) {
+            case GGML_OP_SQR:
+                ggml_et_op_sqr(dev_ctx, node);
+                break;
+
+            case GGML_OP_UNARY:
+                ggml_et_op_unary(dev_ctx, node);
+                break;
+
+            case GGML_OP_SUM_ROWS:
+                ggml_et_op_sum_rows(dev_ctx, node);
+                break;
+
+            case GGML_OP_MEAN:
+                ggml_et_op_mean(dev_ctx, node);
+                break;
+
+            case GGML_OP_CLAMP:
+                ggml_et_op_clamp(dev_ctx, node);
+                break;
+
+            case GGML_OP_MUL:
+                ggml_et_op_mul(dev_ctx, node);
+                break;
+
+            case GGML_OP_ADD:
+                ggml_et_op_add(dev_ctx, node);
+                break;
+
+            case GGML_OP_SUB:
+                ggml_et_op_sub(dev_ctx, node);
+                break;
+
+            case GGML_OP_CUMSUM:
+                ggml_et_op_cumsum(dev_ctx, node);
+                break;
+
+            case GGML_OP_MUL_MAT:
+                ggml_et_op_mul_mat(dev_ctx, node);
+                break;
+
+            case GGML_OP_MUL_MAT_ID:
+                ggml_et_op_mul_mat_id(dev_ctx, node);
+                break;
+
+            case GGML_OP_ROPE:
+                ggml_et_op_rope(dev_ctx, node);
+                break;
+
+            case GGML_OP_RMS_NORM:
+                ggml_et_op_rms_norm(dev_ctx, node);
+                break;
+
+            case GGML_OP_NORM:
+                ggml_et_op_norm(dev_ctx, node);
+                break;
+
+            case GGML_OP_L2_NORM:
+                ggml_et_op_l2_norm(dev_ctx, node);
+                break;
+
+            case GGML_OP_GROUP_NORM:
+                ggml_et_op_group_norm(dev_ctx, node);
+                break;
+
+            case GGML_OP_SCALE:
+                ggml_et_op_scale(dev_ctx, node);
+                break;
+
+            case GGML_OP_GLU:
+                ggml_et_op_glu(dev_ctx, node);
+                break;
+
+            case GGML_OP_SOFT_MAX:
+                ggml_et_op_softmax(dev_ctx, node);
+                break;
+
+            case GGML_OP_IM2COL:
+                ggml_et_op_im2col(dev_ctx, node);
+                break;
+
+            case GGML_OP_CONV_2D:
+                ggml_et_op_conv_2d(dev_ctx, node);
+                break;
+
+            case GGML_OP_FLASH_ATTN_EXT:
+                ggml_et_op_flash_attn_ext(dev_ctx, node);
+                break;
+
+            case GGML_OP_GET_ROWS:
+                ggml_et_op_get_rows(dev_ctx, node);
+                break;
+
+            case GGML_OP_CONT:
+                ggml_et_op_cont(dev_ctx, node);
+                break;
+
+            case GGML_OP_CPY:
+                ggml_et_op_cpy(dev_ctx, node);
+                break;
+
+            case GGML_OP_CONCAT:
+                ggml_et_op_concat(dev_ctx, node);
+                break;
+
+            case GGML_OP_REPEAT:
+                ggml_et_op_repeat(dev_ctx, node);
+                break;
+
+            case GGML_OP_SSM_CONV:
+                ggml_et_op_ssm_conv(dev_ctx, node);
+                break;
+
+            case GGML_OP_SSM_SCAN:
+                ggml_et_op_ssm_scan(dev_ctx, node);
+                break;
+
+            case GGML_OP_PAD:
+                ggml_et_op_pad(dev_ctx, node);
+                break;
+
+            case GGML_OP_SET_ROWS:
+                ggml_et_op_set_rows(dev_ctx, node);
+                break;
+
+            case GGML_OP_FILL:
+                ggml_et_op_fill(dev_ctx, node);
+                break;
+
+            case GGML_OP_DIAG:
+                ggml_et_op_diag(dev_ctx, node);
+                break;
+
+            case GGML_OP_TRI:
+                ggml_et_op_tri(dev_ctx, node);
+                break;
+
+            case GGML_OP_SOLVE_TRI:
+                ggml_et_op_solve_tri(dev_ctx, node);
+                break;
+
+            case GGML_OP_SET:
+                ggml_et_op_set(dev_ctx, node);
+                break;
+
+            case GGML_OP_RWKV_WKV6:
+                ggml_et_op_rwkv_wkv6(dev_ctx, node);
+                break;
+
+            case GGML_OP_RWKV_WKV7:
+                ggml_et_op_rwkv_wkv7(dev_ctx, node);
+                break;
+
+            case GGML_OP_GATED_DELTA_NET:
+                ggml_et_op_gated_delta_net(dev_ctx, node);
+                break;
+
+            default:
+                ggml_et_uberkernel_abort_graph(&dev_ctx->uberkernel);
+                GGML_LOG_ERROR("ET: Unsupported operation in graph: %s", ggml_op_name(node->op));
+                return GGML_STATUS_FAILED;
+        }
+
+        if (ggml_et_uberkernel_failed(&dev_ctx->uberkernel)) {
+            ggml_et_uberkernel_abort_graph(&dev_ctx->uberkernel);
+            return GGML_STATUS_FAILED;
+        }
+    }
+
+    if (!ggml_et_uberkernel_end_graph(dev_ctx)) {
+        ggml_et_uberkernel_abort_graph(&dev_ctx->uberkernel);
+        return GGML_STATUS_FAILED;
+    }
+
+    return GGML_STATUS_SUCCESS;
+}
+
+// Check that elements within each row are contiguous (nb[0] == type_size).
+// Higher-dim strides can be arbitrary - kernels navigate them via byte offsets.
+static bool et_ggml_is_row_contiguous(const ggml_tensor * t) {
+    return t->nb[0] == ggml_type_size(t->type);
+}
+
+static bool ggml_backend_et_device_supports_op(ggml_backend_dev_t dev, const ggml_tensor * op) {
+    GGML_UNUSED(dev);
+
+    bool supported = false;
+    switch (op->op) {
+        case GGML_OP_CUMSUM:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->src[0]->nb[0] == sizeof(float) && ggml_is_contiguous(op);
+            break;
+        case GGML_OP_SQR:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->ne[0] % 16 == 0 && ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]);
+            break;
+        case GGML_OP_SUM_ROWS:
+            // dst has ne[0]=1, src0 row length must be cache-aligned
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->src[0]->ne[0] % 16 == 0 && ggml_is_contiguous(op->src[0]);
+            break;
+        case GGML_OP_MEAN:
+            // Kernel handles arbitrary ne00 (per-row alignment guard with
+            // scalar tail), so no row-length divisibility constraint here.
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op->src[0]);
+            break;
+        case GGML_OP_CLAMP:
+            // Element-wise; kernel distributes by cache lines and handles a
+            // scalar tail, so any contiguous F32 size is fine - including the
+            // 1x1x1x1 scalar case.
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]);
+            break;
+        case GGML_OP_UNARY:
+            // Only require dim-0 contiguity (nb[0] == sizeof(float)). Higher
+            // dims may be arbitrarily strided views; the kernel walks per-row
+            // using all four nb[] values. See unary_f32.c entry_point.
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                ggml_nelements(op) % 16 == 0 && op->nb[0] == sizeof(float) && op->src[0]->nb[0] == sizeof(float)) {
+                switch (ggml_get_unary_op(op)) {
+                    case GGML_UNARY_OP_ABS:
+                    case GGML_UNARY_OP_SGN:
+                    case GGML_UNARY_OP_NEG:
+                    case GGML_UNARY_OP_STEP:
+                    case GGML_UNARY_OP_TANH:
+                    case GGML_UNARY_OP_ELU:
+                    case GGML_UNARY_OP_RELU:
+                    case GGML_UNARY_OP_SIGMOID:
+                    case GGML_UNARY_OP_GELU:
+                    case GGML_UNARY_OP_GELU_QUICK:
+                    case GGML_UNARY_OP_SILU:
+                    case GGML_UNARY_OP_HARDSWISH:
+                    case GGML_UNARY_OP_HARDSIGMOID:
+                    case GGML_UNARY_OP_EXP:
+                    case GGML_UNARY_OP_EXPM1:
+                    case GGML_UNARY_OP_SOFTPLUS:
+                    case GGML_UNARY_OP_GELU_ERF:
+                    case GGML_UNARY_OP_FLOOR:
+                    case GGML_UNARY_OP_CEIL:
+                    case GGML_UNARY_OP_ROUND:
+                    case GGML_UNARY_OP_TRUNC:
+                        supported = true;
+                        break;
+                    default:
+                        break;
+                }
+            }
+            break;
+        case GGML_OP_MUL:
+        case GGML_OP_ADD:
+        case GGML_OP_SUB:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                        op->src[1]->type == GGML_TYPE_F32 && op->nb[0] == sizeof(float) &&
+                        op->src[0]->nb[0] == sizeof(float) &&
+                        (op->src[1]->nb[0] == sizeof(float) || op->src[1]->ne[0] == 1) &&
+                        op->nb[1] == op->ne[0] * sizeof(float);
+            break;
+        case GGML_OP_MUL_MAT:
+            // Support Q8_0 x F32 -> F32, F16 x F32 -> F32, F16 x F16 -> F32, and F32 x F32 -> F32 matrix multiplication
+            // Stride requirements: first dimension must be contiguous for all tensors
+            if (op->type == GGML_TYPE_F32 &&
+                ((op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32) ||
+                 (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F16)) &&
+                op->ne[0] % 16 == 0 &&          // dst row length for tensor-store path
+                op->src[0]->ne[1] % 16 == 0 &&  // m
+                op->src[0]->ne[0] % 16 == 0 &&  // k
+                ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) {
+                // Special path for the FP32 TensorFMA kernel
+                // Limitation - generic kernels can tolerate non-cache-aligned dst rows
+                // because they publish each output element atomically. The matrix
+                // engine path still uses tiled tensor stores, so keep dst rows aligned.
+                // The m edge is difficult to do because of the 4 conseqtive load hardware limitation
+                // And the k edge is impossible because that is encoded as `stride & 0xFFFFFFFFFFC0ULL` which becomes 0 for stride 16 (4x FP32) :(
+                // FIXME: Right now this overwrites the mul_mat_f32 kernel - whatever. Fix later. Demo code
+                supported = true;
+            } else if (op->type == GGML_TYPE_F32 && op->src[0] &&
+                       (op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32) && op->src[1] &&
+                       (op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32)) {
+                // Check first dimension contiguity requirements
+                bool src0_first_dim_contiguous = (op->src[0]->nb[0] == ggml_type_size(op->src[0]->type));
+                bool src1_first_dim_contiguous = (op->src[1]->nb[0] == ggml_type_size(op->src[1]->type));
+                bool dst_first_dim_contiguous  = (op->nb[0] == sizeof(float));
+
+                // Check destination stride ordering (only for dimensions with ne > 1)
+                bool dst_properly_ordered = true;
+                for (int d = 0; d < 3; d++) {
+                    if (op->ne[d] > 1 && op->ne[d + 1] > 1 && op->nb[d] > op->nb[d + 1]) {
+                        dst_properly_ordered = false;
+                    }
+                }
+
+                supported = src0_first_dim_contiguous && src1_first_dim_contiguous && dst_first_dim_contiguous &&
+                            dst_properly_ordered;
+            } else if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_Q8_0 && op->src[1] &&
+                       op->src[1]->type == GGML_TYPE_F32) {
+                // Keep the existing quantized path constraints separate from the
+                // relaxed non-quant generic fallback.
+                bool src0_first_dim_contiguous = (op->src[0]->nb[0] == ggml_type_size(op->src[0]->type));
+                bool src1_first_dim_contiguous = (op->src[1]->nb[0] == ggml_type_size(op->src[1]->type));
+                bool dst_first_dim_contiguous  = (op->nb[0] == sizeof(float));
+
+                bool dst_properly_ordered = true;
+                for (int d = 0; d < 3; d++) {
+                    if (op->ne[d] > 1 && op->ne[d + 1] > 1 && op->nb[d] > op->nb[d + 1]) {
+                        dst_properly_ordered = false;
+                    }
+                }
+
+                supported = src0_first_dim_contiguous && src1_first_dim_contiguous && dst_first_dim_contiguous &&
+                            dst_properly_ordered;
+
+            } else if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_Q4_0 && op->src[1] &&
+                       op->src[1]->type == GGML_TYPE_F32) {
+                // Keep the existing quantized path constraints separate from the
+                // relaxed non-quant generic fallback.
+                bool src0_first_dim_contiguous = (op->src[0]->nb[0] == ggml_type_size(op->src[0]->type));
+                bool src1_first_dim_contiguous = (op->src[1]->nb[0] == ggml_type_size(op->src[1]->type));
+                bool dst_first_dim_contiguous  = (op->nb[0] == sizeof(float));
+
+                bool dst_properly_ordered = true;
+                for (int d = 0; d < 3; d++) {
+                    if (op->ne[d] > 1 && op->ne[d + 1] > 1 && op->nb[d] > op->nb[d + 1]) {
+                        dst_properly_ordered = false;
+                    }
+                }
+
+                supported = src0_first_dim_contiguous && src1_first_dim_contiguous && dst_first_dim_contiguous &&
+                            dst_properly_ordered;
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_MUL_MAT_ID:
+            // Support MUL_MAT_ID for Mixture of Experts: (Q8_0/Q4_0/F16/F32) x F32 -> F32 with I32 expert indices
+            // src0 (as): [K, M, n_expert] - expert weight matrices (can be quantized)
+            // src1 (b):  [K, n_expert_used, batch] - activations (F32)
+            // src2 (ids): [n_expert_used, batch] - expert selection indices (I32)
+            // dst: [M, n_expert_used, batch, 1] - output (F32)
+            if (op->type == GGML_TYPE_F32 && op->src[0] &&
+                (op->src[0]->type == GGML_TYPE_Q8_0 || op->src[0]->type == GGML_TYPE_Q4_0 ||
+                 op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32) &&
+                op->src[1] && op->src[1]->type == GGML_TYPE_F32 && op->src[2] && op->src[2]->type == GGML_TYPE_I32) {
+                // Check first dimension contiguity requirements (matching CPU backend)
+                bool src0_first_dim_contiguous = (op->src[0]->nb[0] == ggml_type_size(op->src[0]->type));
+                bool src1_first_dim_contiguous = (op->src[1]->nb[0] == ggml_type_size(op->src[1]->type));
+                bool src2_first_dim_contiguous = (op->src[2]->nb[0] == ggml_type_size(op->src[2]->type));
+                bool dst_first_dim_contiguous  = (op->nb[0] == sizeof(float));
+
+                // Check destination stride ordering (only for dimensions with ne > 1)
+                bool dst_properly_ordered = true;
+                for (int d = 0; d < 3; d++) {
+                    if (op->ne[d] > 1 && op->ne[d + 1] > 1 && op->nb[d] > op->nb[d + 1]) {
+                        dst_properly_ordered = false;
+                    }
+                }
+
+                // Validate tensor dimension constraints from GGML definition
+                bool dims_valid = (op->src[0]->ne[3] == 1) &&  // as is 3d (one matrix per expert)
+                                  (op->src[1]->ne[3] == 1) &&  // b is 3d
+                                  (op->src[2]->ne[2] == 1 && op->src[2]->ne[3] == 1) &&  // ids is 2d
+                                  (op->src[2]->ne[1] == op->src[1]->ne[2]) &&    // must have expert list per b row
+                                  (op->src[0]->ne[0] == op->src[1]->ne[0]) &&    // K dimension must match
+                                  (op->src[2]->ne[0] % op->src[1]->ne[1] == 0);  // can broadcast
+
+                supported = src0_first_dim_contiguous && src1_first_dim_contiguous && src2_first_dim_contiguous &&
+                            dst_first_dim_contiguous && dst_properly_ordered && dims_valid;
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_ROPE:
+            // Support F32 x I32 -> F32 RoPE for the modes implemented by rope_f32.
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                op->src[1]->type == GGML_TYPE_I32 && ggml_is_contiguous(op) && et_ggml_is_row_contiguous(op->src[0])) {
+                const int  mode             = ggml_get_op_params_i32(op, 2);
+                const int  ndims            = ggml_get_op_params_i32(op, 1);
+                const bool is_normal        = mode == GGML_ROPE_TYPE_NORMAL;
+                const bool is_neox          = mode == GGML_ROPE_TYPE_NEOX;
+                const bool is_imrope        = mode == GGML_ROPE_TYPE_IMROPE;
+                const bool zero_view_offset = op->src[0]->view_src == nullptr || op->src[0]->view_offs == 0;
+                const bool has_sections = ggml_get_op_params_i32(op, 11) > 0 || ggml_get_op_params_i32(op, 12) > 0 ||
+                                          ggml_get_op_params_i32(op, 13) > 0;
+
+                supported =
+                    zero_view_offset && ndims <= 512 &&
+                    (is_normal || (is_neox && ndims % 16 == 0) || (is_imrope && ndims % 16 == 0 && has_sections));
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_RMS_NORM:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->ne[0] % 16 == 0 && ggml_is_contiguous(op) && et_ggml_is_row_contiguous(op->src[0]);
+            break;
+        case GGML_OP_NORM:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->ne[0] % 16 == 0 && ggml_is_contiguous(op) && et_ggml_is_row_contiguous(op->src[0]);
+            break;
+        case GGML_OP_L2_NORM:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->ne[0] % 16 == 0 && ggml_is_contiguous(op) && et_ggml_is_row_contiguous(op->src[0]);
+            break;
+        case GGML_OP_GROUP_NORM:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op) && et_ggml_is_row_contiguous(op->src[0]) &&
+                        ggml_get_op_params_i32(op, 0) > 0;
+            break;
+        case GGML_OP_IM2COL:
+            supported = op->src[0] && op->src[1] &&
+                        ((op->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32) ||
+                         (op->type == GGML_TYPE_F16 &&
+                          (op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32))) &&
+                        ggml_is_contiguous(op) && ggml_is_contiguous(op->src[1]) &&
+                        op->nb[0] == ggml_type_size(op->type) && op->src[1]->nb[0] == ggml_type_size(op->src[1]->type);
+            break;
+        case GGML_OP_CONV_2D:
+            {
+                // First-cut conv_2d_f32_me kernel constraints. Anything outside
+                // this falls back to CPU (it's a strict subset on purpose).
+                if (!op->src[0] || !op->src[1]) {
+                    supported = false;
+                    break;
+                }
+                if (op->type != GGML_TYPE_F32 || op->src[0]->type != GGML_TYPE_F32 ||
+                    op->src[1]->type != GGML_TYPE_F32) {
+                    supported = false;
+                    break;
+                }
+                if (!ggml_is_contiguous(op) || !ggml_is_contiguous(op->src[0]) || !ggml_is_contiguous(op->src[1])) {
+                    supported = false;
+                    break;
+                }
+
+                const ggml_tensor * flt = op->src[0];  // [Kw, Kh, Cin, Cout]
+                const ggml_tensor * in  = op->src[1];  // [W,  H,  Cin, N]
+                const int32_t       s0  = ggml_get_op_params_i32(op, 0);
+                const int32_t       s1  = ggml_get_op_params_i32(op, 1);
+                const int32_t       p0  = ggml_get_op_params_i32(op, 2);
+                const int32_t       p1  = ggml_get_op_params_i32(op, 3);
+                const int32_t       d0  = ggml_get_op_params_i32(op, 4);
+                const int32_t       d1  = ggml_get_op_params_i32(op, 5);
+
+                const int64_t Kw   = flt->ne[0];
+                const int64_t Kh   = flt->ne[1];
+                const int64_t Cin  = flt->ne[2];
+                const int64_t Cout = flt->ne[3];
+                const int64_t H    = in->ne[1];
+                (void) in->ne[0];
+
+                if (s0 < 1 || s1 < 1 || !(d0 == 1 && d1 == 1) || Cin % 16 != 0 || Cout % 16 != 0 || in->ne[3] != 1) {
+                    supported = false;
+                    break;
+                }
+                const int64_t OW = op->ne[0];
+                const int64_t OH = op->ne[1];
+                if (OW <= 0 || OH <= 0) {
+                    supported = false;
+                    break;
+                }
+                (void) p0;
+                (void) p1;
+
+                // Mirror the kernel's sizing:
+                //   if K_TILES * per_KT_bytes <= budget: 1 buffer, n_chunks=1
+                //   else: 2 buffers (double-buffer), shrink chunk_KT until
+                //         2*chunk_KT*per_KT_bytes <= budget.
+                const int64_t Hp            = H + 2 * p1;
+                const int64_t OW_pad        = (OW + 15) & ~15;
+                const int64_t Wp_a          = OW_pad;
+                const bool    need_stage    = (OW % 16 != 0);
+                const int64_t stage_bytes   = need_stage ? (Cout * OH * OW_pad * 4) : 0;
+                const int64_t L2SCP_BUDGET  = 1500 * 1024;
+                // Per-hart partial-TenC scratch (mirrors kernel MAX_TILES_PER_HART=2):
+                // 32 minions x 2 tiles x 1024 bytes = 64 KB per shire.
+                const int64_t scratch_bytes = 32 * 2 * 16 * 16 * 4;
+                const int64_t budget        = L2SCP_BUDGET - stage_bytes - scratch_bytes;
+                const int64_t per_KT_bytes  = Kh * Kw * Cout * 16 * 4 + Kw * 16 * Hp * Wp_a * 4;
+                const int64_t K_TILES       = Cin / 16;
+
+                int64_t chunk_KT_calc;
+                int64_t n_chunks_calc;
+                if (K_TILES * per_KT_bytes <= budget) {
+                    chunk_KT_calc = K_TILES;
+                    n_chunks_calc = 1;
+                } else {
+                    chunk_KT_calc = K_TILES;
+                    while (chunk_KT_calc > 1 && 2 * chunk_KT_calc * per_KT_bytes > budget) {
+                        chunk_KT_calc--;
+                    }
+                    while (chunk_KT_calc > 1 && K_TILES % chunk_KT_calc != 0) {
+                        chunk_KT_calc--;
+                    }
+                    if (chunk_KT_calc < 1) {
+                        supported = false;
+                        break;
+                    }
+                    n_chunks_calc = K_TILES / chunk_KT_calc;
+                }
+
+                if (n_chunks_calc > 1) {
+                    const int64_t M_TILES     = Cout / 16;
+                    const int64_t w_tiles     = (OW + 15) / 16;
+                    const int64_t total_tiles = OH * w_tiles * M_TILES;
+                    // MAX_TILES_PER_HART = 2 (mirrors kernel constant).
+                    const int64_t max_workers = (need_stage ? 32 : 1024) * 2;
+                    if (total_tiles > max_workers) {
+                        supported = false;
+                        break;
+                    }
+                }
+
+                supported = true;
+                break;
+            }
+        case GGML_OP_SCALE:
+            // F32 contiguous, total elements must be cache line aligned (16 floats)
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]) && (ggml_nelements(op) % 16 == 0);
+            break;
+        case GGML_OP_GLU:
+            // Note: we only require row-wise contiguity (ggml_is_contiguous_1) so that
+            // strided views over a packed up_proj tensor (the common split-GLU layout)
+            // are accepted. The kernel walks rows via nb[1] strides, so the inner
+            // dimension just needs to be densely packed.
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                ggml_nelements(op) % 16 == 0 && ggml_is_contiguous_1(op) && ggml_is_contiguous_1(op->src[0])) {
+                // Check GLU variant - support SWIGLU, SWIGLU_OAI, GEGLU, GEGLU_ERF, GEGLU_QUICK, REGLU
+                ggml_glu_op glu_type          = ggml_get_glu_op(op);
+                const bool  supported_variant = glu_type == GGML_GLU_OP_SWIGLU || glu_type == GGML_GLU_OP_SWIGLU_OAI ||
+                                                glu_type == GGML_GLU_OP_GEGLU || glu_type == GGML_GLU_OP_GEGLU_ERF ||
+                                                glu_type == GGML_GLU_OP_GEGLU_QUICK || glu_type == GGML_GLU_OP_REGLU;
+
+                if (op->src[1]) {
+                    supported = supported_variant && op->src[1]->type == GGML_TYPE_F32 &&
+                                ggml_is_contiguous_1(op->src[1]) && op->src[0]->ne[0] == op->ne[0] &&
+                                op->src[1]->ne[0] == op->ne[0];
+                } else {
+                    supported = supported_variant && op->src[0]->ne[0] == 2 * op->ne[0];
+                }
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_SOFT_MAX:
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]) && op->src[0]->ne[0] > 1) {
+                // Check optional mask tensor (F32 only)
+                if (op->src[1]) {
+                    supported = op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[1]);
+                    if (!supported) {
+                        break;
+                    }
+                }
+                // Check optional sinks tensor (F32 only)
+                if (op->src[2]) {
+                    supported = op->src[2]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[2]);
+                } else {
+                    supported = true;
+                }
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_SSM_SCAN:
+            supported = op->type == GGML_TYPE_F32 && ggml_is_contiguous(op) && op->src[0] &&
+                        op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]) && op->src[1] &&
+                        op->src[1]->type == GGML_TYPE_F32 && op->src[2] && op->src[2]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op->src[2]) && op->src[3] && op->src[3]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op->src[3]) && op->src[4] && op->src[4]->type == GGML_TYPE_F32 &&
+                        op->src[5] && op->src[5]->type == GGML_TYPE_F32 && op->src[6] &&
+                        op->src[6]->type == GGML_TYPE_I32 && ggml_is_contiguous(op->src[6]) &&
+                        op->src[1]->nb[0] == sizeof(float) && op->src[4]->nb[0] == sizeof(float) &&
+                        op->src[5]->nb[0] == sizeof(float) &&
+                        op->src[1]->nb[1] == (size_t) op->src[1]->ne[0] * sizeof(float) &&
+                        op->src[4]->nb[1] == (size_t) op->src[4]->ne[0] * sizeof(float) &&
+                        op->src[5]->nb[1] == (size_t) op->src[5]->ne[0] * sizeof(float) &&
+                        op->src[0]->ne[0] == op->src[4]->ne[0] && op->src[0]->ne[1] == op->src[1]->ne[0] &&
+                        op->src[0]->ne[2] == op->src[1]->ne[1] && op->src[1]->ne[2] == op->src[2]->ne[1] &&
+                        op->src[1]->ne[3] == op->src[2]->ne[2] && op->src[4]->ne[2] == op->src[1]->ne[2] &&
+                        op->src[4]->ne[3] == op->src[1]->ne[3] && ggml_are_same_shape(op->src[4], op->src[5]) &&
+                        op->src[6]->ne[0] == op->src[1]->ne[3] && op->src[3]->ne[1] == op->src[1]->ne[1] &&
+                        (op->src[3]->ne[0] == 1 || op->src[3]->ne[0] == op->src[0]->ne[0]) &&
+                        (op->src[1]->ne[1] % op->src[4]->ne[1] == 0);
+            break;
+        case GGML_OP_FLASH_ATTN_EXT:
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                (op->src[1]->type == GGML_TYPE_F32 || op->src[1]->type == GGML_TYPE_F16) && op->src[2] &&
+                (op->src[2]->type == GGML_TYPE_F32 || op->src[2]->type == GGML_TYPE_F16) && op->src[4] == nullptr &&
+                ggml_is_contiguous_rows(op) && ggml_is_contiguous_rows(op->src[0])) {
+                float max_bias      = 0.0f;
+                float logit_softcap = 0.0f;
+                memcpy(&max_bias, (const float *) op->op_params + 1, sizeof(max_bias));
+                memcpy(&logit_softcap, (const float *) op->op_params + 2, sizeof(logit_softcap));
+
+                const ggml_prec prec = ggml_flash_attn_ext_get_prec(op);
+
+                // Mask must be F16 or F32 if present
+                bool mask_ok = (op->src[3] == nullptr) || (op->src[3]->type == GGML_TYPE_F32) ||
+                               (op->src[3]->type == GGML_TYPE_F16);
+
+                // GQA: n_head_q must be a multiple of n_head_kv
+                const int64_t nhq = op->src[0]->ne[2];
+                const int64_t nhk = op->src[1]->ne[2];
+
+                // K/V row stride must match element size
+                const size_t k_elem = op->src[1]->type == GGML_TYPE_F16 ? 2 : 4;
+                const size_t v_elem = op->src[2]->type == GGML_TYPE_F16 ? 2 : 4;
+
+                // Only support matrix engine path (F16 K/V, dk%32==0);
+                // mask scalar F32 fallback to get baseline perf readings
+                const bool me_eligible = op->src[1]->type == GGML_TYPE_F16 && op->src[2]->type == GGML_TYPE_F16 &&
+                                         (op->src[0]->ne[0] % 32) == 0;
+
+                supported = me_eligible && mask_ok && (prec == GGML_PREC_F32 || prec == GGML_PREC_DEFAULT) &&
+                            max_bias == 0.0f && logit_softcap == 0.0f && op->src[0]->nb[0] == sizeof(float) &&
+                            op->src[1]->nb[0] == k_elem && op->src[2]->nb[0] == v_elem && op->nb[0] == sizeof(float) &&
+                            op->src[0]->ne[0] == op->src[1]->ne[0] &&  // dk matches
+                            op->src[2]->ne[0] == op->ne[0] &&          // dv matches
+                            op->src[2]->ne[0] <= 512 &&                // dv limit
+                            op->src[0]->ne[0] <= 512 &&                // dk limit
+                            nhq % nhk == 0 &&                          // GQA ratio is integer
+                            op->src[0]->ne[1] == op->ne[2] && op->src[0]->ne[2] == op->ne[1] &&
+                            op->src[0]->ne[3] == op->ne[3] && op->src[1]->ne[1] == op->src[2]->ne[1] &&
+                            op->src[1]->ne[2] == op->src[2]->ne[2] && op->src[1]->ne[3] == op->src[2]->ne[3] &&
+                            op->src[0]->ne[3] == op->src[1]->ne[3];
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_GET_ROWS:
+            // Support F32/F16/Q4_0/Q8_0/Q4_K data with I32 indices -> F32 output
+            if (op->type == GGML_TYPE_F32 && op->src[0] &&
+                (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16 ||
+                 op->src[0]->type == GGML_TYPE_Q4_0 || op->src[0]->type == GGML_TYPE_Q8_0 ||
+                 op->src[0]->type == GGML_TYPE_Q4_K) &&
+                op->src[1] && op->src[1]->type == GGML_TYPE_I32 && ggml_is_contiguous(op) &&
+                ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) {
+                // Validate dimension constraints from ggml implementation
+                supported = (op->src[0]->ne[2] == op->src[1]->ne[1]) && (op->src[1]->ne[3] == 1);
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_CONT:
+            // Support F32->F32 and F16->F16 CONT operations (rearrange non-contiguous to contiguous)
+            if ((op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16) && op->src[0] &&
+                op->src[0]->type == op->type && ggml_is_contiguous(op)) {
+                // Defensive check: ensure dst and src0 are not aliased (separate buffers)
+                // While GGML design currently guarantees this, check for future robustness
+                if (op->data && op->src[0]->data && op->data == op->src[0]->data) {
+                    GGML_LOG_WARN("ET: CONT operation detected aliased tensors (dst == src0), unsupported");
+                    supported = false;
+                } else {
+                    supported = true;
+                }
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_CPY:
+            // CPY copies src[0] data into dst layout (same as CONT for same-type)
+            // Special path: zero-element tensors (scalars) are accepted as no-ops
+            if (op->src[0]) {
+                const int64_t nelements = op->ne[0] * op->ne[1] * op->ne[2] * op->ne[3];
+                if (nelements == 0) {
+                    // Zero-element / scalar no-op case - always supported
+                    supported = true;
+                } else if ((op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16) && op->src[0]->type == op->type &&
+                           ggml_is_contiguous(op)) {
+                    // Same-type with contiguous dst - reuse CONT kernel
+                    if (op->data && op->src[0]->data && op->data == op->src[0]->data) {
+                        GGML_LOG_WARN("ET: CPY operation detected aliased tensors, unsupported");
+                        supported = false;
+                    } else {
+                        supported = true;
+                    }
+                } else if (op->type == GGML_TYPE_F16 && op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op)) {
+                    // F32 -> F16 conversion copy
+                    supported = true;
+                } else {
+                    supported = false;
+                }
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_CONCAT:
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op)) {
+                const int32_t dim = ((const int32_t *) op->op_params)[0];
+                if (dim == 0 && op->src[0]->ne[0] % 16 == 0 && op->src[1]->ne[0] % 16 == 0 &&
+                    ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) {
+                    // Fast dim==0 path: both source row segments are cacheline-aligned
+                    // and contiguous, so the kernel can use vector row copies.
+                    supported = true;
+                } else if (dim == 0 && ((op->src[0]->nb[0] % sizeof(float) == 0) || op->src[0]->ne[0] == 1) &&
+                           ((op->src[1]->nb[0] % sizeof(float) == 0) || op->src[1]->ne[0] == 1)) {
+                    // Slow dim==0 path: scalar, stride-aware copies for non-contiguous
+                    // or non-aligned source row segments. Destination remains contiguous.
+                    supported = true;
+                } else if (op->ne[0] % 16 == 0 && op->src[0]->ne[0] % 16 == 0 && op->src[1]->ne[0] % 16 == 0 &&
+                           ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) {
+                    // Dim >= 1 path: full aligned row copies from one source or the other.
+                    supported = true;
+                }
+            }
+            break;
+        case GGML_OP_SSM_CONV:
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                        op->src[1]->type == GGML_TYPE_F32 && op->src[0]->nb[0] == sizeof(float) &&
+                        op->src[1]->nb[0] == sizeof(float) && op->src[0]->nb[1] == op->src[0]->ne[0] * sizeof(float) &&
+                        op->src[1]->nb[1] == op->src[1]->ne[0] * sizeof(float) && ggml_is_contiguous(op) &&
+                        op->src[1]->ne[1] == op->src[0]->ne[1] && op->ne[0] == op->src[0]->ne[1] &&
+                        op->ne[1] == op->src[0]->ne[0] - op->src[1]->ne[0] + 1 && op->ne[2] == op->src[0]->ne[2];
+            break;
+        case GGML_OP_PAD:
+            // F32 zero-pad only, no dim0 padding, dst contiguous
+            // ne[0] must be CL-aligned (% 16 == 0) or evenly divide a CL (16 % ne[0] == 0)
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                ggml_is_contiguous(op) && (op->ne[0] % 16 == 0 || 16 % op->ne[0] == 0) &&
+                op->src[0]->nb[0] == sizeof(float)) {
+                const int32_t lp0      = ((const int32_t *) op->op_params)[0];
+                const int32_t rp0      = ((const int32_t *) op->op_params)[1];
+                const bool    circular = (bool) ((const int32_t *) op->op_params)[8];
+                if (lp0 == 0 && rp0 == 0 && !circular) {
+                    supported = true;
+                } else {
+                    supported = false;
+                }
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_REPEAT:
+            // Two acceptable shapes:
+            //   1. No-op REPEAT (src and dst have identical shape): dispatched
+            //      to cont_f32, which handles arbitrary contiguous sizes.
+            //   2. Real REPEAT via repeat_f32 kernel: dst ne[0] cacheline-aligned,
+            //      src0 ne[0] cacheline-aligned or 1, dst.ne[i] % src0.ne[i] == 0.
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]) && ggml_are_same_shape(op->src[0], op)) {
+                supported = true;
+            } else if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                       (op->src[0]->ne[0] == 1 || op->src[0]->ne[0] % 16 == 0) && op->ne[0] % 16 == 0 &&
+                       ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]) && op->ne[0] % op->src[0]->ne[0] == 0 &&
+                       op->ne[1] % op->src[0]->ne[1] == 0 && op->ne[2] % op->src[0]->ne[2] == 0 &&
+                       op->ne[3] % op->src[0]->ne[3] == 0) {
+                supported = true;
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_FILL:
+            // F32 contiguous, ne[0] cacheline-aligned for SIMD fill
+            supported = op->type == GGML_TYPE_F32 && ggml_is_contiguous(op) && op->ne[0] % 16 == 0;
+            break;
+        case GGML_OP_DIAG:
+            // F32 contiguous dst, src0 is 1D vector [N,1,...], dst is [N,N,...]
+            // ne[0] must be cacheline-aligned for SIMD zeroing
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        op->ne[0] % 16 == 0 && op->ne[0] == op->ne[1] && op->src[0]->ne[0] == op->ne[0] &&
+                        op->src[0]->ne[1] == 1 && ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]);
+            break;
+        case GGML_OP_TRI:
+            // F32 contiguous, same shape in/out
+            // Kernel handles arbitrary ne[0] with aligned fast path + scalar fallback
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&
+                        ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]);
+            break;
+        case GGML_OP_SOLVE_TRI:
+            // F32 contiguous, A square, shapes compatible
+            // Only lower-triangular left-side non-unit variant
+            // Require k % 16 == 0 for cache-line-safe column parallelism
+            supported = op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                        op->src[1]->type == GGML_TYPE_F32 && op->src[0]->ne[0] == op->src[0]->ne[1] &&
+                        op->src[0]->ne[1] == op->src[1]->ne[1] && op->src[1]->ne[0] % 16 == 0 &&
+                        ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]);
+            break;
+        case GGML_OP_SET:
+            // Minimal useful support: inplace F32 SET of a contiguous src1 view into
+            // a contiguous dst/base tensor using explicit destination view strides.
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op) && ggml_is_contiguous(op->src[0]) &&
+                ggml_is_contiguous(op->src[1]) && ggml_are_same_shape(op, op->src[0]) && op->src[1]->ne[0] % 16 == 0) {
+                const bool   inplace = (bool) ((const int32_t *) op->op_params)[4];
+                const size_t nb1     = ((const int32_t *) op->op_params)[0];
+                const size_t nb2     = ((const int32_t *) op->op_params)[1];
+                const size_t nb3     = ((const int32_t *) op->op_params)[2];
+                const size_t offset  = ((const int32_t *) op->op_params)[3];
+                const size_t nb0     = ggml_element_size(op);
+                const size_t im0     = op->src[1]->ne[0] == 0 ? 0 : op->src[1]->ne[0] - 1;
+                const size_t im1     = op->src[1]->ne[1] == 0 ? 0 : op->src[1]->ne[1] - 1;
+                const size_t im2     = op->src[1]->ne[2] == 0 ? 0 : op->src[1]->ne[2] - 1;
+                const size_t im3     = op->src[1]->ne[3] == 0 ? 0 : op->src[1]->ne[3] - 1;
+
+                const bool view_bounds_ok = offset + im0 * nb0 + im1 * nb1 + im2 * nb2 + im3 * nb3 <= ggml_nbytes(op);
+
+                const bool cacheline_aligned =
+                    (nb1 % 64 == 0) && (nb2 % 64 == 0) && (nb3 % 64 == 0) && (offset % 64 == 0);
+
+                supported = inplace && view_bounds_ok && cacheline_aligned;
+            }
+            break;
+        case GGML_OP_RWKV_WKV6:
+            // F32 contiguous, head_size must be multiple of 8 for vectorization
+            // 6 sources: k, v, r, tf, td, state
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                op->src[1]->type == GGML_TYPE_F32 && op->src[2] && op->src[2]->type == GGML_TYPE_F32 && op->src[3] &&
+                op->src[3]->type == GGML_TYPE_F32 && op->src[4] && op->src[4]->type == GGML_TYPE_F32 && op->src[5] &&
+                op->src[5]->type == GGML_TYPE_F32 && op->src[0]->ne[0] % 8 == 0 &&  // head_size multiple of 8
+                ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]) && ggml_is_contiguous(op->src[2]) &&
+                ggml_is_contiguous(op->src[3]) && ggml_is_contiguous(op->src[4]) && ggml_is_contiguous(op->src[5])) {
+                supported = true;
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_RWKV_WKV7:
+            // F32 contiguous, head_size must be multiple of 8 for vectorization
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] &&
+                op->src[1]->type == GGML_TYPE_F32 && op->src[2] && op->src[2]->type == GGML_TYPE_F32 && op->src[3] &&
+                op->src[3]->type == GGML_TYPE_F32 && op->src[4] && op->src[4]->type == GGML_TYPE_F32 && op->src[5] &&
+                op->src[5]->type == GGML_TYPE_F32 && op->src[6] && op->src[6]->type == GGML_TYPE_F32 &&
+                op->src[2]->ne[0] % 8 == 0 &&  // head_size multiple of 8
+                ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]) && ggml_is_contiguous(op->src[2]) &&
+                ggml_is_contiguous(op->src[3]) && ggml_is_contiguous(op->src[4]) && ggml_is_contiguous(op->src[5]) &&
+                ggml_is_contiguous(op->src[6])) {
+                supported = true;
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_GATED_DELTA_NET:
+            // F32, S_v must be multiple of 8 for vectorization
+            // q, k, v may be row-contiguous with strided higher dimensions.
+            // g, beta, state stay contiguous.
+            if (op->type == GGML_TYPE_F32 && op->src[0] && op->src[0]->type == GGML_TYPE_F32 &&  // q
+                op->src[1] && op->src[1]->type == GGML_TYPE_F32 &&                               // k
+                op->src[2] && op->src[2]->type == GGML_TYPE_F32 &&                               // v
+                op->src[3] && op->src[3]->type == GGML_TYPE_F32 &&                               // g
+                op->src[4] && op->src[4]->type == GGML_TYPE_F32 &&                               // beta
+                op->src[5] && op->src[5]->type == GGML_TYPE_F32 &&                               // state
+                op->src[2]->ne[0] % 8 == 0 &&                                                    // S_v multiple of 8
+                (op->src[3]->ne[0] == 1 || op->src[3]->ne[0] == op->src[2]->ne[0]) &&  // g is scalar or per-element
+                op->src[4]->ne[0] == 1 &&                                              // beta is scalar per position
+                et_ggml_is_row_contiguous(op->src[0]) && et_ggml_is_row_contiguous(op->src[1]) &&
+                et_ggml_is_row_contiguous(op->src[2]) && ggml_is_contiguous(op->src[3]) &&
+                ggml_is_contiguous(op->src[4]) && ggml_is_contiguous(op->src[5])) {
+                supported = true;
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_VIEW:
+        case GGML_OP_PERMUTE:
+        case GGML_OP_TRANSPOSE:
+        case GGML_OP_RESHAPE:
+            // Metadata-only no-ops, accept any type
+            supported = true;
+            break;
+        case GGML_OP_SET_ROWS:
+            // Support F32 data with I64 indices -> F16/F32 output (scatter operation)
+            if (op->src[0] && op->src[0]->type == GGML_TYPE_F32 && op->src[1] && op->src[1]->type == GGML_TYPE_I64 &&
+                (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16) && ggml_is_contiguous_rows(op) &&
+                ggml_is_contiguous_rows(op->src[0]) && ggml_is_contiguous(op->src[1])) {
+                // Validate dimension constraints from ggml implementation
+                supported = (op->ne[0] == op->src[0]->ne[0]) &&              // same number of columns
+                            (op->ne[2] == op->src[0]->ne[2]) &&              // same batch size
+                            (op->ne[3] == op->src[0]->ne[3]) &&              // same outer dimension
+                            (op->src[0]->ne[1] == op->src[1]->ne[0]) &&      // src rows = index count
+                            (op->src[0]->ne[2] % op->src[1]->ne[1] == 0) &&  // batch constraint
+                            (op->src[0]->ne[3] % op->src[1]->ne[2] == 0) &&  // outer constraint
+                            (op->src[1]->ne[3] == 1);                        // indices tensor constraint
+            } else {
+                supported = false;
+            }
+            break;
+        case GGML_OP_NONE:
+            // Always support NONE operations - they represent leaf nodes (parameters, inputs, constants)
+            // No computation needed, just memory management
+            supported = true;
+            break;
+        default:
+            supported = false;
+            break;
+    }
+    // if(!supported) {
+    //     ggml_et_dump_operator_metadata(op);
+    // }
+    return supported;
+}
+
+static bool ggml_backend_et_device_supports_buft(ggml_backend_dev_t dev, ggml_backend_buffer_type_t buft) {
+    GGML_UNUSED(dev);
+    return buft->iface.get_name == ggml_backend_et_buffer_type_get_name;
+}
+
+static bool ggml_backend_et_device_offload_op(ggml_backend_dev_t dev, const ggml_tensor * op) {
+    // GET_ROWS (embedding lookup) uses a large weight (tok_embd) that lives on CPU (dev_input).
+    // The scheduler has no mechanism to cache cross-backend weight copies - it re-copies split
+    // inputs every graph_compute call. For GET_ROWS this means copying the entire embedding table
+    // (e.g. 266MB for Llama 3.1 1B) from host to device on every token, just to look up a few rows.
+    // Keep GET_ROWS on CPU and let the scheduler copy only the small result to the device.
+    // The other backends either only offload if the tensor lives on device or is large enough to
+    // justify the copy cost.
+    if (op->op == GGML_OP_GET_ROWS) {
+        return false;
+    }
+    return true;
+
+    GGML_UNUSED(dev);
+}
+
+static const struct ggml_backend_i ggml_backend_et_i = {
+    /* .get_name                = */ ggml_backend_et_get_name,
+    /* .free                    = */ ggml_backend_et_free,
+    /* .set_tensor_async        = */ ggml_backend_et_set_tensor_async,
+    /* .get_tensor_async        = */ ggml_backend_et_get_tensor_async,
+    /* .set_tensor_2d_async     = */ NULL,
+    /* .get_tensor_2d_async     = */ NULL,
+    /* .cpy_tensor_async        = */ NULL,
+    /* .synchronize             = */ ggml_backend_et_synchronize,
+    /* .graph_plan_create       = */ NULL,
+    /* .graph_plan_free         = */ NULL,
+    /* .graph_plan_update       = */ NULL,
+    /* .graph_plan_compute      = */ NULL,
+    /* .graph_compute           = */ ggml_backend_et_graph_compute,
+    /* .event_record            = */ NULL,
+    /* .event_wait              = */ NULL,
+    /* .graph_optimize          = */ NULL,
+};
+
+static const char * ggml_backend_et_device_get_name(ggml_backend_dev_t dev) {
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    return dev_ctx->name.c_str();
+}
+
+static const char * ggml_backend_et_device_get_description(ggml_backend_dev_t dev) {
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    return dev_ctx->desc.c_str();
+}
+
+static void ggml_backend_et_device_get_memory(ggml_backend_dev_t dev, size_t * free, size_t * total) {
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    // Currently getFreeMemory is not available on a runtime without server.
+    // For now, report total memory as free.
+    *free                                    = dev_ctx->total_mem;
+    *total                                   = dev_ctx->total_mem;
+}
+
+static enum ggml_backend_dev_type ggml_backend_et_device_get_type(ggml_backend_dev_t dev) {
+    GGML_UNUSED(dev);
+    return GGML_BACKEND_DEVICE_TYPE_GPU;
+}
+
+static void ggml_backend_et_device_get_props(ggml_backend_dev_t dev, struct ggml_backend_dev_props * props) {
+    GGML_UNUSED(dev);
+    props->name        = ggml_backend_et_device_get_name(dev);
+    props->description = ggml_backend_et_device_get_description(dev);
+    props->type        = ggml_backend_et_device_get_type(dev);
+    ggml_backend_et_device_get_memory(dev, &props->memory_free, &props->memory_total);
+    props->device_id = NULL;  // No PCI device ID available
+    props->caps      = {
+        /* .async                 = */ true,
+        /* .host_buffer           = */ false,
+        /* .buffer_from_host_ptr  = */ false,
+        /* .events                = */ false,
+    };
+}
+
+static ggml_backend_t ggml_backend_et_device_init_backend(ggml_backend_dev_t dev, const char * params) {
+    GGML_UNUSED(params);
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    return ggml_backend_et_init(dev_ctx->devidx);
+}
+
+static ggml_backend_buffer_type_t ggml_backend_et_device_get_buffer_type(ggml_backend_dev_t dev) {
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    return dev_ctx->buftype;
+}
+
+static ggml_backend_buffer_type_t ggml_backend_et_device_get_host_buffer_type(ggml_backend_dev_t dev) {
+    GGML_UNUSED(dev);
+    return ggml_backend_cpu_buffer_type();
+}
+
+static const struct ggml_backend_device_i ggml_backend_et_device_i = {
+    /* .get_name          = */ ggml_backend_et_device_get_name,
+    /* .get_description   = */ ggml_backend_et_device_get_description,
+    /* .get_memory        = */ ggml_backend_et_device_get_memory,
+    /* .get_type          = */ ggml_backend_et_device_get_type,
+    /* .get_props         = */ ggml_backend_et_device_get_props,
+    /* .init_backend      = */ ggml_backend_et_device_init_backend,
+    /* .get_buffer_type   = */ ggml_backend_et_device_get_buffer_type,
+    /* .get_host_buffer_type = */ ggml_backend_et_device_get_host_buffer_type,
+    /* .buffer_from_host_ptr = */ NULL,
+    /* .supports_op       = */ ggml_backend_et_device_supports_op,
+    /* .supports_buft     = */ ggml_backend_et_device_supports_buft,
+    /* .offload_op        = */ ggml_backend_et_device_offload_op,
+    /* .event_new         = */ NULL,
+    /* .event_free        = */ NULL,
+    /* .event_synchronize = */ NULL,
+};
+
+/*
+  Backend Registry.
+*/
+
+static const char * ggml_backend_et_reg_get_name(ggml_backend_reg_t reg) {
+    GGML_UNUSED(reg);
+    return GGML_ET_NAME;
+}
+
+static size_t ggml_backend_et_reg_get_device_count(ggml_backend_reg_t reg) {
+    ggml_backend_et_reg_ctx * ctx = (ggml_backend_et_reg_ctx *) reg->context;
+    return ctx->devices.size();
+}
+
+static ggml_backend_dev_t ggml_backend_et_reg_get_device(ggml_backend_reg_t reg, size_t devidx) {
+    ggml_backend_et_reg_ctx * ctx = (ggml_backend_et_reg_ctx *) reg->context;
+    if (devidx >= ctx->devices.size()) {
+        return nullptr;
+    }
+    return ctx->devices[devidx];
+}
+
+static void * ggml_backend_et_get_proc_address(ggml_backend_reg_t reg, const char * name) {
+    GGML_UNUSED(reg);
+    GGML_UNUSED(name);
+    return nullptr;
+}
+
+static const struct ggml_backend_reg_i ggml_backend_et_reg_i = {
+    /* .get_name         = */ ggml_backend_et_reg_get_name,
+    /* .get_device_count = */ ggml_backend_et_reg_get_device_count,
+    /* .get_device       = */ ggml_backend_et_reg_get_device,
+    /* .get_proc_address = */ ggml_backend_et_get_proc_address,
+};
+
+ggml_backend_reg_t ggml_backend_et_reg(void) {
+    static ggml_backend_reg_t _reg = []() -> ggml_backend_reg_t {
+        ggml_backend_et_reg_ctx * ctx = new ggml_backend_et_reg_ctx;
+
+        if (!ggml_et_driver_init()) {
+            return nullptr;
+        }
+
+        ggml_backend_reg_t r = new ggml_backend_reg{
+            /* .api_version = */ GGML_BACKEND_API_VERSION,
+            /* .iface       = */ ggml_backend_et_reg_i,
+            /* .context     = */ nullptr,  // Set later
+        };
+
+        std::vector<rt::DeviceId> rtids = ggml_et_runtime()->getDevices();
+
+        for (int i = 0; i < ggml_et_devicelayer()->getDevicesCount(); i++) {
+            ggml_backend_dev_t dev = new ggml_backend_device{
+                /* .iface   = */ ggml_backend_et_device_i,
+                /* .reg     = */ r,
+                /* .context = */ nullptr  // Set later
+            };
+
+            rt::DeviceId         rtid = rtids[i];
+            rt::DeviceProperties prop = ggml_et_runtime()->getDeviceProperties(rtid);
+
+            // Create device context.
+            ggml_backend_et_device_context * dev_ctx = new ggml_backend_et_device_context;
+            dev_ctx->devidx                          = i;
+            dev_ctx->rtid                            = rtid;
+            dev_ctx->name                            = GGML_ET_NAME + std::to_string(i);
+            dev_ctx->desc                            = "ET device " + std::to_string(i);
+            dev_ctx->total_mem                       = static_cast<size_t>(prop.memorySize_);
+            {
+                const char * env            = getenv("GGML_ET_UBERKERNEL");
+                dev_ctx->uberkernel_enabled = env && env[0] != '\0' && strcmp(env, "0") != 0;
+            }
+            // Add buffer type for device to device context.
+            ggml_backend_et_buffer_type_context * bufty_ctx = new ggml_backend_et_buffer_type_context;
+            bufty_ctx->devidx                               = i;
+            bufty_ctx->name                                 = GGML_ET_NAME + std::to_string(i);
+            dev_ctx->buftype = new ggml_backend_buffer_type{ /* .iface   = */ ggml_backend_et_buffer_type_i,
+                                                             /* .device  = */ dev,
+                                                             /* .context = */ bufty_ctx };
+
+            // Create default stream for ordered execution on this device
+            dev_ctx->default_stream = ggml_et_runtime()->createStream(rtid);
+
+            dev_ctx->trace_buffer = ggml_et_runtime()->mallocDevice(rtid, ET_TRACE_BUFFER_SIZE);
+            // Pre-size each slot's host buffers and device-side scratch so the
+            // first few graph_compute calls don't pay a malloc/grow penalty.
+            for (auto & slot : dev_ctx->uberkernel.slots) {
+                slot.insts.reserve(256);
+                slot.params_blob.reserve(1 << 20);
+                slot.device_insts_capacity  = 256 * sizeof(ggml_et_uberkernel_inst);
+                slot.device_params_capacity = 1 << 20;
+                slot.device_insts           = ggml_et_runtime()->mallocDevice(rtid, slot.device_insts_capacity);
+                slot.device_params          = ggml_et_runtime()->mallocDevice(rtid, slot.device_params_capacity);
+                if (slot.device_insts == nullptr) {
+                    slot.device_insts_capacity = 0;
+                }
+                if (slot.device_params == nullptr) {
+                    slot.device_params_capacity = 0;
+                }
+            }
+
+            dev->context = dev_ctx;
+
+            ctx->devices.push_back(dev);
+        }
+
+        r->context = ctx;
+        return r;
+    }();
+
+    return _reg;
+}
+
+ggml_guid_t ggml_backend_et_guid(void) {
+    static ggml_guid guid = { 0x4b, 0xe0, 0x72, 0x88, 0xc0, 0xf6, 0x29, 0xb4,
+                              0x79, 0x9f, 0x70, 0x68, 0x71, 0x0f, 0x6d, 0xc8 };
+    return &guid;
+}
+
+ggml_backend_t ggml_backend_et_init(size_t devidx) {
+    if (!ggml_et_driver_init()) {
+        return nullptr;
+    }
+
+    if (devidx >= (size_t) ggml_backend_et_get_device_count()) {
+        return nullptr;
+    }
+
+    ggml_backend_et_context * ctx = new ggml_backend_et_context;
+    ctx->devidx                   = (int) devidx;
+
+    ggml_backend_t backend = new ggml_backend{
+        /* .guid    = */ ggml_backend_et_guid(),
+        /* .iface   = */ ggml_backend_et_i,
+        /* .device  = */ ggml_backend_et_reg_get_device(ggml_backend_et_reg(), devidx),
+        /* .context = */ ctx,
+    };
+
+    return backend;
+}
+
+bool ggml_backend_is_et(ggml_backend_t backend) {
+    return backend != NULL && ggml_guid_matches(backend->guid, ggml_backend_et_guid());
+}
+
+int ggml_backend_et_get_device_count(void) {
+    return ggml_backend_et_reg_get_device_count(ggml_backend_et_reg());
+}
+
+void ggml_backend_et_get_device_description(int devidx, char * description, size_t description_size) {
+    if (devidx < 0 || devidx >= ggml_backend_et_get_device_count()) {
+        snprintf(description, description_size, "ET Device %d (invalid)", devidx);
+        return;
+    }
+
+    ggml_backend_dev_t               dev     = ggml_backend_et_reg_get_device(ggml_backend_et_reg(), devidx);
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    snprintf(description, description_size, "%s", dev_ctx->desc.c_str());
+}
+
+void ggml_backend_et_get_device_memory(int devidx, size_t * free, size_t * total) {
+    if (devidx < 0 || devidx >= ggml_backend_et_get_device_count()) {
+        *free  = 0;
+        *total = 0;
+        return;
+    }
+
+    ggml_backend_dev_t dev = ggml_backend_et_reg_get_device(ggml_backend_et_reg(), devidx);
+    ggml_backend_et_device_get_memory(dev, free, total);
+}
+
+ggml_backend_buffer_type_t ggml_backend_et_buffer_type(size_t dev_num) {
+    if (dev_num >= (size_t) ggml_backend_et_get_device_count()) {
+        return nullptr;
+    }
+
+    ggml_backend_dev_t               dev     = ggml_backend_et_reg_get_device(ggml_backend_et_reg(), dev_num);
+    ggml_backend_et_device_context * dev_ctx = (ggml_backend_et_device_context *) dev->context;
+    return dev_ctx->buftype;
+}
+
+ggml_backend_buffer_type_t ggml_backend_et_host_buffer_type(void) {
+    static ggml_backend_buffer_type host_buffer_type = {
+        /* .iface   = */ ggml_backend_et_buffer_type_i,
+        /* .device  = */ nullptr,
+        /* .context = */ nullptr,
+    };
+    return &host_buffer_type;
+}
+
+GGML_BACKEND_DL_IMPL(ggml_backend_et_reg)